1 | /* |
2 | * Main routine of the firmware. |
3 | * |
4 | * Copyright 2009 (C) Qi Hardware Inc., |
5 | * Author: Xiangfu Liu <xiangfu@sharism.cc> |
6 | * |
7 | * This program is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License |
9 | * version 3 as published by the Free Software Foundation. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
19 | * Boston, MA 02110-1301, USA |
20 | */ |
21 | #include "target/jz4740.h" |
22 | #include "target/configs.h" |
23 | #include "usb_boot_defines.h" |
24 | |
25 | struct fw_args *fw_args; |
26 | volatile u32 CPU_ID; |
27 | volatile u32 UART_BASE; |
28 | volatile u32 CONFIG_BAUDRATE; |
29 | volatile u8 SDRAM_BW16; |
30 | volatile u8 SDRAM_BANK4; |
31 | volatile u8 SDRAM_ROW; |
32 | volatile u8 SDRAM_COL; |
33 | volatile u8 CONFIG_MOBILE_SDRAM; |
34 | volatile u32 CFG_CPU_SPEED; |
35 | volatile u32 CFG_EXTAL; |
36 | volatile u8 PHM_DIV; |
37 | volatile u8 IS_SHARE; |
38 | |
39 | #if 0 |
40 | void test_load_args(void) |
41 | { |
42 | CPU_ID = 0x4760; |
43 | CFG_EXTAL = 12000000; |
44 | CFG_CPU_SPEED = 252000000; |
45 | PHM_DIV = 3; |
46 | fw_args->use_uart = 0; |
47 | UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000; |
48 | CONFIG_BAUDRATE = 57600; |
49 | SDRAM_BW16 = 1; |
50 | SDRAM_BANK4 = 1; |
51 | SDRAM_ROW = 13; |
52 | SDRAM_COL = 9; |
53 | CONFIG_MOBILE_SDRAM = 0; |
54 | IS_SHARE = 1; |
55 | |
56 | fw_args->debug_ops = -1; |
57 | } |
58 | #endif |
59 | |
60 | void load_args(void) |
61 | { |
62 | fw_args = (struct fw_args *)0x80002008; /* get the fw args from memory */ |
63 | CPU_ID = fw_args->cpu_id ; |
64 | CFG_EXTAL = (u32)fw_args->ext_clk * 1000000; |
65 | CFG_CPU_SPEED = (u32)fw_args->cpu_speed * CFG_EXTAL ; |
66 | if (CFG_EXTAL == 19000000) { |
67 | CFG_EXTAL = 19200000; |
68 | CFG_CPU_SPEED = 192000000; |
69 | } |
70 | PHM_DIV = fw_args->phm_div; |
71 | UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000; |
72 | CONFIG_BAUDRATE = fw_args->boudrate; |
73 | SDRAM_BW16 = fw_args->bus_width; |
74 | SDRAM_BANK4 = fw_args->bank_num; |
75 | SDRAM_ROW = fw_args->row_addr; |
76 | SDRAM_COL = fw_args->col_addr; |
77 | CONFIG_MOBILE_SDRAM = fw_args->is_mobile; |
78 | IS_SHARE = fw_args->is_busshare; |
79 | } |
80 | |
81 | void c_main(void) |
82 | { |
83 | load_args(); |
84 | |
85 | if (fw_args->debug_ops > 0) { |
86 | do_debug(); |
87 | return ; |
88 | } |
89 | |
90 | switch (CPU_ID) { |
91 | case 0x4740: |
92 | gpio_init_4740(); |
93 | pll_init_4740(); |
94 | serial_init(); |
95 | sdram_init_4740(); |
96 | break; |
97 | case 0x4760: |
98 | gpio_init_4760(); |
99 | cpm_start_all_4760(); |
100 | serial_init(); |
101 | pll_init_4760(); |
102 | sdram_init_4760(); |
103 | break; |
104 | default: |
105 | return; |
106 | } |
107 | #if 1 |
108 | serial_puts("Setup xburst CPU args as:\n"); |
109 | serial_put_hex(CPU_ID); |
110 | serial_put_hex(CFG_EXTAL); |
111 | serial_put_hex(CFG_CPU_SPEED); |
112 | serial_put_hex(PHM_DIV); |
113 | serial_put_hex(fw_args->use_uart); |
114 | serial_put_hex(CONFIG_BAUDRATE); |
115 | serial_put_hex(SDRAM_BW16); |
116 | serial_put_hex(SDRAM_BANK4); |
117 | serial_put_hex(SDRAM_ROW); |
118 | serial_put_hex(SDRAM_COL); |
119 | serial_put_hex(REG_CPM_CPCCR); |
120 | #endif |
121 | serial_puts("xburst stage1 run finish !\n"); |
122 | if (CPU_ID == 0x4760) { |
123 | __asm__ ( |
124 | "li $31, 0xbfc012e0 \n\t" |
125 | "jr $31 \n\t " |
126 | ); |
127 | } |
128 | } |
129 | |