| 1 | /* |
| 2 | * jz4730_board.h |
| 3 | * |
| 4 | * JZ4730 board definitions. |
| 5 | * |
| 6 | * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. |
| 7 | * |
| 8 | */ |
| 9 | #ifndef __JZ4730_BOARD_H__ |
| 10 | #define __JZ4730_BOARD_H__ |
| 11 | |
| 12 | /*------------------------------------------------------------------- |
| 13 | * Frequency of the external OSC in Hz. |
| 14 | */ |
| 15 | #define CFG_EXTAL 12000000 |
| 16 | |
| 17 | /*------------------------------------------------------------------- |
| 18 | * CPU speed. |
| 19 | */ |
| 20 | #define CFG_CPU_SPEED 336000000 |
| 21 | |
| 22 | /*------------------------------------------------------------------- |
| 23 | * Serial console. |
| 24 | */ |
| 25 | #define CFG_UART_BASE UART3_BASE |
| 26 | |
| 27 | #define CONFIG_BAUDRATE 9600 |
| 28 | |
| 29 | /*------------------------------------------------------------------- |
| 30 | * SDRAM info. |
| 31 | */ |
| 32 | |
| 33 | // SDRAM paramters |
| 34 | #define CFG_SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ |
| 35 | #define CFG_SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ |
| 36 | #define CFG_SDRAM_ROW 13 /* Row address: 11 to 13 */ |
| 37 | #define CFG_SDRAM_COL 9 /* Column address: 8 to 12 */ |
| 38 | #define CFG_SDRAM_CASL 2 /* CAS latency: 2 or 3 */ |
| 39 | |
| 40 | // SDRAM Timings, unit: ns |
| 41 | #define CFG_SDRAM_TRAS 45 /* RAS# Active Time */ |
| 42 | #define CFG_SDRAM_RCD 20 /* RAS# to CAS# Delay */ |
| 43 | #define CFG_SDRAM_TPC 20 /* RAS# Precharge Time */ |
| 44 | #define CFG_SDRAM_TRWL 7 /* Write Latency Time */ |
| 45 | #define CFG_SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */ |
| 46 | |
| 47 | /*------------------------------------------------------------------- |
| 48 | * Linux kernel command line. |
| 49 | */ |
| 50 | #define CFG_CMDLINE "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw init=/etc/inittab" |
| 51 | |
| 52 | #endif /* __JZ4730_BOARD_H__ */ |
| 53 | |
