Root/nandboot/include/jz4740_board.h

1/*
2 * jz4740_board.h
3 *
4 * JZ4740 board definitions.
5 *
6 * Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
7 *
8 */
9#ifndef __JZ4740_BOARD_H__
10#define __JZ4740_BOARD_H__
11
12/*-------------------------------------------------------------------
13 * NAND Boot config code
14 */
15#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 /* NAND Boot config code */
16
17/*-------------------------------------------------------------------
18 * Frequency of the external OSC in Hz.
19 */
20#define CFG_EXTAL 12000000
21
22/*-------------------------------------------------------------------
23 * CPU speed.
24 */
25#define CFG_CPU_SPEED 336000000
26
27/*-------------------------------------------------------------------
28 * Serial console.
29 */
30#define CFG_UART_BASE UART0_BASE
31
32#define CONFIG_BAUDRATE 57600
33
34/*-------------------------------------------------------------------
35 * SDRAM info.
36 */
37
38// SDRAM paramters
39#define CFG_SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
40#define CFG_SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
41#define CFG_SDRAM_ROW 13 /* Row address: 11 to 13 */
42#define CFG_SDRAM_COL 9 /* Column address: 8 to 12 */
43#define CFG_SDRAM_CASL 2 /* CAS latency: 2 or 3 */
44
45// SDRAM Timings, unit: ns
46#define CFG_SDRAM_TRAS 45 /* RAS# Active Time */
47#define CFG_SDRAM_RCD 20 /* RAS# to CAS# Delay */
48#define CFG_SDRAM_TPC 20 /* RAS# Precharge Time */
49#define CFG_SDRAM_TRWL 7 /* Write Latency Time */
50#define CFG_SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */
51
52/*-------------------------------------------------------------------
53 * Linux kernel command line.
54 */
55#define CFG_CMDLINE "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw init=/etc/inittab"
56
57#endif /* __JZ4740_BOARD_H__ */
58

Archive Download this file



interactive