| 1 | /* |
| 2 | * cpu.c |
| 3 | * |
| 4 | * CPU common routines |
| 5 | * |
| 6 | * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. |
| 7 | * Author: Peter Wei <jlwei@ingenic.cn> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | */ |
| 14 | #include <types.h> |
| 15 | |
| 16 | /* |
| 17 | * Cache Operations |
| 18 | */ |
| 19 | #define Index_Invalidate_I 0x00 |
| 20 | #define Index_Writeback_Inv_D 0x01 |
| 21 | #define Index_Invalidate_SI 0x02 |
| 22 | #define Index_Writeback_Inv_SD 0x03 |
| 23 | #define Index_Load_Tag_I 0x04 |
| 24 | #define Index_Load_Tag_D 0x05 |
| 25 | #define Index_Load_Tag_SI 0x06 |
| 26 | #define Index_Load_Tag_SD 0x07 |
| 27 | #define Index_Store_Tag_I 0x08 |
| 28 | #define Index_Store_Tag_D 0x09 |
| 29 | #define Index_Store_Tag_SI 0x0A |
| 30 | #define Index_Store_Tag_SD 0x0B |
| 31 | #define Create_Dirty_Excl_D 0x0d |
| 32 | #define Create_Dirty_Excl_SD 0x0f |
| 33 | #define Hit_Invalidate_I 0x10 |
| 34 | #define Hit_Invalidate_D 0x11 |
| 35 | #define Hit_Invalidate_SI 0x12 |
| 36 | #define Hit_Invalidate_SD 0x13 |
| 37 | #define Fill 0x14 |
| 38 | #define Hit_Writeback_Inv_D 0x15 |
| 39 | /* 0x16 is unused */ |
| 40 | #define Hit_Writeback_Inv_SD 0x17 |
| 41 | #define Hit_Writeback_I 0x18 |
| 42 | #define Hit_Writeback_D 0x19 |
| 43 | /* 0x1a is unused */ |
| 44 | #define Hit_Writeback_SD 0x1b |
| 45 | /* 0x1c is unused */ |
| 46 | /* 0x1e is unused */ |
| 47 | #define Hit_Set_Virtual_SI 0x1e |
| 48 | #define Hit_Set_Virtual_SD 0x1f |
| 49 | |
| 50 | #define CFG_DCACHE_SIZE 16384 |
| 51 | #define CFG_ICACHE_SIZE 16384 |
| 52 | #define CFG_CACHELINE_SIZE 32 |
| 53 | |
| 54 | #define K0BASE 0x80000000 |
| 55 | |
| 56 | void flush_icache_all(void) |
| 57 | { |
| 58 | unsigned int addr, t = 0; |
| 59 | |
| 60 | asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ |
| 61 | asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ |
| 62 | |
| 63 | for (addr = K0BASE; addr < K0BASE + CFG_ICACHE_SIZE; |
| 64 | addr += CFG_CACHELINE_SIZE) { |
| 65 | asm volatile ( |
| 66 | ".set mips3\n\t" |
| 67 | " cache %0, 0(%1)\n\t" |
| 68 | ".set mips2\n\t" |
| 69 | : |
| 70 | : "I" (Index_Store_Tag_I), "r"(addr)); |
| 71 | } |
| 72 | |
| 73 | /* invalicate btb */ |
| 74 | asm volatile ( |
| 75 | ".set mips32\n\t" |
| 76 | "mfc0 %0, $16, 7\n\t" |
| 77 | "nop\n\t" |
| 78 | "ori %0,2\n\t" |
| 79 | "mtc0 %0, $16, 7\n\t" |
| 80 | ".set mips2\n\t" |
| 81 | : |
| 82 | : "r" (t)); |
| 83 | } |
| 84 | |
| 85 | void flush_dcache_all(void) |
| 86 | { |
| 87 | unsigned int addr; |
| 88 | |
| 89 | for (addr = K0BASE; addr < K0BASE + CFG_DCACHE_SIZE; |
| 90 | addr += CFG_CACHELINE_SIZE) { |
| 91 | asm volatile ( |
| 92 | ".set mips3\n\t" |
| 93 | " cache %0, 0(%1)\n\t" |
| 94 | ".set mips2\n\t" |
| 95 | : |
| 96 | : "I" (Index_Writeback_Inv_D), "r"(addr)); |
| 97 | } |
| 98 | |
| 99 | asm volatile ("sync"); |
| 100 | } |
| 101 | |
| 102 | void flush_cache_all(void) |
| 103 | { |
| 104 | flush_dcache_all(); |
| 105 | flush_icache_all(); |
| 106 | } |
| 107 | |
