Root/nandboot/src/jz4730.c

1/*
2 * jz4730.c
3 *
4 * JZ4730 common routines
5 *
6 * Copyright (c) 2005-2007 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15#include <config.h>
16
17#ifdef CONFIG_JZ4730
18
19#include <jz4730.h>
20#include <jz4730_board.h>
21
22void pll_init(void)
23{
24    unsigned int nf, plcr1;
25
26    nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
27    plcr1 = ((nf-2) << CPM_PLCR1_PLL1FD_BIT) |
28        (0 << CPM_PLCR1_PLL1RD_BIT) | /* RD=0, NR=2, 1.8432 = 3.6864/2 */
29        (0 << CPM_PLCR1_PLL1OD_BIT) | /* OD=0, NO=1 */
30        (0x20 << CPM_PLCR1_PLL1ST_BIT) | /* PLL stable time */
31        CPM_PLCR1_PLL1EN; /* enable PLL */
32
33    /* Clock divisors.
34     *
35     * CFCR values: when CPM_CFCR_UCS(bit 28) is set, select external USB clock.
36     *
37     * 0x00411110 -> 1:2:2:2:2
38     * 0x00422220 -> 1:3:3:3:3
39     * 0x00433330 -> 1:4:4:4:4
40     * 0x00444440 -> 1:6:6:6:6
41     * 0x00455550 -> 1:8:8:8:8
42     * 0x00466660 -> 1:12:12:12:12
43     */
44    REG_CPM_CFCR = 0x00422220 | (((CFG_CPU_SPEED/48000000) - 1) << 25);
45
46    /* PLL out frequency */
47    REG_CPM_PLCR1 = plcr1;
48}
49
50#define MEM_CLK (CFG_CPU_SPEED / 3)
51
52/*
53 * Init SDRAM memory.
54 */
55void sdram_init(void)
56{
57    register unsigned int dmcr0, dmcr, sdmode, tmp, ns;
58
59    unsigned int cas_latency_sdmr[2] = {
60        EMC_SDMR_CAS_2,
61        EMC_SDMR_CAS_3,
62    };
63
64    unsigned int cas_latency_dmcr[2] = {
65        1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
66        2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
67    };
68
69    REG_EMC_BCR = 0; /* Disable bus release */
70    REG_EMC_RTCSR = 0; /* Disable clock for counting */
71
72    /* Fault DMCR value for mode register setting*/
73#define SDRAM_ROW0 11
74#define SDRAM_COL0 8
75#define SDRAM_BANK40 0
76
77    dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
78        ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
79        (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
80        (CFG_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
81        EMC_DMCR_EPIN |
82        cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
83
84    /* Basic DMCR value */
85    dmcr = ((CFG_SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
86        ((CFG_SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
87        (CFG_SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
88        (CFG_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
89        EMC_DMCR_EPIN |
90        cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
91
92    /* SDRAM timing */
93    ns = 1000000000 / MEM_CLK;
94    tmp = CFG_SDRAM_TRAS/ns;
95    if (tmp < 4)
96        tmp = 4;
97    if (tmp > 11)
98        tmp = 11;
99    dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
100    tmp = CFG_SDRAM_RCD/ns;
101    if (tmp > 3)
102        tmp = 3;
103    dmcr |= (tmp << EMC_DMCR_RCD_BIT);
104    tmp = CFG_SDRAM_TPC/ns;
105    if (tmp > 7)
106        tmp = 7;
107    dmcr |= (tmp << EMC_DMCR_TPC_BIT);
108    tmp = CFG_SDRAM_TRWL/ns;
109    if (tmp > 3)
110        tmp = 3;
111    dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
112    tmp = (CFG_SDRAM_TRAS + CFG_SDRAM_TPC)/ns;
113    if (tmp > 14)
114        tmp = 14;
115    dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
116
117    /* SDRAM mode value */
118    sdmode = EMC_SDMR_BT_SEQ |
119         EMC_SDMR_OM_NORMAL |
120         EMC_SDMR_BL_4 |
121         cas_latency_sdmr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
122    if (CFG_SDRAM_BW16)
123        sdmode <<= 1;
124    else
125        sdmode <<= 2;
126
127    /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
128    REG_EMC_DMCR = dmcr;
129    REG8(EMC_SDMR0|sdmode) = 0;
130    REG8(EMC_SDMR1|sdmode) = 0;
131
132    /* Wait for precharge, > 200us */
133    tmp = (CFG_CPU_SPEED / 1000000) * 1000;
134    while (tmp--);
135
136    /* Stage 2. Enable auto-refresh */
137    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
138
139    tmp = CFG_SDRAM_TREF/ns;
140    tmp = tmp/64 + 1;
141    if (tmp > 0xff) tmp = 0xff;
142    REG_EMC_RTCOR = tmp;
143    REG_EMC_RTCNT = 0;
144    REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
145
146    /* Wait for number of auto-refresh cycles */
147    tmp = (CFG_CPU_SPEED / 1000000) * 1000;
148    while (tmp--);
149
150    /* Stage 3. Mode Register Set */
151    REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
152    REG8(EMC_SDMR0|sdmode) = 0;
153    REG8(EMC_SDMR1|sdmode) = 0;
154
155        /* Set back to the ture basic DMCR value */
156    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
157
158    /* everything is ok now */
159}
160
161#endif /* CONFIG_JZ4730 */
162

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