| 1 | /* |
| 2 | * jz4740.c |
| 3 | * |
| 4 | * JZ4740 common routines |
| 5 | * |
| 6 | * Copyright (c) 2005-2008 Ingenic Semiconductor Inc. |
| 7 | * Author: Peter Wei <jlwei@ingenic.cn> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #include <config.h> |
| 16 | |
| 17 | #ifdef CONFIG_JZ4740 |
| 18 | |
| 19 | #include <jz4740.h> |
| 20 | #include <jz4740_board.h> |
| 21 | |
| 22 | /* PLL output clock = EXTAL * NF / (NR * NO) |
| 23 | * |
| 24 | * NF = FD + 2, NR = RD + 2 |
| 25 | * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3) |
| 26 | */ |
| 27 | void pll_init(void) |
| 28 | { |
| 29 | register unsigned int cfcr, plcr1; |
| 30 | int n2FR[33] = { |
| 31 | 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, |
| 32 | 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, |
| 33 | 9 |
| 34 | }; |
| 35 | int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:M:L */ |
| 36 | int nf, pllout2; |
| 37 | |
| 38 | cfcr = CPM_CPCCR_CLKOEN | |
| 39 | CPM_CPCCR_PCS | |
| 40 | (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | |
| 41 | (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | |
| 42 | (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | |
| 43 | (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | |
| 44 | (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT); |
| 45 | |
| 46 | pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); |
| 47 | |
| 48 | /* Init USB Host clock, pllout2 must be n*48MHz */ |
| 49 | REG_CPM_UHCCDR = pllout2 / 48000000 - 1; |
| 50 | |
| 51 | nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; |
| 52 | plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ |
| 53 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
| 54 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
| 55 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ |
| 56 | CPM_CPPCR_PLLEN; /* enable PLL */ |
| 57 | |
| 58 | /* init PLL */ |
| 59 | REG_CPM_CPCCR = cfcr; |
| 60 | REG_CPM_CPPCR = plcr1; |
| 61 | } |
| 62 | |
| 63 | /* |
| 64 | * Init SDRAM memory. |
| 65 | */ |
| 66 | void sdram_init(void) |
| 67 | { |
| 68 | register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; |
| 69 | |
| 70 | unsigned int cas_latency_sdmr[2] = { |
| 71 | EMC_SDMR_CAS_2, |
| 72 | EMC_SDMR_CAS_3, |
| 73 | }; |
| 74 | |
| 75 | unsigned int cas_latency_dmcr[2] = { |
| 76 | 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ |
| 77 | 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ |
| 78 | }; |
| 79 | |
| 80 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| 81 | |
| 82 | cpu_clk = CFG_CPU_SPEED; |
| 83 | mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; |
| 84 | |
| 85 | REG_EMC_BCR = 0; /* Disable bus release */ |
| 86 | REG_EMC_RTCSR = 0; /* Disable clock for counting */ |
| 87 | |
| 88 | /* Fault DMCR value for mode register setting*/ |
| 89 | #define SDRAM_ROW0 11 |
| 90 | #define SDRAM_COL0 8 |
| 91 | #define SDRAM_BANK40 0 |
| 92 | |
| 93 | dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | |
| 94 | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | |
| 95 | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | |
| 96 | (CFG_SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
| 97 | EMC_DMCR_EPIN | |
| 98 | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)]; |
| 99 | |
| 100 | /* Basic DMCR value */ |
| 101 | dmcr = ((CFG_SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | |
| 102 | ((CFG_SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | |
| 103 | (CFG_SDRAM_BANK4<<EMC_DMCR_BA_BIT) | |
| 104 | (CFG_SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
| 105 | EMC_DMCR_EPIN | |
| 106 | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)]; |
| 107 | |
| 108 | /* SDRAM timimg */ |
| 109 | ns = 1000000000 / mem_clk; |
| 110 | tmp = CFG_SDRAM_TRAS/ns; |
| 111 | if (tmp < 4) tmp = 4; |
| 112 | if (tmp > 11) tmp = 11; |
| 113 | dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); |
| 114 | tmp = CFG_SDRAM_RCD/ns; |
| 115 | if (tmp > 3) tmp = 3; |
| 116 | dmcr |= (tmp << EMC_DMCR_RCD_BIT); |
| 117 | tmp = CFG_SDRAM_TPC/ns; |
| 118 | if (tmp > 7) tmp = 7; |
| 119 | dmcr |= (tmp << EMC_DMCR_TPC_BIT); |
| 120 | tmp = CFG_SDRAM_TRWL/ns; |
| 121 | if (tmp > 3) tmp = 3; |
| 122 | dmcr |= (tmp << EMC_DMCR_TRWL_BIT); |
| 123 | tmp = (CFG_SDRAM_TRAS + CFG_SDRAM_TPC)/ns; |
| 124 | if (tmp > 14) tmp = 14; |
| 125 | dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); |
| 126 | |
| 127 | /* SDRAM mode value */ |
| 128 | sdmode = EMC_SDMR_BT_SEQ | |
| 129 | EMC_SDMR_OM_NORMAL | |
| 130 | EMC_SDMR_BL_4 | |
| 131 | cas_latency_sdmr[((CFG_SDRAM_CASL == 3) ? 1 : 0)]; |
| 132 | |
| 133 | /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ |
| 134 | REG_EMC_DMCR = dmcr; |
| 135 | REG8(EMC_SDMR0|sdmode) = 0; |
| 136 | |
| 137 | /* Wait for precharge, > 200us */ |
| 138 | tmp = (cpu_clk / 1000000) * 1000; |
| 139 | while (tmp--); |
| 140 | |
| 141 | /* Stage 2. Enable auto-refresh */ |
| 142 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; |
| 143 | |
| 144 | tmp = CFG_SDRAM_TREF/ns; |
| 145 | tmp = tmp/64 + 1; |
| 146 | if (tmp > 0xff) tmp = 0xff; |
| 147 | REG_EMC_RTCOR = tmp; |
| 148 | REG_EMC_RTCNT = 0; |
| 149 | REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ |
| 150 | |
| 151 | /* Wait for number of auto-refresh cycles */ |
| 152 | tmp = (cpu_clk / 1000000) * 1000; |
| 153 | while (tmp--); |
| 154 | |
| 155 | /* Stage 3. Mode Register Set */ |
| 156 | REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
| 157 | REG8(EMC_SDMR0|sdmode) = 0; |
| 158 | |
| 159 | /* Set back to basic DMCR value */ |
| 160 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
| 161 | |
| 162 | /* everything is ok now */ |
| 163 | } |
| 164 | |
| 165 | #endif /* CONFIG_JZ4740 */ |
| 166 | |
