Root/nandprog/include/configs.h

1#ifndef __CONFIGS_H__
2#define __CONFIGS_H__
3
4#include "include.h"
5
6np_data config_list[]=
7{
8    {
9        //No 0
10        //The config for jz4730 uboot
11        .pt = JZ4730,
12        .et = HARDHM, //HW HM ECC
13        .ep = 0, //ecc position index 0
14        .bw = 8,
15        .ps = 2048,
16        .os = 64,
17        .ppb = 64,
18        .rc = 3,
19        .bbp = 0,
20        .bba = 0,
21
22        .ebase = 0x13010000,
23        .dport = 0x14000000,
24        .gport = 0,
25        .bm_ms = 0x100,
26        .pm_ms = 0xb0000,
27        .gm_ms = 0,
28        .ap_offset = 0x80000,
29        .cp_offset = 0x40000,
30
31        .nand_init = nand_init_4730,
32        .nand_erase = nand_erase_4730,
33        .nand_program = nand_program_4730,
34        .nand_read = nand_read_4730,
35        .nand_read_oob = nand_read_oob_4730,
36        .nand_block_markbad = nand_block_markbad,
37        .nand_check = nand_check_cmp,
38        .nand_check_block = nand_check_block,
39        .nand_select = chip_select_4730,
40    },
41
42    {
43        //No 1
44        //The config for jz4730 linux fs
45
46        .pt = JZ4730,
47        .et = HARDHM, //HW HM ECC
48        .ep = 1, //ecc position index 1
49        .bw = 8,
50        .ps = 2048,
51        .os = 64,
52        .ppb = 64,
53        .rc = 3,
54        .bbp = 0,
55        .bba = 0,
56
57        .ebase = 0x13010000,
58        .dport = 0x14000000,
59        .gport = 0,
60        .bm_ms = 0x100,
61        .pm_ms = 0xb0000,
62        .gm_ms = 0,
63        .ap_offset = 0x80000,
64        .cp_offset = 0x40000,
65
66        .nand_init = nand_init_4730,
67        .nand_erase = nand_erase_4730,
68        .nand_program = nand_program_4730,
69        .nand_read = nand_read_4730,
70        .nand_read_oob = nand_read_oob_4730,
71        .nand_block_markbad = nand_block_markbad,
72        .nand_check = nand_check_cmp,
73        .nand_check_block = nand_check_block,
74        .nand_select = chip_select_4730,
75
76    },
77
78    {
79        //No 2
80        //The config for jz4730 ucos
81        .pt = JZ4730,
82        .et = HARDHM, //HW HM ECC
83        .ep = 1, //need modify
84        .bw = 8,
85        .ps = 2048,
86        .os = 64,
87        .ppb = 64,
88        .rc = 3,
89        .bbp = 0, //need modify
90        .bba = 0, //need modify
91
92        //do not need modify
93        .ebase = 0x13010000,
94        .dport = 0x14000000,
95        .gport = 0,
96        .bm_ms = 0x100,
97        .pm_ms = 0xb0000,
98        .gm_ms = 0,
99        .ap_offset = 0x80000,
100        .cp_offset = 0x40000,
101        
102        .nand_init = nand_init_4730,
103        .nand_erase = nand_erase_4730,
104        .nand_program = nand_program_4730,
105        .nand_read = nand_read_4730,
106        .nand_read_oob = nand_read_oob_4730,
107        .nand_block_markbad = nand_block_markbad,
108        .nand_check = nand_check_cmp,
109        .nand_check_block = nand_check_block,
110        .nand_select = chip_select_4730,
111
112    },
113    {
114        //No 3
115        //The config for jz4730 wince
116        .pt = JZ4730,
117        .et = HARDHM, //HW HM ECC
118        .ep = 1, //need modify
119        .bw = 8,
120        .ps = 2048,
121        .os = 64,
122        .ppb = 64,
123        .rc = 3,
124        .bbp = 0, //need modify
125        .bba = 0, //need modify
126
127        //do not need modify
128        .ebase = 0x13010000,
129        .dport = 0x14000000,
130        .gport = 0,
131        .bm_ms = 0x100,
132        .pm_ms = 0xb0000,
133        .gm_ms = 0,
134        .ap_offset = 0x80000,
135        .cp_offset = 0x40000,
136        
137        .nand_init = nand_init_4730,
138        .nand_erase = nand_erase_4730,
139        .nand_program = nand_program_4730,
140        .nand_read = nand_read_4730,
141        .nand_read_oob = nand_read_oob_4730,
142        .nand_block_markbad = nand_block_markbad,
143        .nand_check = nand_check_cmp,
144        .nand_check_block = nand_check_block,
145        .nand_select = chip_select_4730,
146
147    },
148
149    {
150        //No 4
151        //The config for jz4740 uboot use HW RS
152        .pt = JZ4740,
153        .et = HARDRS, //HW HM ECC
154        .ep = 2, //need modify
155        .bw = 8,
156        .ps = 2048,
157        .os = 64,
158        .ppb = 128,
159        .rc = 3,
160        .bbp = 0, //need modify
161        .bba = 0, //need modify
162
163        //do not need modify
164        .ebase = 0x13010000,
165        .dport = 0x18000000,
166        .gport = 0x10010000,
167        .bm_ms = 0x100,
168        .pm_ms = 0x20000,
169        .gm_ms = 0x500,
170        .ap_offset = 0x10000,
171        .cp_offset = 0x8000,
172        
173        .nand_init = nand_init_4740,
174        .nand_erase = nand_erase_4740,
175        .nand_program = nand_program_4740,
176        .nand_read = nand_read_4740_rs,
177        .nand_read_oob = nand_read_oob_4740,
178        .nand_block_markbad = nand_block_markbad_4740,
179        .nand_check = nand_check_cmp,
180        .nand_check_block = nand_check_block_4740,
181        .nand_select = chip_select_4740,
182
183    },
184
185    {
186        //No 5
187        //The config for jz4740 linux use HW RS
188        .pt = JZ4740,
189        .et = HARDRS, //HW HM ECC
190        .ep = 3, //need modify
191        .bw = 8,
192        .ps = 2048,
193        .os = 64,
194        .ppb = 128,
195        .rc = 3,
196        .bbp = 1, //need modify
197        .bba = 0, //need modify
198
199        //do not need modify
200        .ebase = 0x13010000,
201        .dport = 0x18000000,
202        .gport = 0x10010000,
203        .bm_ms = 0x100,
204        .pm_ms = 0x20000,
205        .gm_ms = 0x500,
206        .ap_offset = 0x10000,
207        .cp_offset = 0x8000,
208        
209        .nand_init = nand_init_4740,
210        .nand_fini = nand_fini_4740,
211        .nand_erase = nand_erase_4740,
212        .nand_program = nand_program_4740,
213        .nand_read = nand_read_4740_rs,
214        .nand_read_oob = nand_read_oob_4740,
215        .nand_block_markbad = nand_block_markbad_4740,
216        .nand_check = nand_check_cmp,
217        .nand_check_block = nand_check_block_4740,
218        .nand_select = chip_select_4740,
219
220    },
221
222    {
223        //No 6
224        //The config for jz4740 linux use HW HM
225        .pt = JZ4740,
226        .et = HARDHM, //HW HM ECC
227        .ep = 1, //need modify
228        .bw = 8,
229        .ps = 2048,
230        .os = 64,
231        .ppb = 128,
232        .rc = 3,
233        .bbp = 0, //need modify
234        .bba = 0, //need modify
235
236        //do not need modify
237        .ebase = 0x13010000,
238        .dport = 0x18000000,
239        .gport = 0x10010000,
240        .bm_ms = 0x100,
241        .pm_ms = 0x20000,
242        .gm_ms = 0x500,
243        .ap_offset = 0x10000,
244        .cp_offset = 0x8000,
245
246        .nand_init = nand_init_4740,
247        .nand_erase = nand_erase_4740,
248        .nand_program = nand_program_4740,
249        .nand_read = nand_read_4740_hm,
250        .nand_read_oob = nand_read_oob_4740,
251        .nand_block_markbad = nand_block_markbad_4740,
252        .nand_check = nand_check_cmp,
253        .nand_check_block = nand_check_block_4740,
254        .nand_select = chip_select_4740,
255
256    },
257
258    {
259        //No 7
260        //The config for jz4740 ucos use HW RS
261        .pt = JZ4740,
262        .et = HARDRS, //HW HM ECC
263// .ep = 3, //need modify
264        .bw = 8,
265        .ps = 2048,
266        .os = 64,
267        .ppb = 128,
268        .rc = 3,
269// .bbp = 0, //need modify
270// .bba = 0, //need modify
271
272        //do not need modify
273        .ebase = 0x13010000,
274        .dport = 0x18000000,
275        .gport = 0x10010000,
276        .bm_ms = 0x100,
277        .pm_ms = 0x20000,
278        .gm_ms = 0x500,
279        .ap_offset = 0x10000,
280        .cp_offset = 0x8000,
281        
282        .nand_init = nand_init_4740,
283        .nand_erase = nand_erase_4740,
284        .nand_program = nand_program_4740,
285        .nand_read = nand_read_4740_rs,
286        .nand_read_oob = nand_read_oob_4740,
287        .nand_block_markbad = nand_block_markbad_4740,
288        .nand_check = nand_check_cmp,
289        .nand_check_block = nand_check_block_4740,
290        .nand_select = chip_select_4740,
291
292    },
293
294    {
295        //No 8
296        //The config for jz4740 ucos use HW HM
297        .pt = JZ4740,
298        .et = HARDHM, //HW HM ECC
299// .ep = 3, //need modify
300        .bw = 8,
301        .ps = 2048,
302        .os = 64,
303        .ppb = 128,
304        .rc = 3,
305// .bbp = 0, //need modify
306// .bba = 0, //need modify
307
308        //do not need modify
309        .ebase = 0x13010000,
310        .dport = 0x18000000,
311        .gport = 0x10010000,
312        .bm_ms = 0x100,
313        .pm_ms = 0x20000,
314        .gm_ms = 0x500,
315        .ap_offset = 0x10000,
316        .cp_offset = 0x8000,
317        
318        .nand_init = nand_init_4740,
319        .nand_erase = nand_erase_4740,
320        .nand_program = nand_program_4740,
321        .nand_read = nand_read_4740_hm,
322        .nand_read_oob = nand_read_oob_4740,
323        .nand_block_markbad = nand_block_markbad_4740,
324        .nand_check = nand_check_cmp,
325        .nand_check_block = nand_check_block_4740,
326        .nand_select = chip_select_4740,
327
328    },
329
330    {
331        //No 9
332        //The config for jz4740 wince use HW RS
333        .pt = JZ4740,
334        .et = HARDRS, //HW HM ECC
335// .ep = 3, //need modify
336        .bw = 8,
337        .ps = 2048,
338        .os = 64,
339        .ppb = 128,
340        .rc = 3,
341// .bbp = 0, //need modify
342// .bba = 0, //need modify
343
344        //do not need modify
345        .ebase = 0x13010000,
346        .dport = 0x18000000,
347        .gport = 0x10010000,
348        .bm_ms = 0x100,
349        .pm_ms = 0x20000,
350        .gm_ms = 0x500,
351        .ap_offset = 0x10000,
352        .cp_offset = 0x8000,
353        
354        .nand_init = nand_init_4740,
355        .nand_erase = nand_erase_4740,
356        .nand_program = nand_program_4740,
357        .nand_read = nand_read_4740_rs,
358        .nand_read_oob = nand_read_oob_4740,
359        .nand_block_markbad = nand_block_markbad_4740,
360        .nand_check = nand_check_cmp,
361        .nand_check_block = nand_check_block_4740,
362        .nand_select = chip_select_4740,
363
364    },
365
366    {
367        //No 10
368        //The config for jz4740 wince use HW RS
369        .pt = JZ4740,
370        .et = HARDHM, //HW HM ECC
371// .ep = 3, //need modify
372        .bw = 8,
373        .ps = 2048,
374        .os = 64,
375        .ppb = 128,
376        .rc = 3,
377// .bbp = 0, //need modify
378// .bba = 0, //need modify
379
380        //do not need modify
381        .ebase = 0x13010000,
382        .dport = 0x18000000,
383        .gport = 0x10010000,
384        .bm_ms = 0x100,
385        .pm_ms = 0x20000,
386        .gm_ms = 0x500,
387        .ap_offset = 0x10000,
388        .cp_offset = 0x8000,
389        
390        .nand_init = nand_init_4740,
391        .nand_erase = nand_erase_4740,
392        .nand_program = nand_program_4740,
393        .nand_read = nand_read_4740_hm,
394        .nand_read_oob = nand_read_oob_4740,
395        .nand_block_markbad = nand_block_markbad_4740,
396        .nand_check = nand_check_cmp,
397        .nand_check_block = nand_check_block_4740,
398        .nand_select = chip_select_4740,
399
400    },
401
402
403};
404
405
406#endif
407

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