| 1 | /* |
| 2 | * jz4730.h |
| 3 | * |
| 4 | * Registers definition of the JZ4730 CPU. |
| 5 | * |
| 6 | * Copyright (c) 2005-2007 Ingenic Semiconductor Inc. |
| 7 | * |
| 8 | * This program is free software. |
| 9 | */ |
| 10 | #ifndef __JZ4730_H__ |
| 11 | #define __JZ4730_H__ |
| 12 | |
| 13 | #ifndef __ASSEMBLY__ |
| 14 | |
| 15 | #define u32 unsigned int |
| 16 | #define u16 unsigned short |
| 17 | #define u8 unsigned char |
| 18 | |
| 19 | #define REG8(addr) *((volatile u8 *)(addr)) |
| 20 | #define REG16(addr) *((volatile u16 *)(addr)) |
| 21 | #define REG32(addr) *((volatile u32 *)(addr)) |
| 22 | |
| 23 | #else |
| 24 | |
| 25 | #define REG8(addr) (addr) |
| 26 | #define REG16(addr) (addr) |
| 27 | #define REG32(addr) (addr) |
| 28 | |
| 29 | #endif /* !ASSEMBLY */ |
| 30 | |
| 31 | #define HARB_BASE 0xB3000000 |
| 32 | //#define EMC_BASE 0xB3010000 |
| 33 | #define DMAC_BASE 0xB3020000 |
| 34 | #define UHC_BASE 0xB3030000 |
| 35 | #define UDC_BASE 0xB3040000 |
| 36 | #define LCD_BASE 0xB3050000 |
| 37 | #define CIM_BASE 0xB3060000 |
| 38 | #define ETH_BASE 0xB3100000 |
| 39 | #define NBM_BASE 0xB3F00000 |
| 40 | |
| 41 | #define CPM_BASE 0xB0000000 |
| 42 | #define INTC_BASE 0xB0001000 |
| 43 | #define OST_BASE 0xB0002000 |
| 44 | #define RTC_BASE 0xB0003000 |
| 45 | #define WDT_BASE 0xB0004000 |
| 46 | #define GPIO_BASE 0xB0010000 |
| 47 | #define AIC_BASE 0xB0020000 |
| 48 | #define MSC_BASE 0xB0021000 |
| 49 | #define UART0_BASE 0xB0030000 |
| 50 | #define UART1_BASE 0xB0031000 |
| 51 | #define UART2_BASE 0xB0032000 |
| 52 | #define UART3_BASE 0xB0033000 |
| 53 | #define FIR_BASE 0xB0040000 |
| 54 | #define SCC_BASE 0xB0041000 |
| 55 | #define SCC0_BASE 0xB0041000 |
| 56 | #define I2C_BASE 0xB0042000 |
| 57 | #define SSI_BASE 0xB0043000 |
| 58 | #define SCC1_BASE 0xB0044000 |
| 59 | #define PWM0_BASE 0xB0050000 |
| 60 | #define PWM1_BASE 0xB0051000 |
| 61 | #define DES_BASE 0xB0060000 |
| 62 | #define UPRT_BASE 0xB0061000 |
| 63 | #define KBC_BASE 0xB0062000 |
| 64 | |
| 65 | |
| 66 | |
| 67 | |
| 68 | /************************************************************************* |
| 69 | * MSC |
| 70 | *************************************************************************/ |
| 71 | #define MSC_STRPCL (MSC_BASE + 0x000) |
| 72 | #define MSC_STAT (MSC_BASE + 0x004) |
| 73 | #define MSC_CLKRT (MSC_BASE + 0x008) |
| 74 | #define MSC_CMDAT (MSC_BASE + 0x00C) |
| 75 | #define MSC_RESTO (MSC_BASE + 0x010) |
| 76 | #define MSC_RDTO (MSC_BASE + 0x014) |
| 77 | #define MSC_BLKLEN (MSC_BASE + 0x018) |
| 78 | #define MSC_NOB (MSC_BASE + 0x01C) |
| 79 | #define MSC_SNOB (MSC_BASE + 0x020) |
| 80 | #define MSC_IMASK (MSC_BASE + 0x024) |
| 81 | #define MSC_IREG (MSC_BASE + 0x028) |
| 82 | #define MSC_CMD (MSC_BASE + 0x02C) |
| 83 | #define MSC_ARG (MSC_BASE + 0x030) |
| 84 | #define MSC_RES (MSC_BASE + 0x034) |
| 85 | #define MSC_RXFIFO (MSC_BASE + 0x038) |
| 86 | #define MSC_TXFIFO (MSC_BASE + 0x03C) |
| 87 | |
| 88 | #define REG_MSC_STRPCL REG16(MSC_STRPCL) |
| 89 | #define REG_MSC_STAT REG32(MSC_STAT) |
| 90 | #define REG_MSC_CLKRT REG16(MSC_CLKRT) |
| 91 | #define REG_MSC_CMDAT REG32(MSC_CMDAT) |
| 92 | #define REG_MSC_RESTO REG16(MSC_RESTO) |
| 93 | #define REG_MSC_RDTO REG16(MSC_RDTO) |
| 94 | #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) |
| 95 | #define REG_MSC_NOB REG16(MSC_NOB) |
| 96 | #define REG_MSC_SNOB REG16(MSC_SNOB) |
| 97 | #define REG_MSC_IMASK REG16(MSC_IMASK) |
| 98 | #define REG_MSC_IREG REG16(MSC_IREG) |
| 99 | #define REG_MSC_CMD REG8(MSC_CMD) |
| 100 | #define REG_MSC_ARG REG32(MSC_ARG) |
| 101 | #define REG_MSC_RES REG16(MSC_RES) |
| 102 | #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) |
| 103 | #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) |
| 104 | |
| 105 | /* MSC Clock and Control Register (MSC_STRPCL) */ |
| 106 | |
| 107 | #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) |
| 108 | #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) |
| 109 | #define MSC_STRPCL_START_READWAIT (1 << 5) |
| 110 | #define MSC_STRPCL_STOP_READWAIT (1 << 4) |
| 111 | #define MSC_STRPCL_RESET (1 << 3) |
| 112 | #define MSC_STRPCL_START_OP (1 << 2) |
| 113 | #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 |
| 114 | #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) |
| 115 | #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ |
| 116 | #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ |
| 117 | |
| 118 | /* MSC Status Register (MSC_STAT) */ |
| 119 | |
| 120 | #define MSC_STAT_IS_RESETTING (1 << 15) |
| 121 | #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) |
| 122 | #define MSC_STAT_PRG_DONE (1 << 13) |
| 123 | #define MSC_STAT_DATA_TRAN_DONE (1 << 12) |
| 124 | #define MSC_STAT_END_CMD_RES (1 << 11) |
| 125 | #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) |
| 126 | #define MSC_STAT_IS_READWAIT (1 << 9) |
| 127 | #define MSC_STAT_CLK_EN (1 << 8) |
| 128 | #define MSC_STAT_DATA_FIFO_FULL (1 << 7) |
| 129 | #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) |
| 130 | #define MSC_STAT_CRC_RES_ERR (1 << 5) |
| 131 | #define MSC_STAT_CRC_READ_ERROR (1 << 4) |
| 132 | #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 |
| 133 | #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) |
| 134 | #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ |
| 135 | #define MSC_STAT_CRC_WRITE_ERROR_YES (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ |
| 136 | #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ |
| 137 | #define MSC_STAT_TIME_OUT_RES (1 << 1) |
| 138 | #define MSC_STAT_TIME_OUT_READ (1 << 0) |
| 139 | |
| 140 | /* MSC Bus Clock Control Register (MSC_CLKRT) */ |
| 141 | |
| 142 | #define MSC_CLKRT_CLK_RATE_BIT 0 |
| 143 | #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) |
| 144 | #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ |
| 145 | #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ |
| 146 | #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ |
| 147 | #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ |
| 148 | #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ |
| 149 | #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ |
| 150 | #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ |
| 151 | #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ |
| 152 | |
| 153 | /* MSC Command Sequence Control Register (MSC_CMDAT) */ |
| 154 | |
| 155 | #define MSC_CMDAT_IO_ABORT (1 << 11) |
| 156 | #define MSC_CMDAT_BUS_WIDTH_BIT 9 |
| 157 | #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 158 | #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ |
| 159 | #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ |
| 160 | #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 161 | #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) |
| 162 | #define MSC_CMDAT_DMA_EN (1 << 8) |
| 163 | #define MSC_CMDAT_INIT (1 << 7) |
| 164 | #define MSC_CMDAT_BUSY (1 << 6) |
| 165 | #define MSC_CMDAT_STREAM_BLOCK (1 << 5) |
| 166 | #define MSC_CMDAT_WRITE_READ (1 << 4) |
| 167 | #define MSC_CMDAT_DATA_EN (1 << 3) |
| 168 | #define MSC_CMDAT_RESPONSE_FORMAT_BIT 0 |
| 169 | #define MSC_CMDAT_RESPONSE_FORMAT_MASK (0x7 << MSC_CMDAT_RESPONSE_FORMAT_BIT) |
| 170 | #define MSC_CMDAT_RESPONSE_FORMAT_NONE (0x0 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* No response */ |
| 171 | #define MSC_CMDAT_RESPONSE_FORMAT_R1 (0x1 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R1 and R1b */ |
| 172 | #define MSC_CMDAT_RESPONSE_FORMAT_R2 (0x2 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R2 */ |
| 173 | #define MSC_CMDAT_RESPONSE_FORMAT_R3 (0x3 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R3 */ |
| 174 | #define MSC_CMDAT_RESPONSE_FORMAT_R4 (0x4 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R4 */ |
| 175 | #define MSC_CMDAT_RESPONSE_FORMAT_R5 (0x5 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R5 */ |
| 176 | #define MSC_CMDAT_RESPONSE_FORMAT_R6 (0x6 << MSC_CMDAT_RESPONSE_FORMAT_BIT) /* Format R6 */ |
| 177 | |
| 178 | #define CMDAT_DMA_EN (1 << 8) |
| 179 | #define CMDAT_INIT (1 << 7) |
| 180 | #define CMDAT_BUSY (1 << 6) |
| 181 | #define CMDAT_STREAM (1 << 5) |
| 182 | #define CMDAT_WRITE (1 << 4) |
| 183 | #define CMDAT_DATA_EN (1 << 3) |
| 184 | |
| 185 | /* MSC Interrupts Mask Register (MSC_IMASK) */ |
| 186 | |
| 187 | #define MSC_IMASK_SDIO (1 << 7) |
| 188 | #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) |
| 189 | #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) |
| 190 | #define MSC_IMASK_END_CMD_RES (1 << 2) |
| 191 | #define MSC_IMASK_PRG_DONE (1 << 1) |
| 192 | #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) |
| 193 | |
| 194 | /* MSC Interrupts Status Register (MSC_IREG) */ |
| 195 | |
| 196 | #define MSC_IREG_SDIO (1 << 7) |
| 197 | #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) |
| 198 | #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) |
| 199 | #define MSC_IREG_END_CMD_RES (1 << 2) |
| 200 | #define MSC_IREG_PRG_DONE (1 << 1) |
| 201 | #define MSC_IREG_DATA_TRAN_DONE (1 << 0) |
| 202 | |
| 203 | |
| 204 | |
| 205 | |
| 206 | /************************************************************************* |
| 207 | * RTC |
| 208 | *************************************************************************/ |
| 209 | #define RTC_RCR (RTC_BASE + 0x00) |
| 210 | #define RTC_RSR (RTC_BASE + 0x04) |
| 211 | #define RTC_RSAR (RTC_BASE + 0x08) |
| 212 | #define RTC_RGR (RTC_BASE + 0x0c) |
| 213 | |
| 214 | #define REG_RTC_RCR REG32(RTC_RCR) |
| 215 | #define REG_RTC_RSR REG32(RTC_RSR) |
| 216 | #define REG_RTC_RSAR REG32(RTC_RSAR) |
| 217 | #define REG_RTC_RGR REG32(RTC_RGR) |
| 218 | |
| 219 | #define RTC_RCR_HZ (1 << 6) |
| 220 | #define RTC_RCR_HZIE (1 << 5) |
| 221 | #define RTC_RCR_AF (1 << 4) |
| 222 | #define RTC_RCR_AIE (1 << 3) |
| 223 | #define RTC_RCR_AE (1 << 2) |
| 224 | #define RTC_RCR_START (1 << 0) |
| 225 | |
| 226 | #define RTC_RGR_LOCK (1 << 31) |
| 227 | #define RTC_RGR_ADJ_BIT 16 |
| 228 | #define RTC_RGR_ADJ_MASK (0x3ff << RTC_RGR_ADJ_BIT) |
| 229 | #define RTC_RGR_DIV_BIT 0 |
| 230 | #define RTC_REG_DIV_MASK (0xff << RTC_RGR_DIV_BIT) |
| 231 | |
| 232 | |
| 233 | |
| 234 | |
| 235 | /************************************************************************* |
| 236 | * FIR |
| 237 | *************************************************************************/ |
| 238 | #define FIR_TDR (FIR_BASE + 0x000) |
| 239 | #define FIR_RDR (FIR_BASE + 0x004) |
| 240 | #define FIR_TFLR (FIR_BASE + 0x008) |
| 241 | #define FIR_AR (FIR_BASE + 0x00C) |
| 242 | #define FIR_CR1 (FIR_BASE + 0x010) |
| 243 | #define FIR_CR2 (FIR_BASE + 0x014) |
| 244 | #define FIR_SR (FIR_BASE + 0x018) |
| 245 | |
| 246 | #define REG_FIR_TDR REG8(FIR_TDR) |
| 247 | #define REG_FIR_RDR REG8(FIR_RDR) |
| 248 | #define REG_FIR_TFLR REG16(FIR_TFLR) |
| 249 | #define REG_FIR_AR REG8(FIR_AR) |
| 250 | #define REG_FIR_CR1 REG8(FIR_CR1) |
| 251 | #define REG_FIR_CR2 REG16(FIR_CR2) |
| 252 | #define REG_FIR_SR REG16(FIR_SR) |
| 253 | |
| 254 | /* FIR Control Register 1 (FIR_CR1) */ |
| 255 | |
| 256 | #define FIR_CR1_FIRUE (1 << 7) |
| 257 | #define FIR_CR1_ACE (1 << 6) |
| 258 | #define FIR_CR1_EOUS (1 << 5) |
| 259 | #define FIR_CR1_TIIE (1 << 4) |
| 260 | #define FIR_CR1_TFIE (1 << 3) |
| 261 | #define FIR_CR1_RFIE (1 << 2) |
| 262 | #define FIR_CR1_TXE (1 << 1) |
| 263 | #define FIR_CR1_RXE (1 << 0) |
| 264 | |
| 265 | /* FIR Control Register 2 (FIR_CR2) */ |
| 266 | |
| 267 | #define FIR_CR2_SIPE (1 << 10) |
| 268 | #define FIR_CR2_BCRC (1 << 9) |
| 269 | #define FIR_CR2_TFLRS (1 << 8) |
| 270 | #define FIR_CR2_ISS (1 << 7) |
| 271 | #define FIR_CR2_LMS (1 << 6) |
| 272 | #define FIR_CR2_TPPS (1 << 5) |
| 273 | #define FIR_CR2_RPPS (1 << 4) |
| 274 | #define FIR_CR2_TTRG_BIT 2 |
| 275 | #define FIR_CR2_TTRG_MASK (0x3 << FIR_CR2_TTRG_BIT) |
| 276 | #define FIR_CR2_TTRG_16 (0 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 16 */ |
| 277 | #define FIR_CR2_TTRG_32 (1 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 32 */ |
| 278 | #define FIR_CR2_TTRG_64 (2 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 64 */ |
| 279 | #define FIR_CR2_TTRG_128 (3 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 128 */ |
| 280 | #define FIR_CR2_RTRG_BIT 0 |
| 281 | #define FIR_CR2_RTRG_MASK (0x3 << FIR_CR2_RTRG_BIT) |
| 282 | #define FIR_CR2_RTRG_16 (0 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 16 */ |
| 283 | #define FIR_CR2_RTRG_32 (1 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 32 */ |
| 284 | #define FIR_CR2_RTRG_64 (2 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 64 */ |
| 285 | #define FIR_CR2_RTRG_128 (3 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 128 */ |
| 286 | |
| 287 | /* FIR Status Register (FIR_SR) */ |
| 288 | |
| 289 | #define FIR_SR_RFW (1 << 12) |
| 290 | #define FIR_SR_RFA (1 << 11) |
| 291 | #define FIR_SR_TFRTL (1 << 10) |
| 292 | #define FIR_SR_RFRTL (1 << 9) |
| 293 | #define FIR_SR_URUN (1 << 8) |
| 294 | #define FIR_SR_RFTE (1 << 7) |
| 295 | #define FIR_SR_ORUN (1 << 6) |
| 296 | #define FIR_SR_CRCE (1 << 5) |
| 297 | #define FIR_SR_FEND (1 << 4) |
| 298 | #define FIR_SR_TFF (1 << 3) |
| 299 | #define FIR_SR_RFE (1 << 2) |
| 300 | #define FIR_SR_TIDLE (1 << 1) |
| 301 | #define FIR_SR_RB (1 << 0) |
| 302 | |
| 303 | |
| 304 | |
| 305 | |
| 306 | /************************************************************************* |
| 307 | * SCC |
| 308 | *************************************************************************/ |
| 309 | #define SCC_DR(base) ((base) + 0x000) |
| 310 | #define SCC_FDR(base) ((base) + 0x004) |
| 311 | #define SCC_CR(base) ((base) + 0x008) |
| 312 | #define SCC_SR(base) ((base) + 0x00C) |
| 313 | #define SCC_TFR(base) ((base) + 0x010) |
| 314 | #define SCC_EGTR(base) ((base) + 0x014) |
| 315 | #define SCC_ECR(base) ((base) + 0x018) |
| 316 | #define SCC_RTOR(base) ((base) + 0x01C) |
| 317 | |
| 318 | #define REG_SCC_DR(base) REG8(SCC_DR(base)) |
| 319 | #define REG_SCC_FDR(base) REG8(SCC_FDR(base)) |
| 320 | #define REG_SCC_CR(base) REG32(SCC_CR(base)) |
| 321 | #define REG_SCC_SR(base) REG16(SCC_SR(base)) |
| 322 | #define REG_SCC_TFR(base) REG16(SCC_TFR(base)) |
| 323 | #define REG_SCC_EGTR(base) REG8(SCC_EGTR(base)) |
| 324 | #define REG_SCC_ECR(base) REG32(SCC_ECR(base)) |
| 325 | #define REG_SCC_RTOR(base) REG8(SCC_RTOR(base)) |
| 326 | |
| 327 | /* SCC FIFO Data Count Register (SCC_FDR) */ |
| 328 | |
| 329 | #define SCC_FDR_EMPTY 0x00 |
| 330 | #define SCC_FDR_FULL 0x10 |
| 331 | |
| 332 | /* SCC Control Register (SCC_CR) */ |
| 333 | |
| 334 | #define SCC_CR_SCCE (1 << 31) |
| 335 | #define SCC_CR_TRS (1 << 30) |
| 336 | #define SCC_CR_T2R (1 << 29) |
| 337 | #define SCC_CR_FDIV_BIT 24 |
| 338 | #define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT) |
| 339 | #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */ |
| 340 | #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */ |
| 341 | #define SCC_CR_FLUSH (1 << 23) |
| 342 | #define SCC_CR_TRIG_BIT 16 |
| 343 | #define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT) |
| 344 | #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */ |
| 345 | #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */ |
| 346 | #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */ |
| 347 | #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */ |
| 348 | #define SCC_CR_TP (1 << 15) |
| 349 | #define SCC_CR_CONV (1 << 14) |
| 350 | #define SCC_CR_TXIE (1 << 13) |
| 351 | #define SCC_CR_RXIE (1 << 12) |
| 352 | #define SCC_CR_TENDIE (1 << 11) |
| 353 | #define SCC_CR_RTOIE (1 << 10) |
| 354 | #define SCC_CR_ECIE (1 << 9) |
| 355 | #define SCC_CR_EPIE (1 << 8) |
| 356 | #define SCC_CR_RETIE (1 << 7) |
| 357 | #define SCC_CR_EOIE (1 << 6) |
| 358 | #define SCC_CR_TSEND (1 << 3) |
| 359 | #define SCC_CR_PX_BIT 1 |
| 360 | #define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT) |
| 361 | #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */ |
| 362 | #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */ |
| 363 | #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */ |
| 364 | #define SCC_CR_CLKSTP (1 << 0) |
| 365 | |
| 366 | /* SCC Status Register (SCC_SR) */ |
| 367 | |
| 368 | #define SCC_SR_TRANS (1 << 15) |
| 369 | #define SCC_SR_ORER (1 << 12) |
| 370 | #define SCC_SR_RTO (1 << 11) |
| 371 | #define SCC_SR_PER (1 << 10) |
| 372 | #define SCC_SR_TFTG (1 << 9) |
| 373 | #define SCC_SR_RFTG (1 << 8) |
| 374 | #define SCC_SR_TEND (1 << 7) |
| 375 | #define SCC_SR_RETR_3 (1 << 4) |
| 376 | #define SCC_SR_ECNTO (1 << 0) |
| 377 | |
| 378 | |
| 379 | |
| 380 | |
| 381 | /************************************************************************* |
| 382 | * ETH |
| 383 | *************************************************************************/ |
| 384 | #define ETH_BMR (ETH_BASE + 0x1000) |
| 385 | #define ETH_TPDR (ETH_BASE + 0x1004) |
| 386 | #define ETH_RPDR (ETH_BASE + 0x1008) |
| 387 | #define ETH_RAR (ETH_BASE + 0x100C) |
| 388 | #define ETH_TAR (ETH_BASE + 0x1010) |
| 389 | #define ETH_SR (ETH_BASE + 0x1014) |
| 390 | #define ETH_CR (ETH_BASE + 0x1018) |
| 391 | #define ETH_IER (ETH_BASE + 0x101C) |
| 392 | #define ETH_MFCR (ETH_BASE + 0x1020) |
| 393 | #define ETH_CTAR (ETH_BASE + 0x1050) |
| 394 | #define ETH_CRAR (ETH_BASE + 0x1054) |
| 395 | #define ETH_MCR (ETH_BASE + 0x0000) |
| 396 | #define ETH_MAHR (ETH_BASE + 0x0004) |
| 397 | #define ETH_MALR (ETH_BASE + 0x0008) |
| 398 | #define ETH_HTHR (ETH_BASE + 0x000C) |
| 399 | #define ETH_HTLR (ETH_BASE + 0x0010) |
| 400 | #define ETH_MIAR (ETH_BASE + 0x0014) |
| 401 | #define ETH_MIDR (ETH_BASE + 0x0018) |
| 402 | #define ETH_FCR (ETH_BASE + 0x001C) |
| 403 | #define ETH_VTR1 (ETH_BASE + 0x0020) |
| 404 | #define ETH_VTR2 (ETH_BASE + 0x0024) |
| 405 | #define ETH_WKFR (ETH_BASE + 0x0028) |
| 406 | #define ETH_PMTR (ETH_BASE + 0x002C) |
| 407 | |
| 408 | #define REG_ETH_BMR REG32(ETH_BMR) |
| 409 | #define REG_ETH_TPDR REG32(ETH_TPDR) |
| 410 | #define REG_ETH_RPDR REG32(ETH_RPDR) |
| 411 | #define REG_ETH_RAR REG32(ETH_RAR) |
| 412 | #define REG_ETH_TAR REG32(ETH_TAR) |
| 413 | #define REG_ETH_SR REG32(ETH_SR) |
| 414 | #define REG_ETH_CR REG32(ETH_CR) |
| 415 | #define REG_ETH_IER REG32(ETH_IER) |
| 416 | #define REG_ETH_MFCR REG32(ETH_MFCR) |
| 417 | #define REG_ETH_CTAR REG32(ETH_CTAR) |
| 418 | #define REG_ETH_CRAR REG32(ETH_CRAR) |
| 419 | #define REG_ETH_MCR REG32(ETH_MCR) |
| 420 | #define REG_ETH_MAHR REG32(ETH_MAHR) |
| 421 | #define REG_ETH_MALR REG32(ETH_MALR) |
| 422 | #define REG_ETH_HTHR REG32(ETH_HTHR) |
| 423 | #define REG_ETH_HTLR REG32(ETH_HTLR) |
| 424 | #define REG_ETH_MIAR REG32(ETH_MIAR) |
| 425 | #define REG_ETH_MIDR REG32(ETH_MIDR) |
| 426 | #define REG_ETH_FCR REG32(ETH_FCR) |
| 427 | #define REG_ETH_VTR1 REG32(ETH_VTR1) |
| 428 | #define REG_ETH_VTR2 REG32(ETH_VTR2) |
| 429 | #define REG_ETH_WKFR REG32(ETH_WKFR) |
| 430 | #define REG_ETH_PMTR REG32(ETH_PMTR) |
| 431 | |
| 432 | /* Bus Mode Register (ETH_BMR) */ |
| 433 | |
| 434 | #define ETH_BMR_DBO (1 << 20) |
| 435 | #define ETH_BMR_PBL_BIT 8 |
| 436 | #define ETH_BMR_PBL_MASK (0x3f << ETH_BMR_PBL_BIT) |
| 437 | #define ETH_BMR_PBL_1 (0x1 << ETH_BMR_PBL_BIT) |
| 438 | #define ETH_BMR_PBL_4 (0x4 << ETH_BMR_PBL_BIT) |
| 439 | #define ETH_BMR_BLE (1 << 7) |
| 440 | #define ETH_BMR_DSL_BIT 2 |
| 441 | #define ETH_BMR_DSL_MASK (0x1f << ETH_BMR_DSL_BIT) |
| 442 | #define ETH_BMR_DSL_0 (0x0 << ETH_BMR_DSL_BIT) |
| 443 | #define ETH_BMR_DSL_1 (0x1 << ETH_BMR_DSL_BIT) |
| 444 | #define ETH_BMR_DSL_2 (0x2 << ETH_BMR_DSL_BIT) |
| 445 | #define ETH_BMR_DSL_4 (0x4 << ETH_BMR_DSL_BIT) |
| 446 | #define ETH_BMR_DSL_8 (0x8 << ETH_BMR_DSL_BIT) |
| 447 | #define ETH_BMR_SWR (1 << 0) |
| 448 | |
| 449 | /* DMA Status Register (ETH_SR) */ |
| 450 | |
| 451 | #define ETH_SR_EB_BIT 23 |
| 452 | #define ETH_SR_EB_MASK (0x7 << ETH_SR_EB_BIT) |
| 453 | #define ETH_SR_EB_TX_ABORT (0x1 << ETH_SR_EB_BIT) |
| 454 | #define ETH_SR_EB_RX_ABORT (0x2 << ETH_SR_EB_BIT) |
| 455 | #define ETH_SR_TS_BIT 20 |
| 456 | #define ETH_SR_TS_MASK (0x7 << ETH_SR_TS_BIT) |
| 457 | #define ETH_SR_TS_STOP (0x0 << ETH_SR_TS_BIT) |
| 458 | #define ETH_SR_TS_FTD (0x1 << ETH_SR_TS_BIT) |
| 459 | #define ETH_SR_TS_WEOT (0x2 << ETH_SR_TS_BIT) |
| 460 | #define ETH_SR_TS_QDAT (0x3 << ETH_SR_TS_BIT) |
| 461 | #define ETH_SR_TS_SUSPEND (0x6 << ETH_SR_TS_BIT) |
| 462 | #define ETH_SR_TS_CTD (0x7 << ETH_SR_TS_BIT) |
| 463 | #define ETH_SR_RS_BIT 17 |
| 464 | #define ETH_SR_RS_MASK (0x7 << ETH_SR_RS_BIT) |
| 465 | #define ETH_SR_RS_STOP (0x0 << ETH_SR_RS_BIT) |
| 466 | #define ETH_SR_RS_FRD (0x1 << ETH_SR_RS_BIT) |
| 467 | #define ETH_SR_RS_CEOR (0x2 << ETH_SR_RS_BIT) |
| 468 | #define ETH_SR_RS_WRP (0x3 << ETH_SR_RS_BIT) |
| 469 | #define ETH_SR_RS_SUSPEND (0x4 << ETH_SR_RS_BIT) |
| 470 | #define ETH_SR_RS_CRD (0x5 << ETH_SR_RS_BIT) |
| 471 | #define ETH_SR_RS_FCF (0x6 << ETH_SR_RS_BIT) |
| 472 | #define ETH_SR_RS_QRF (0x7 << ETH_SR_RS_BIT) |
| 473 | #define ETH_SR_NIS (1 << 16) |
| 474 | #define ETH_SR_AIS (1 << 15) |
| 475 | #define ETH_SR_ERI (1 << 14) |
| 476 | #define ETH_SR_FBE (1 << 13) |
| 477 | #define ETH_SR_ETI (1 << 10) |
| 478 | #define ETH_SR_RWT (1 << 9) |
| 479 | #define ETH_SR_RPS (1 << 8) |
| 480 | #define ETH_SR_RU (1 << 7) |
| 481 | #define ETH_SR_RI (1 << 6) |
| 482 | #define ETH_SR_UNF (1 << 5) |
| 483 | #define ETH_SR_TJT (1 << 3) |
| 484 | #define ETH_SR_TU (1 << 2) |
| 485 | #define ETH_SR_TPS (1 << 1) |
| 486 | #define ETH_SR_TI (1 << 0) |
| 487 | |
| 488 | /* Control (Operation Mode) Register (ETH_CR) */ |
| 489 | |
| 490 | #define ETH_CR_TTM (1 << 22) |
| 491 | #define ETH_CR_SF (1 << 21) |
| 492 | #define ETH_CR_TR_BIT 14 |
| 493 | #define ETH_CR_TR_MASK (0x3 << ETH_CR_TR_BIT) |
| 494 | #define ETH_CR_ST (1 << 13) |
| 495 | #define ETH_CR_OSF (1 << 2) |
| 496 | #define ETH_CR_SR (1 << 1) |
| 497 | |
| 498 | /* Interrupt Enable Register (ETH_IER) */ |
| 499 | |
| 500 | #define ETH_IER_NI (1 << 16) |
| 501 | #define ETH_IER_AI (1 << 15) |
| 502 | #define ETH_IER_ERE (1 << 14) |
| 503 | #define ETH_IER_FBE (1 << 13) |
| 504 | #define ETH_IER_ET (1 << 10) |
| 505 | #define ETH_IER_RWE (1 << 9) |
| 506 | #define ETH_IER_RS (1 << 8) |
| 507 | #define ETH_IER_RU (1 << 7) |
| 508 | #define ETH_IER_RI (1 << 6) |
| 509 | #define ETH_IER_UN (1 << 5) |
| 510 | #define ETH_IER_TJ (1 << 3) |
| 511 | #define ETH_IER_TU (1 << 2) |
| 512 | #define ETH_IER_TS (1 << 1) |
| 513 | #define ETH_IER_TI (1 << 0) |
| 514 | |
| 515 | /* Missed Frame and Buffer Overflow Counter Register (ETH_MFCR) */ |
| 516 | |
| 517 | #define ETH_MFCR_OVERFLOW_BIT 17 |
| 518 | #define ETH_MFCR_OVERFLOW_MASK (0x7ff << ETH_MFCR_OVERFLOW_BIT) |
| 519 | #define ETH_MFCR_MFC_BIT 0 |
| 520 | #define ETH_MFCR_MFC_MASK (0xffff << ETH_MFCR_MFC_BIT) |
| 521 | |
| 522 | /* MAC Control Register (ETH_MCR) */ |
| 523 | |
| 524 | #define ETH_MCR_RA (1 << 31) |
| 525 | #define ETH_MCR_HBD (1 << 28) |
| 526 | #define ETH_MCR_PS (1 << 27) |
| 527 | #define ETH_MCR_DRO (1 << 23) |
| 528 | #define ETH_MCR_OM_BIT 21 |
| 529 | #define ETH_MCR_OM_MASK (0x3 << ETH_MCR_OM_BIT) |
| 530 | #define ETH_MCR_OM_NORMAL (0x0 << ETH_MCR_OM_BIT) |
| 531 | #define ETH_MCR_OM_INTERNAL (0x1 << ETH_MCR_OM_BIT) |
| 532 | #define ETH_MCR_OM_EXTERNAL (0x2 << ETH_MCR_OM_BIT) |
| 533 | #define ETH_MCR_F (1 << 20) |
| 534 | #define ETH_MCR_PM (1 << 19) |
| 535 | #define ETH_MCR_PR (1 << 18) |
| 536 | #define ETH_MCR_IF (1 << 17) |
| 537 | #define ETH_MCR_PB (1 << 16) |
| 538 | #define ETH_MCR_HO (1 << 15) |
| 539 | #define ETH_MCR_HP (1 << 13) |
| 540 | #define ETH_MCR_LCC (1 << 12) |
| 541 | #define ETH_MCR_DBF (1 << 11) |
| 542 | #define ETH_MCR_DTRY (1 << 10) |
| 543 | #define ETH_MCR_ASTP (1 << 8) |
| 544 | #define ETH_MCR_BOLMT_BIT 6 |
| 545 | #define ETH_MCR_BOLMT_MASK (0x3 << ETH_MCR_BOLMT_BIT) |
| 546 | #define ETH_MCR_BOLMT_10 (0 << ETH_MCR_BOLMT_BIT) |
| 547 | #define ETH_MCR_BOLMT_8 (1 << ETH_MCR_BOLMT_BIT) |
| 548 | #define ETH_MCR_BOLMT_4 (2 << ETH_MCR_BOLMT_BIT) |
| 549 | #define ETH_MCR_BOLMT_1 (3 << ETH_MCR_BOLMT_BIT) |
| 550 | #define ETH_MCR_DC (1 << 5) |
| 551 | #define ETH_MCR_TE (1 << 3) |
| 552 | #define ETH_MCR_RE (1 << 2) |
| 553 | |
| 554 | /* MII Address Register (ETH_MIAR) */ |
| 555 | |
| 556 | #define ETH_MIAR_PHY_ADDR_BIT 11 |
| 557 | #define ETH_MIAR_PHY_ADDR_MASK (0x1f << ETH_MIAR_PHY_ADDR_BIT) |
| 558 | #define ETH_MIAR_MII_REG_BIT 6 |
| 559 | #define ETH_MIAR_MII_REG_MASK (0x1f << ETH_MIAR_MII_REG_BIT) |
| 560 | #define ETH_MIAR_MII_WRITE (1 << 1) |
| 561 | #define ETH_MIAR_MII_BUSY (1 << 0) |
| 562 | |
| 563 | /* Flow Control Register (ETH_FCR) */ |
| 564 | |
| 565 | #define ETH_FCR_PAUSE_TIME_BIT 16 |
| 566 | #define ETH_FCR_PAUSE_TIME_MASK (0xffff << ETH_FCR_PAUSE_TIME_BIT) |
| 567 | #define ETH_FCR_PCF (1 << 2) |
| 568 | #define ETH_FCR_FCE (1 << 1) |
| 569 | #define ETH_FCR_BUSY (1 << 0) |
| 570 | |
| 571 | /* PMT Control and Status Register (ETH_PMTR) */ |
| 572 | |
| 573 | #define ETH_PMTR_GU (1 << 9) |
| 574 | #define ETH_PMTR_RF (1 << 6) |
| 575 | #define ETH_PMTR_MF (1 << 5) |
| 576 | #define ETH_PMTR_RWK (1 << 2) |
| 577 | #define ETH_PMTR_MPK (1 << 1) |
| 578 | |
| 579 | /* Receive Descriptor 0 (ETH_RD0) Bits */ |
| 580 | |
| 581 | #define ETH_RD0_OWN (1 << 31) |
| 582 | #define ETH_RD0_FF (1 << 30) |
| 583 | #define ETH_RD0_FL_BIT 16 |
| 584 | #define ETH_RD0_FL_MASK (0x3fff << ETH_RD0_FL_BIT) |
| 585 | #define ETH_RD0_ES (1 << 15) |
| 586 | #define ETH_RD0_DE (1 << 14) |
| 587 | #define ETH_RD0_LE (1 << 12) |
| 588 | #define ETH_RD0_RF (1 << 11) |
| 589 | #define ETH_RD0_MF (1 << 10) |
| 590 | #define ETH_RD0_FD (1 << 9) |
| 591 | #define ETH_RD0_LD (1 << 8) |
| 592 | #define ETH_RD0_TL (1 << 7) |
| 593 | #define ETH_RD0_CS (1 << 6) |
| 594 | #define ETH_RD0_FT (1 << 5) |
| 595 | #define ETH_RD0_WT (1 << 4) |
| 596 | #define ETH_RD0_ME (1 << 3) |
| 597 | #define ETH_RD0_DB (1 << 2) |
| 598 | #define ETH_RD0_CE (1 << 1) |
| 599 | |
| 600 | /* Receive Descriptor 1 (ETH_RD1) Bits */ |
| 601 | |
| 602 | #define ETH_RD1_RER (1 << 25) |
| 603 | #define ETH_RD1_RCH (1 << 24) |
| 604 | #define ETH_RD1_RBS2_BIT 11 |
| 605 | #define ETH_RD1_RBS2_MASK (0x7ff << ETH_RD1_RBS2_BIT) |
| 606 | #define ETH_RD1_RBS1_BIT 0 |
| 607 | #define ETH_RD1_RBS1_MASK (0x7ff << ETH_RD1_RBS1_BIT) |
| 608 | |
| 609 | /* Transmit Descriptor 0 (ETH_TD0) Bits */ |
| 610 | |
| 611 | #define ETH_TD0_OWN (1 << 31) |
| 612 | #define ETH_TD0_FA (1 << 15) |
| 613 | #define ETH_TD0_LOC (1 << 11) |
| 614 | #define ETH_TD0_NC (1 << 10) |
| 615 | #define ETH_TD0_LC (1 << 9) |
| 616 | #define ETH_TD0_EC (1 << 8) |
| 617 | #define ETH_TD0_HBF (1 << 7) |
| 618 | #define ETH_TD0_CC_BIT 3 |
| 619 | #define ETH_TD0_CC_MASK (0xf << ETH_TD0_CC_BIT) |
| 620 | #define ETH_TD0_ED (1 << 2) |
| 621 | #define ETH_TD0_UF (1 << 1) |
| 622 | #define ETH_TD0_DF (1 << 0) |
| 623 | |
| 624 | /* Transmit Descriptor 1 (ETH_TD1) Bits */ |
| 625 | |
| 626 | #define ETH_TD1_IC (1 << 31) |
| 627 | #define ETH_TD1_LS (1 << 30) |
| 628 | #define ETH_TD1_FS (1 << 29) |
| 629 | #define ETH_TD1_AC (1 << 26) |
| 630 | #define ETH_TD1_TER (1 << 25) |
| 631 | #define ETH_TD1_TCH (1 << 24) |
| 632 | #define ETH_TD1_DPD (1 << 23) |
| 633 | #define ETH_TD1_TBS2_BIT 11 |
| 634 | #define ETH_TD1_TBS2_MASK (0x7ff << ETH_TD1_TBS2_BIT) |
| 635 | #define ETH_TD1_TBS1_BIT 0 |
| 636 | #define ETH_TD1_TBS1_MASK (0x7ff << ETH_TD1_TBS1_BIT) |
| 637 | |
| 638 | |
| 639 | |
| 640 | |
| 641 | /************************************************************************* |
| 642 | * WDT |
| 643 | *************************************************************************/ |
| 644 | #define WDT_WTCSR (WDT_BASE + 0x00) |
| 645 | #define WDT_WTCNT (WDT_BASE + 0x04) |
| 646 | |
| 647 | #define REG_WDT_WTCSR REG8(WDT_WTCSR) |
| 648 | #define REG_WDT_WTCNT REG32(WDT_WTCNT) |
| 649 | |
| 650 | #define WDT_WTCSR_START (1 << 4) |
| 651 | |
| 652 | |
| 653 | |
| 654 | |
| 655 | /************************************************************************* |
| 656 | * OST |
| 657 | *************************************************************************/ |
| 658 | #define OST_TER (OST_BASE + 0x00) |
| 659 | #define OST_TRDR(n) (OST_BASE + 0x10 + ((n) * 0x20)) |
| 660 | #define OST_TCNT(n) (OST_BASE + 0x14 + ((n) * 0x20)) |
| 661 | #define OST_TCSR(n) (OST_BASE + 0x18 + ((n) * 0x20)) |
| 662 | #define OST_TCRB(n) (OST_BASE + 0x1c + ((n) * 0x20)) |
| 663 | |
| 664 | #define REG_OST_TER REG8(OST_TER) |
| 665 | #define REG_OST_TRDR(n) REG32(OST_TRDR((n))) |
| 666 | #define REG_OST_TCNT(n) REG32(OST_TCNT((n))) |
| 667 | #define REG_OST_TCSR(n) REG16(OST_TCSR((n))) |
| 668 | #define REG_OST_TCRB(n) REG32(OST_TCRB((n))) |
| 669 | |
| 670 | #define OST_TCSR_BUSY (1 << 7) |
| 671 | #define OST_TCSR_UF (1 << 6) |
| 672 | #define OST_TCSR_UIE (1 << 5) |
| 673 | #define OST_TCSR_CKS_BIT 0 |
| 674 | #define OST_TCSR_CKS_MASK (0x07 << OST_TCSR_CKS_BIT) |
| 675 | #define OST_TCSR_CKS_PCLK_4 (0 << OST_TCSR_CKS_BIT) |
| 676 | #define OST_TCSR_CKS_PCLK_16 (1 << OST_TCSR_CKS_BIT) |
| 677 | #define OST_TCSR_CKS_PCLK_64 (2 << OST_TCSR_CKS_BIT) |
| 678 | #define OST_TCSR_CKS_PCLK_256 (3 << OST_TCSR_CKS_BIT) |
| 679 | #define OST_TCSR_CKS_RTCCLK (4 << OST_TCSR_CKS_BIT) |
| 680 | #define OST_TCSR_CKS_EXTAL (5 << OST_TCSR_CKS_BIT) |
| 681 | |
| 682 | #define OST_TCSR0 OST_TCSR(0) |
| 683 | #define OST_TCSR1 OST_TCSR(1) |
| 684 | #define OST_TCSR2 OST_TCSR(2) |
| 685 | #define OST_TRDR0 OST_TRDR(0) |
| 686 | #define OST_TRDR1 OST_TRDR(1) |
| 687 | #define OST_TRDR2 OST_TRDR(2) |
| 688 | #define OST_TCNT0 OST_TCNT(0) |
| 689 | #define OST_TCNT1 OST_TCNT(1) |
| 690 | #define OST_TCNT2 OST_TCNT(2) |
| 691 | #define OST_TCRB0 OST_TCRB(0) |
| 692 | #define OST_TCRB1 OST_TCRB(1) |
| 693 | #define OST_TCRB2 OST_TCRB(2) |
| 694 | |
| 695 | /************************************************************************* |
| 696 | * UART |
| 697 | *************************************************************************/ |
| 698 | |
| 699 | #define IRDA_BASE UART0_BASE |
| 700 | #define UART_BASE UART0_BASE |
| 701 | #define UART_OFF 0x1000 |
| 702 | |
| 703 | /* register offset */ |
| 704 | #define OFF_RDR (0x00) /* R 8b H'xx */ |
| 705 | #define OFF_TDR (0x00) /* W 8b H'xx */ |
| 706 | #define OFF_DLLR (0x00) /* RW 8b H'00 */ |
| 707 | #define OFF_DLHR (0x04) /* RW 8b H'00 */ |
| 708 | #define OFF_IER (0x04) /* RW 8b H'00 */ |
| 709 | #define OFF_ISR (0x08) /* R 8b H'01 */ |
| 710 | #define OFF_FCR (0x08) /* W 8b H'00 */ |
| 711 | #define OFF_LCR (0x0C) /* RW 8b H'00 */ |
| 712 | #define OFF_MCR (0x10) /* RW 8b H'00 */ |
| 713 | #define OFF_LSR (0x14) /* R 8b H'00 */ |
| 714 | #define OFF_MSR (0x18) /* R 8b H'00 */ |
| 715 | #define OFF_SPR (0x1C) /* RW 8b H'00 */ |
| 716 | #define OFF_MCR (0x10) /* RW 8b H'00 */ |
| 717 | #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ |
| 718 | |
| 719 | /* register address */ |
| 720 | #define UART0_RDR (UART0_BASE + OFF_RDR) |
| 721 | #define UART0_TDR (UART0_BASE + OFF_TDR) |
| 722 | #define UART0_DLLR (UART0_BASE + OFF_DLLR) |
| 723 | #define UART0_DLHR (UART0_BASE + OFF_DLHR) |
| 724 | #define UART0_IER (UART0_BASE + OFF_IER) |
| 725 | #define UART0_ISR (UART0_BASE + OFF_ISR) |
| 726 | #define UART0_FCR (UART0_BASE + OFF_FCR) |
| 727 | #define UART0_LCR (UART0_BASE + OFF_LCR) |
| 728 | #define UART0_MCR (UART0_BASE + OFF_MCR) |
| 729 | #define UART0_LSR (UART0_BASE + OFF_LSR) |
| 730 | #define UART0_MSR (UART0_BASE + OFF_MSR) |
| 731 | #define UART0_SPR (UART0_BASE + OFF_SPR) |
| 732 | #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) |
| 733 | |
| 734 | #define UART1_RDR (UART1_BASE + OFF_RDR) |
| 735 | #define UART1_TDR (UART1_BASE + OFF_TDR) |
| 736 | #define UART1_DLLR (UART1_BASE + OFF_DLLR) |
| 737 | #define UART1_DLHR (UART1_BASE + OFF_DLHR) |
| 738 | #define UART1_IER (UART1_BASE + OFF_IER) |
| 739 | #define UART1_ISR (UART1_BASE + OFF_ISR) |
| 740 | #define UART1_FCR (UART1_BASE + OFF_FCR) |
| 741 | #define UART1_LCR (UART1_BASE + OFF_LCR) |
| 742 | #define UART1_MCR (UART1_BASE + OFF_MCR) |
| 743 | #define UART1_LSR (UART1_BASE + OFF_LSR) |
| 744 | #define UART1_MSR (UART1_BASE + OFF_MSR) |
| 745 | #define UART1_SPR (UART1_BASE + OFF_SPR) |
| 746 | #define UART1_SIRCR (UART1_BASE + OFF_SIRCR) |
| 747 | |
| 748 | #define UART2_RDR (UART2_BASE + OFF_RDR) |
| 749 | #define UART2_TDR (UART2_BASE + OFF_TDR) |
| 750 | #define UART2_DLLR (UART2_BASE + OFF_DLLR) |
| 751 | #define UART2_DLHR (UART2_BASE + OFF_DLHR) |
| 752 | #define UART2_IER (UART2_BASE + OFF_IER) |
| 753 | #define UART2_ISR (UART2_BASE + OFF_ISR) |
| 754 | #define UART2_FCR (UART2_BASE + OFF_FCR) |
| 755 | #define UART2_LCR (UART2_BASE + OFF_LCR) |
| 756 | #define UART2_MCR (UART2_BASE + OFF_MCR) |
| 757 | #define UART2_LSR (UART2_BASE + OFF_LSR) |
| 758 | #define UART2_MSR (UART2_BASE + OFF_MSR) |
| 759 | #define UART2_SPR (UART2_BASE + OFF_SPR) |
| 760 | #define UART2_SIRCR (UART2_BASE + OFF_SIRCR) |
| 761 | |
| 762 | #define UART3_RDR (UART3_BASE + OFF_RDR) |
| 763 | #define UART3_TDR (UART3_BASE + OFF_TDR) |
| 764 | #define UART3_DLLR (UART3_BASE + OFF_DLLR) |
| 765 | #define UART3_DLHR (UART3_BASE + OFF_DLHR) |
| 766 | #define UART3_IER (UART3_BASE + OFF_IER) |
| 767 | #define UART3_ISR (UART3_BASE + OFF_ISR) |
| 768 | #define UART3_FCR (UART3_BASE + OFF_FCR) |
| 769 | #define UART3_LCR (UART3_BASE + OFF_LCR) |
| 770 | #define UART3_MCR (UART3_BASE + OFF_MCR) |
| 771 | #define UART3_LSR (UART3_BASE + OFF_LSR) |
| 772 | #define UART3_MSR (UART3_BASE + OFF_MSR) |
| 773 | #define UART3_SPR (UART3_BASE + OFF_SPR) |
| 774 | #define UART3_SIRCR (UART3_BASE + OFF_SIRCR) |
| 775 | |
| 776 | /* |
| 777 | * Define macros for UART_IER |
| 778 | * UART Interrupt Enable Register |
| 779 | */ |
| 780 | #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ |
| 781 | #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ |
| 782 | #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ |
| 783 | #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ |
| 784 | #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ |
| 785 | |
| 786 | /* |
| 787 | * Define macros for UART_ISR |
| 788 | * UART Interrupt Status Register |
| 789 | */ |
| 790 | #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ |
| 791 | #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ |
| 792 | #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ |
| 793 | #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ |
| 794 | #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ |
| 795 | #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ |
| 796 | #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ |
| 797 | #define UART_ISR_FFMS_NO_FIFO (0 << 6) |
| 798 | #define UART_ISR_FFMS_FIFO_MODE (3 << 6) |
| 799 | |
| 800 | /* |
| 801 | * Define macros for UART_FCR |
| 802 | * UART FIFO Control Register |
| 803 | */ |
| 804 | #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ |
| 805 | #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ |
| 806 | #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ |
| 807 | #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ |
| 808 | #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ |
| 809 | #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ |
| 810 | #define UART_FCR_RTRG_1 (0 << 6) |
| 811 | #define UART_FCR_RTRG_4 (1 << 6) |
| 812 | #define UART_FCR_RTRG_8 (2 << 6) |
| 813 | #define UART_FCR_RTRG_15 (3 << 6) |
| 814 | |
| 815 | /* |
| 816 | * Define macros for UART_LCR |
| 817 | * UART Line Control Register |
| 818 | */ |
| 819 | #define UART_LCR_WLEN (3 << 0) /* word length */ |
| 820 | #define UART_LCR_WLEN_5 (0 << 0) |
| 821 | #define UART_LCR_WLEN_6 (1 << 0) |
| 822 | #define UART_LCR_WLEN_7 (2 << 0) |
| 823 | #define UART_LCR_WLEN_8 (3 << 0) |
| 824 | #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| 825 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| 826 | #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| 827 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| 828 | #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| 829 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| 830 | |
| 831 | #define UART_LCR_PE (1 << 3) /* 0: parity disable */ |
| 832 | #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ |
| 833 | #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ |
| 834 | #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ |
| 835 | #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ |
| 836 | |
| 837 | /* |
| 838 | * Define macros for UART_LSR |
| 839 | * UART Line Status Register |
| 840 | */ |
| 841 | #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ |
| 842 | #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ |
| 843 | #define UART_LSR_PER (1 << 2) /* 0: no parity error */ |
| 844 | #define UART_LSR_FER (1 << 3) /* 0; no framing error */ |
| 845 | #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ |
| 846 | #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ |
| 847 | #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ |
| 848 | #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ |
| 849 | |
| 850 | /* |
| 851 | * Define macros for UART_MCR |
| 852 | * UART Modem Control Register |
| 853 | */ |
| 854 | #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ |
| 855 | #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ |
| 856 | #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ |
| 857 | #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ |
| 858 | #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ |
| 859 | #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ |
| 860 | |
| 861 | /* |
| 862 | * Define macros for UART_MSR |
| 863 | * UART Modem Status Register |
| 864 | */ |
| 865 | #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ |
| 866 | #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ |
| 867 | #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ |
| 868 | #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ |
| 869 | #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ |
| 870 | #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ |
| 871 | #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ |
| 872 | #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ |
| 873 | |
| 874 | /* |
| 875 | * Define macros for SIRCR |
| 876 | * Slow IrDA Control Register |
| 877 | */ |
| 878 | #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ |
| 879 | #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ |
| 880 | #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length |
| 881 | 1: 0 pulse width is 1.6us for 115.2Kbps */ |
| 882 | #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ |
| 883 | #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ |
| 884 | |
| 885 | |
| 886 | |
| 887 | /************************************************************************* |
| 888 | * INTC |
| 889 | *************************************************************************/ |
| 890 | #define INTC_ISR (INTC_BASE + 0x00) |
| 891 | #define INTC_IMR (INTC_BASE + 0x04) |
| 892 | #define INTC_IMSR (INTC_BASE + 0x08) |
| 893 | #define INTC_IMCR (INTC_BASE + 0x0c) |
| 894 | #define INTC_IPR (INTC_BASE + 0x10) |
| 895 | |
| 896 | #define REG_INTC_ISR REG32(INTC_ISR) |
| 897 | #define REG_INTC_IMR REG32(INTC_IMR) |
| 898 | #define REG_INTC_IMSR REG32(INTC_IMSR) |
| 899 | #define REG_INTC_IMCR REG32(INTC_IMCR) |
| 900 | #define REG_INTC_IPR REG32(INTC_IPR) |
| 901 | |
| 902 | #define IRQ_I2C 1 |
| 903 | #define IRQ_PS2 2 |
| 904 | #define IRQ_UPRT 3 |
| 905 | #define IRQ_CORE 4 |
| 906 | #define IRQ_UART3 6 |
| 907 | #define IRQ_UART2 7 |
| 908 | #define IRQ_UART1 8 |
| 909 | #define IRQ_UART0 9 |
| 910 | #define IRQ_SCC1 10 |
| 911 | #define IRQ_SCC0 11 |
| 912 | #define IRQ_UDC 12 |
| 913 | #define IRQ_UHC 13 |
| 914 | #define IRQ_MSC 14 |
| 915 | #define IRQ_RTC 15 |
| 916 | #define IRQ_FIR 16 |
| 917 | #define IRQ_SSI 17 |
| 918 | #define IRQ_CIM 18 |
| 919 | #define IRQ_ETH 19 |
| 920 | #define IRQ_AIC 20 |
| 921 | #define IRQ_DMAC 21 |
| 922 | #define IRQ_OST2 22 |
| 923 | #define IRQ_OST1 23 |
| 924 | #define IRQ_OST0 24 |
| 925 | #define IRQ_GPIO3 25 |
| 926 | #define IRQ_GPIO2 26 |
| 927 | #define IRQ_GPIO1 27 |
| 928 | #define IRQ_GPIO0 28 |
| 929 | #define IRQ_LCD 30 |
| 930 | |
| 931 | |
| 932 | |
| 933 | |
| 934 | /************************************************************************* |
| 935 | * CIM |
| 936 | *************************************************************************/ |
| 937 | #define CIM_CFG (CIM_BASE + 0x0000) |
| 938 | #define CIM_CTRL (CIM_BASE + 0x0004) |
| 939 | #define CIM_STATE (CIM_BASE + 0x0008) |
| 940 | #define CIM_IID (CIM_BASE + 0x000C) |
| 941 | #define CIM_RXFIFO (CIM_BASE + 0x0010) |
| 942 | #define CIM_DA (CIM_BASE + 0x0020) |
| 943 | #define CIM_FA (CIM_BASE + 0x0024) |
| 944 | #define CIM_FID (CIM_BASE + 0x0028) |
| 945 | #define CIM_CMD (CIM_BASE + 0x002C) |
| 946 | |
| 947 | #define REG_CIM_CFG REG32(CIM_CFG) |
| 948 | #define REG_CIM_CTRL REG32(CIM_CTRL) |
| 949 | #define REG_CIM_STATE REG32(CIM_STATE) |
| 950 | #define REG_CIM_IID REG32(CIM_IID) |
| 951 | #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) |
| 952 | #define REG_CIM_DA REG32(CIM_DA) |
| 953 | #define REG_CIM_FA REG32(CIM_FA) |
| 954 | #define REG_CIM_FID REG32(CIM_FID) |
| 955 | #define REG_CIM_CMD REG32(CIM_CMD) |
| 956 | |
| 957 | /* CIM Configuration Register (CIM_CFG) */ |
| 958 | |
| 959 | #define CIM_CFG_INV_DAT (1 << 15) |
| 960 | #define CIM_CFG_VSP (1 << 14) |
| 961 | #define CIM_CFG_HSP (1 << 13) |
| 962 | #define CIM_CFG_PCP (1 << 12) |
| 963 | #define CIM_CFG_DUMMY_ZERO (1 << 9) |
| 964 | #define CIM_CFG_EXT_VSYNC (1 << 8) |
| 965 | #define CIM_CFG_PACK_BIT 4 |
| 966 | #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) |
| 967 | #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) |
| 968 | #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) |
| 969 | #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) |
| 970 | #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) |
| 971 | #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) |
| 972 | #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) |
| 973 | #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) |
| 974 | #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) |
| 975 | #define CIM_CFG_DSM_BIT 0 |
| 976 | #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) |
| 977 | #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ |
| 978 | #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ |
| 979 | #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ |
| 980 | #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ |
| 981 | |
| 982 | /* CIM Control Register (CIM_CTRL) */ |
| 983 | |
| 984 | #define CIM_CTRL_MCLKDIV_BIT 24 |
| 985 | #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) |
| 986 | #define CIM_CTRL_FRC_BIT 16 |
| 987 | #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) |
| 988 | #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ |
| 989 | #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ |
| 990 | #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ |
| 991 | #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ |
| 992 | #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ |
| 993 | #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ |
| 994 | #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ |
| 995 | #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ |
| 996 | #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ |
| 997 | #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ |
| 998 | #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ |
| 999 | #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ |
| 1000 | #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ |
| 1001 | #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ |
| 1002 | #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ |
| 1003 | #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ |
| 1004 | #define CIM_CTRL_VDDM (1 << 13) |
| 1005 | #define CIM_CTRL_DMA_SOFM (1 << 12) |
| 1006 | #define CIM_CTRL_DMA_EOFM (1 << 11) |
| 1007 | #define CIM_CTRL_DMA_STOPM (1 << 10) |
| 1008 | #define CIM_CTRL_RXF_TRIGM (1 << 9) |
| 1009 | #define CIM_CTRL_RXF_OFM (1 << 8) |
| 1010 | #define CIM_CTRL_RXF_TRIG_BIT 4 |
| 1011 | #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) |
| 1012 | #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ |
| 1013 | #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ |
| 1014 | #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ |
| 1015 | #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ |
| 1016 | #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ |
| 1017 | #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ |
| 1018 | #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ |
| 1019 | #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ |
| 1020 | #define CIM_CTRL_DMA_EN (1 << 2) |
| 1021 | #define CIM_CTRL_RXF_RST (1 << 1) |
| 1022 | #define CIM_CTRL_ENA (1 << 0) |
| 1023 | |
| 1024 | /* CIM State Register (CIM_STATE) */ |
| 1025 | |
| 1026 | #define CIM_STATE_DMA_SOF (1 << 6) |
| 1027 | #define CIM_STATE_DMA_EOF (1 << 5) |
| 1028 | #define CIM_STATE_DMA_STOP (1 << 4) |
| 1029 | #define CIM_STATE_RXF_OF (1 << 3) |
| 1030 | #define CIM_STATE_RXF_TRIG (1 << 2) |
| 1031 | #define CIM_STATE_RXF_EMPTY (1 << 1) |
| 1032 | #define CIM_STATE_VDD (1 << 0) |
| 1033 | |
| 1034 | /* CIM DMA Command Register (CIM_CMD) */ |
| 1035 | |
| 1036 | #define CIM_CMD_SOFINT (1 << 31) |
| 1037 | #define CIM_CMD_EOFINT (1 << 30) |
| 1038 | #define CIM_CMD_STOP (1 << 28) |
| 1039 | #define CIM_CMD_LEN_BIT 0 |
| 1040 | #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) |
| 1041 | |
| 1042 | |
| 1043 | |
| 1044 | |
| 1045 | /************************************************************************* |
| 1046 | * PWM |
| 1047 | *************************************************************************/ |
| 1048 | #define PWM_CTR(n) (PWM##n##_BASE + 0x000) |
| 1049 | #define PWM_PER(n) (PWM##n##_BASE + 0x004) |
| 1050 | #define PWM_DUT(n) (PWM##n##_BASE + 0x008) |
| 1051 | |
| 1052 | #define REG_PWM_CTR(n) REG8(PWM_CTR(n)) |
| 1053 | #define REG_PWM_PER(n) REG16(PWM_PER(n)) |
| 1054 | #define REG_PWM_DUT(n) REG16(PWM_DUT(n)) |
| 1055 | |
| 1056 | /* PWM Control Register (PWM_CTR) */ |
| 1057 | |
| 1058 | #define PWM_CTR_EN (1 << 7) |
| 1059 | #define PWM_CTR_SD (1 << 6) |
| 1060 | #define PWM_CTR_PRESCALE_BIT 0 |
| 1061 | #define PWM_CTR_PRESCALE_MASK (0x3f << PWM_CTR_PRESCALE_BIT) |
| 1062 | |
| 1063 | /* PWM Period Register (PWM_PER) */ |
| 1064 | |
| 1065 | #define PWM_PER_PERIOD_BIT 0 |
| 1066 | #define PWM_PER_PERIOD_MASK (0x3ff << PWM_PER_PERIOD_BIT) |
| 1067 | |
| 1068 | /* PWM Duty Register (PWM_DUT) */ |
| 1069 | |
| 1070 | #define PWM_DUT_FDUTY (1 << 10) |
| 1071 | #define PWM_DUT_DUTY_BIT 0 |
| 1072 | #define PWM_DUT_DUTY_MASK (0x3ff << PWM_DUT_DUTY_BIT) |
| 1073 | |
| 1074 | |
| 1075 | |
| 1076 | |
| 1077 | /************************************************************************* |
| 1078 | * EMC |
| 1079 | *************************************************************************/ |
| 1080 | #define EMC_BCR (EMC_BASE + 0x00) |
| 1081 | #define EMC_SMCR0 (EMC_BASE + 0x10) |
| 1082 | #define EMC_SMCR1 (EMC_BASE + 0x14) |
| 1083 | #define EMC_SMCR2 (EMC_BASE + 0x18) |
| 1084 | #define EMC_SMCR3 (EMC_BASE + 0x1c) |
| 1085 | #define EMC_SMCR4 (EMC_BASE + 0x20) |
| 1086 | #define EMC_SMCR5 (EMC_BASE + 0x24) |
| 1087 | #define EMC_SMCR6 (EMC_BASE + 0x28) |
| 1088 | #define EMC_SMCR7 (EMC_BASE + 0x2c) |
| 1089 | #define EMC_SACR0 (EMC_BASE + 0x30) |
| 1090 | #define EMC_SACR1 (EMC_BASE + 0x34) |
| 1091 | #define EMC_SACR2 (EMC_BASE + 0x38) |
| 1092 | #define EMC_SACR3 (EMC_BASE + 0x3c) |
| 1093 | #define EMC_SACR4 (EMC_BASE + 0x40) |
| 1094 | #define EMC_SACR5 (EMC_BASE + 0x44) |
| 1095 | #define EMC_SACR6 (EMC_BASE + 0x48) |
| 1096 | #define EMC_SACR7 (EMC_BASE + 0x4c) |
| 1097 | #define EMC_NFCSR (EMC_BASE + 0x50) |
| 1098 | #define EMC_NFECC (EMC_BASE + 0x54) |
| 1099 | #define EMC_PCCR1 (EMC_BASE + 0x60) |
| 1100 | #define EMC_PCCR2 (EMC_BASE + 0x64) |
| 1101 | #define EMC_PCCR3 (EMC_BASE + 0x68) |
| 1102 | #define EMC_PCCR4 (EMC_BASE + 0x6c) |
| 1103 | #define EMC_DMCR (EMC_BASE + 0x80) |
| 1104 | #define EMC_RTCSR (EMC_BASE + 0x84) |
| 1105 | #define EMC_RTCNT (EMC_BASE + 0x88) |
| 1106 | #define EMC_RTCOR (EMC_BASE + 0x8c) |
| 1107 | #define EMC_DMAR1 (EMC_BASE + 0x90) |
| 1108 | #define EMC_DMAR2 (EMC_BASE + 0x94) |
| 1109 | #define EMC_DMAR3 (EMC_BASE + 0x98) |
| 1110 | #define EMC_DMAR4 (EMC_BASE + 0x9c) |
| 1111 | |
| 1112 | #define EMC_SDMR0 (EMC_BASE + 0xa000) |
| 1113 | #define EMC_SDMR1 (EMC_BASE + 0xb000) |
| 1114 | #define EMC_SDMR2 (EMC_BASE + 0xc000) |
| 1115 | #define EMC_SDMR3 (EMC_BASE + 0xd000) |
| 1116 | |
| 1117 | /* NAND command/address/data port */ |
| 1118 | #define NAND_DATAPORT 0xB4000000 /* read-write area */ |
| 1119 | #define NAND_CMDPORT 0xB4040000 /* write only area */ |
| 1120 | #define NAND_ADDRPORT 0xB4080000 /* write only area */ |
| 1121 | |
| 1122 | #define REG_EMC_BCR REG32(EMC_BCR) |
| 1123 | #define REG_EMC_SMCR0 REG32(EMC_SMCR0) |
| 1124 | #define REG_EMC_SMCR1 REG32(EMC_SMCR1) |
| 1125 | #define REG_EMC_SMCR2 REG32(EMC_SMCR2) |
| 1126 | #define REG_EMC_SMCR3 REG32(EMC_SMCR3) |
| 1127 | #define REG_EMC_SMCR4 REG32(EMC_SMCR4) |
| 1128 | #define REG_EMC_SMCR5 REG32(EMC_SMCR5) |
| 1129 | #define REG_EMC_SMCR6 REG32(EMC_SMCR6) |
| 1130 | #define REG_EMC_SMCR7 REG32(EMC_SMCR7) |
| 1131 | #define REG_EMC_SACR0 REG32(EMC_SACR0) |
| 1132 | #define REG_EMC_SACR1 REG32(EMC_SACR1) |
| 1133 | #define REG_EMC_SACR2 REG32(EMC_SACR2) |
| 1134 | #define REG_EMC_SACR3 REG32(EMC_SACR3) |
| 1135 | #define REG_EMC_SACR4 REG32(EMC_SACR4) |
| 1136 | #define REG_EMC_SACR5 REG32(EMC_SACR5) |
| 1137 | #define REG_EMC_SACR6 REG32(EMC_SACR6) |
| 1138 | #define REG_EMC_SACR7 REG32(EMC_SACR7) |
| 1139 | #define REG_EMC_NFCSR REG32(EMC_NFCSR) |
| 1140 | #define REG_EMC_NFECC REG32(EMC_NFECC) |
| 1141 | #define REG_EMC_DMCR REG32(EMC_DMCR) |
| 1142 | #define REG_EMC_RTCSR REG16(EMC_RTCSR) |
| 1143 | #define REG_EMC_RTCNT REG16(EMC_RTCNT) |
| 1144 | #define REG_EMC_RTCOR REG16(EMC_RTCOR) |
| 1145 | #define REG_EMC_DMAR1 REG32(EMC_DMAR1) |
| 1146 | #define REG_EMC_DMAR2 REG32(EMC_DMAR2) |
| 1147 | #define REG_EMC_DMAR3 REG32(EMC_DMAR3) |
| 1148 | #define REG_EMC_DMAR4 REG32(EMC_DMAR4) |
| 1149 | #define REG_EMC_PCCR1 REG32(EMC_PCCR1) |
| 1150 | #define REG_EMC_PCCR2 REG32(EMC_PCCR2) |
| 1151 | #define REG_EMC_PCCR3 REG32(EMC_PCCR3) |
| 1152 | #define REG_EMC_PCCR4 REG32(EMC_PCCR4) |
| 1153 | |
| 1154 | |
| 1155 | #define EMC_BCR_BRE (1 << 1) |
| 1156 | |
| 1157 | #define EMC_SMCR_STRV_BIT 24 |
| 1158 | #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) |
| 1159 | #define EMC_SMCR_TAW_BIT 20 |
| 1160 | #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) |
| 1161 | #define EMC_SMCR_TBP_BIT 16 |
| 1162 | #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) |
| 1163 | #define EMC_SMCR_TAH_BIT 12 |
| 1164 | #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) |
| 1165 | #define EMC_SMCR_TAS_BIT 8 |
| 1166 | #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) |
| 1167 | #define EMC_SMCR_BW_BIT 6 |
| 1168 | #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) |
| 1169 | #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) |
| 1170 | #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) |
| 1171 | #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) |
| 1172 | #define EMC_SMCR_BCM (1 << 3) |
| 1173 | #define EMC_SMCR_BL_BIT 1 |
| 1174 | #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) |
| 1175 | #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) |
| 1176 | #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) |
| 1177 | #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) |
| 1178 | #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) |
| 1179 | #define EMC_SMCR_SMT (1 << 0) |
| 1180 | |
| 1181 | #define EMC_SACR_BASE_BIT 8 |
| 1182 | #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) |
| 1183 | #define EMC_SACR_MASK_BIT 0 |
| 1184 | #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) |
| 1185 | |
| 1186 | #define EMC_NFCSR_RB (1 << 7) |
| 1187 | #define EMC_NFCSR_BOOT_SEL_BIT 4 |
| 1188 | #define EMC_NFCSR_BOOT_SEL_MASK (0x07 << EMC_NFCSR_BOOT_SEL_BIT) |
| 1189 | #define EMC_NFCSR_ERST (1 << 3) |
| 1190 | #define EMC_NFCSR_ECCE (1 << 2) |
| 1191 | #define EMC_NFCSR_FCE (1 << 1) |
| 1192 | #define EMC_NFCSR_NFE (1 << 0) |
| 1193 | |
| 1194 | #define EMC_NFECC_ECC2_BIT 16 |
| 1195 | #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) |
| 1196 | #define EMC_NFECC_ECC1_BIT 8 |
| 1197 | #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) |
| 1198 | #define EMC_NFECC_ECC0_BIT 0 |
| 1199 | #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) |
| 1200 | |
| 1201 | #define EMC_DMCR_BW_BIT 31 |
| 1202 | #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) |
| 1203 | #define EMC_DMCR_BW_32 (0 << EMC_DMCR_BW_BIT) |
| 1204 | #define EMC_DMCR_BW_16 (1 << EMC_DMCR_BW_BIT) |
| 1205 | #define EMC_DMCR_CA_BIT 26 |
| 1206 | #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) |
| 1207 | #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) |
| 1208 | #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) |
| 1209 | #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) |
| 1210 | #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) |
| 1211 | #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) |
| 1212 | #define EMC_DMCR_RMODE (1 << 25) |
| 1213 | #define EMC_DMCR_RFSH (1 << 24) |
| 1214 | #define EMC_DMCR_MRSET (1 << 23) |
| 1215 | #define EMC_DMCR_RA_BIT 20 |
| 1216 | #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) |
| 1217 | #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) |
| 1218 | #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) |
| 1219 | #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) |
| 1220 | #define EMC_DMCR_BA_BIT 19 |
| 1221 | #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) |
| 1222 | #define EMC_DMCR_BA_2 (0 << EMC_DMCR_BA_BIT) |
| 1223 | #define EMC_DMCR_BA_4 (1 << EMC_DMCR_BA_BIT) |
| 1224 | #define EMC_DMCR_PDM (1 << 18) |
| 1225 | #define EMC_DMCR_EPIN (1 << 17) |
| 1226 | #define EMC_DMCR_TRAS_BIT 13 |
| 1227 | #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) |
| 1228 | #define EMC_DMCR_RCD_BIT 11 |
| 1229 | #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) |
| 1230 | #define EMC_DMCR_TPC_BIT 8 |
| 1231 | #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) |
| 1232 | #define EMC_DMCR_TRWL_BIT 5 |
| 1233 | #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) |
| 1234 | #define EMC_DMCR_TRC_BIT 2 |
| 1235 | #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) |
| 1236 | #define EMC_DMCR_TCL_BIT 0 |
| 1237 | #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) |
| 1238 | #define EMC_DMCR_CASL_2 (1 << EMC_DMCR_TCL_BIT) |
| 1239 | #define EMC_DMCR_CASL_3 (2 << EMC_DMCR_TCL_BIT) |
| 1240 | |
| 1241 | #define EMC_RTCSR_CMF (1 << 7) |
| 1242 | #define EMC_RTCSR_CKS_BIT 0 |
| 1243 | #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) |
| 1244 | #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) |
| 1245 | #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) |
| 1246 | #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) |
| 1247 | #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) |
| 1248 | #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) |
| 1249 | #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) |
| 1250 | #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) |
| 1251 | #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) |
| 1252 | |
| 1253 | #define EMC_DMAR_BASE_BIT 8 |
| 1254 | #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) |
| 1255 | #define EMC_DMAR_MASK_BIT 0 |
| 1256 | #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) |
| 1257 | |
| 1258 | #define EMC_SDMR_BM (1 << 9) |
| 1259 | #define EMC_SDMR_OM_BIT 7 |
| 1260 | #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) |
| 1261 | #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) |
| 1262 | #define EMC_SDMR_CAS_BIT 4 |
| 1263 | #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) |
| 1264 | #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) |
| 1265 | #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) |
| 1266 | #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) |
| 1267 | #define EMC_SDMR_BT_BIT 3 |
| 1268 | #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) |
| 1269 | #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) |
| 1270 | #define EMC_SDMR_BT_INTR (1 << EMC_SDMR_BT_BIT) |
| 1271 | #define EMC_SDMR_BL_BIT 0 |
| 1272 | #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) |
| 1273 | #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) |
| 1274 | #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) |
| 1275 | #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) |
| 1276 | #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) |
| 1277 | |
| 1278 | #define EMC_SDMR_CAS2_16BIT \ |
| 1279 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| 1280 | #define EMC_SDMR_CAS2_32BIT \ |
| 1281 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| 1282 | #define EMC_SDMR_CAS3_16BIT \ |
| 1283 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| 1284 | #define EMC_SDMR_CAS3_32BIT \ |
| 1285 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| 1286 | |
| 1287 | #define EMC_PCCR12_AMW (1 << 31) |
| 1288 | #define EMC_PCCR12_AMAS_BIT 28 |
| 1289 | #define EMC_PCCR12_AMAS_MASK (0x07 << EMC_PCCR12_AMAS_BIT) |
| 1290 | #define EMC_PCCR12_AMAH_BIT 24 |
| 1291 | #define EMC_PCCR12_AMAH_MASK (0x07 << EMC_PCCR12_AMAH_BIT) |
| 1292 | #define EMC_PCCR12_AMPW_BIT 20 |
| 1293 | #define EMC_PCCR12_AMPW_MASK (0x0f << EMC_PCCR12_AMPW_BIT) |
| 1294 | #define EMC_PCCR12_AMRT_BIT 16 |
| 1295 | #define EMC_PCCR12_AMRT_MASK (0x0f << EMC_PCCR12_AMRT_BIT) |
| 1296 | #define EMC_PCCR12_CMW (1 << 15) |
| 1297 | #define EMC_PCCR12_CMAS_BIT 12 |
| 1298 | #define EMC_PCCR12_CMAS_MASK (0x07 << EMC_PCCR12_CMAS_BIT) |
| 1299 | #define EMC_PCCR12_CMAH_BIT 8 |
| 1300 | #define EMC_PCCR12_CMAH_MASK (0x07 << EMC_PCCR12_CMAH_BIT) |
| 1301 | #define EMC_PCCR12_CMPW_BIT 4 |
| 1302 | #define EMC_PCCR12_CMPW_MASK (0x0f << EMC_PCCR12_CMPW_BIT) |
| 1303 | #define EMC_PCCR12_CMRT_BIT 0 |
| 1304 | #define EMC_PCCR12_CMRT_MASK (0x07 << EMC_PCCR12_CMRT_BIT) |
| 1305 | |
| 1306 | #define EMC_PCCR34_DRS_BIT 16 |
| 1307 | #define EMC_PCCR34_DRS_MASK (0x03 << EMC_PCCR34_DRS_BIT) |
| 1308 | #define EMC_PCCR34_DRS_SPKR (1 << EMC_PCCR34_DRS_BIT) |
| 1309 | #define EMC_PCCR34_DRS_IOIS16 (2 << EMC_PCCR34_DRS_BIT) |
| 1310 | #define EMC_PCCR34_DRS_INPACK (3 << EMC_PCCR34_DRS_BIT) |
| 1311 | #define EMC_PCCR34_IOIS16 (1 << 15) |
| 1312 | #define EMC_PCCR34_IOW (1 << 14) |
| 1313 | #define EMC_PCCR34_TCB_BIT 12 |
| 1314 | #define EMC_PCCR34_TCB_MASK (0x03 << EMC_PCCR34_TCB_BIT) |
| 1315 | #define EMC_PCCR34_IORT_BIT 8 |
| 1316 | #define EMC_PCCR34_IORT_MASK (0x07 << EMC_PCCR34_IORT_BIT) |
| 1317 | #define EMC_PCCR34_IOAE_BIT 6 |
| 1318 | #define EMC_PCCR34_IOAE_MASK (0x03 << EMC_PCCR34_IOAE_BIT) |
| 1319 | #define EMC_PCCR34_IOAE_NONE (0 << EMC_PCCR34_IOAE_BIT) |
| 1320 | #define EMC_PCCR34_IOAE_1 (1 << EMC_PCCR34_IOAE_BIT) |
| 1321 | #define EMC_PCCR34_IOAE_2 (2 << EMC_PCCR34_IOAE_BIT) |
| 1322 | #define EMC_PCCR34_IOAE_5 (3 << EMC_PCCR34_IOAE_BIT) |
| 1323 | #define EMC_PCCR34_IOAH_BIT 4 |
| 1324 | #define EMC_PCCR34_IOAH_MASK (0x03 << EMC_PCCR34_IOAH_BIT) |
| 1325 | #define EMC_PCCR34_IOAH_NONE (0 << EMC_PCCR34_IOAH_BIT) |
| 1326 | #define EMC_PCCR34_IOAH_1 (1 << EMC_PCCR34_IOAH_BIT) |
| 1327 | #define EMC_PCCR34_IOAH_2 (2 << EMC_PCCR34_IOAH_BIT) |
| 1328 | #define EMC_PCCR34_IOAH_5 (3 << EMC_PCCR34_IOAH_BIT) |
| 1329 | #define EMC_PCCR34_IOPW_BIT 0 |
| 1330 | #define EMC_PCCR34_IOPW_MASK (0x0f << EMC_PCCR34_IOPW_BIT) |
| 1331 | |
| 1332 | |
| 1333 | |
| 1334 | |
| 1335 | /************************************************************************* |
| 1336 | * GPIO |
| 1337 | *************************************************************************/ |
| 1338 | #define GPIO_GPDR(n) (GPIO_BASE + (0x00 + (n)*0x30)) |
| 1339 | #define GPIO_GPDIR(n) (GPIO_BASE + (0x04 + (n)*0x30)) |
| 1340 | #define GPIO_GPODR(n) (GPIO_BASE + (0x08 + (n)*0x30)) |
| 1341 | #define GPIO_GPPUR(n) (GPIO_BASE + (0x0c + (n)*0x30)) |
| 1342 | #define GPIO_GPALR(n) (GPIO_BASE + (0x10 + (n)*0x30)) |
| 1343 | #define GPIO_GPAUR(n) (GPIO_BASE + (0x14 + (n)*0x30)) |
| 1344 | #define GPIO_GPIDLR(n) (GPIO_BASE + (0x18 + (n)*0x30)) |
| 1345 | #define GPIO_GPIDUR(n) (GPIO_BASE + (0x1c + (n)*0x30)) |
| 1346 | #define GPIO_GPIER(n) (GPIO_BASE + (0x20 + (n)*0x30)) |
| 1347 | #define GPIO_GPIMR(n) (GPIO_BASE + (0x24 + (n)*0x30)) |
| 1348 | #define GPIO_GPFR(n) (GPIO_BASE + (0x28 + (n)*0x30)) |
| 1349 | |
| 1350 | #define REG_GPIO_GPDR(n) REG32(GPIO_GPDR((n))) |
| 1351 | #define REG_GPIO_GPDIR(n) REG32(GPIO_GPDIR((n))) |
| 1352 | #define REG_GPIO_GPODR(n) REG32(GPIO_GPODR((n))) |
| 1353 | #define REG_GPIO_GPPUR(n) REG32(GPIO_GPPUR((n))) |
| 1354 | #define REG_GPIO_GPALR(n) REG32(GPIO_GPALR((n))) |
| 1355 | #define REG_GPIO_GPAUR(n) REG32(GPIO_GPAUR((n))) |
| 1356 | #define REG_GPIO_GPIDLR(n) REG32(GPIO_GPIDLR((n))) |
| 1357 | #define REG_GPIO_GPIDUR(n) REG32(GPIO_GPIDUR((n))) |
| 1358 | #define REG_GPIO_GPIER(n) REG32(GPIO_GPIER((n))) |
| 1359 | #define REG_GPIO_GPIMR(n) REG32(GPIO_GPIMR((n))) |
| 1360 | #define REG_GPIO_GPFR(n) REG32(GPIO_GPFR((n))) |
| 1361 | |
| 1362 | #define GPIO_IRQ_LOLEVEL 0 |
| 1363 | #define GPIO_IRQ_HILEVEL 1 |
| 1364 | #define GPIO_IRQ_FALLEDG 2 |
| 1365 | #define GPIO_IRQ_RAISEDG 3 |
| 1366 | |
| 1367 | #define IRQ_GPIO_0 48 |
| 1368 | #define NUM_GPIO 100 |
| 1369 | |
| 1370 | #define GPIO_GPDR0 GPIO_GPDR(0) |
| 1371 | #define GPIO_GPDR1 GPIO_GPDR(1) |
| 1372 | #define GPIO_GPDR2 GPIO_GPDR(2) |
| 1373 | #define GPIO_GPDR3 GPIO_GPDR(3) |
| 1374 | #define GPIO_GPDIR0 GPIO_GPDIR(0) |
| 1375 | #define GPIO_GPDIR1 GPIO_GPDIR(1) |
| 1376 | #define GPIO_GPDIR2 GPIO_GPDIR(2) |
| 1377 | #define GPIO_GPDIR3 GPIO_GPDIR(3) |
| 1378 | #define GPIO_GPODR0 GPIO_GPODR(0) |
| 1379 | #define GPIO_GPODR1 GPIO_GPODR(1) |
| 1380 | #define GPIO_GPODR2 GPIO_GPODR(2) |
| 1381 | #define GPIO_GPODR3 GPIO_GPODR(3) |
| 1382 | #define GPIO_GPPUR0 GPIO_GPPUR(0) |
| 1383 | #define GPIO_GPPUR1 GPIO_GPPUR(1) |
| 1384 | #define GPIO_GPPUR2 GPIO_GPPUR(2) |
| 1385 | #define GPIO_GPPUR3 GPIO_GPPUR(3) |
| 1386 | #define GPIO_GPALR0 GPIO_GPALR(0) |
| 1387 | #define GPIO_GPALR1 GPIO_GPALR(1) |
| 1388 | #define GPIO_GPALR2 GPIO_GPALR(2) |
| 1389 | #define GPIO_GPALR3 GPIO_GPALR(3) |
| 1390 | #define GPIO_GPAUR0 GPIO_GPAUR(0) |
| 1391 | #define GPIO_GPAUR1 GPIO_GPAUR(1) |
| 1392 | #define GPIO_GPAUR2 GPIO_GPAUR(2) |
| 1393 | #define GPIO_GPAUR3 GPIO_GPAUR(3) |
| 1394 | #define GPIO_GPIDLR0 GPIO_GPIDLR(0) |
| 1395 | #define GPIO_GPIDLR1 GPIO_GPIDLR(1) |
| 1396 | #define GPIO_GPIDLR2 GPIO_GPIDLR(2) |
| 1397 | #define GPIO_GPIDLR3 GPIO_GPIDLR(3) |
| 1398 | #define GPIO_GPIDUR0 GPIO_GPIDUR(0) |
| 1399 | #define GPIO_GPIDUR1 GPIO_GPIDUR(1) |
| 1400 | #define GPIO_GPIDUR2 GPIO_GPIDUR(2) |
| 1401 | #define GPIO_GPIDUR3 GPIO_GPIDUR(3) |
| 1402 | #define GPIO_GPIER0 GPIO_GPIER(0) |
| 1403 | #define GPIO_GPIER1 GPIO_GPIER(1) |
| 1404 | #define GPIO_GPIER2 GPIO_GPIER(2) |
| 1405 | #define GPIO_GPIER3 GPIO_GPIER(3) |
| 1406 | #define GPIO_GPIMR0 GPIO_GPIMR(0) |
| 1407 | #define GPIO_GPIMR1 GPIO_GPIMR(1) |
| 1408 | #define GPIO_GPIMR2 GPIO_GPIMR(2) |
| 1409 | #define GPIO_GPIMR3 GPIO_GPIMR(3) |
| 1410 | #define GPIO_GPFR0 GPIO_GPFR(0) |
| 1411 | #define GPIO_GPFR1 GPIO_GPFR(1) |
| 1412 | #define GPIO_GPFR2 GPIO_GPFR(2) |
| 1413 | #define GPIO_GPFR3 GPIO_GPFR(3) |
| 1414 | |
| 1415 | |
| 1416 | /************************************************************************* |
| 1417 | * HARB |
| 1418 | *************************************************************************/ |
| 1419 | #define HARB_HAPOR (HARB_BASE + 0x000) |
| 1420 | #define HARB_HMCTR (HARB_BASE + 0x010) |
| 1421 | #define HARB_HME8H (HARB_BASE + 0x014) |
| 1422 | #define HARB_HMCR1 (HARB_BASE + 0x018) |
| 1423 | #define HARB_HMER2 (HARB_BASE + 0x01C) |
| 1424 | #define HARB_HMER3 (HARB_BASE + 0x020) |
| 1425 | #define HARB_HMLTR (HARB_BASE + 0x024) |
| 1426 | |
| 1427 | #define REG_HARB_HAPOR REG32(HARB_HAPOR) |
| 1428 | #define REG_HARB_HMCTR REG32(HARB_HMCTR) |
| 1429 | #define REG_HARB_HME8H REG32(HARB_HME8H) |
| 1430 | #define REG_HARB_HMCR1 REG32(HARB_HMCR1) |
| 1431 | #define REG_HARB_HMER2 REG32(HARB_HMER2) |
| 1432 | #define REG_HARB_HMER3 REG32(HARB_HMER3) |
| 1433 | #define REG_HARB_HMLTR REG32(HARB_HMLTR) |
| 1434 | |
| 1435 | /* HARB Priority Order Register (HARB_HAPOR) */ |
| 1436 | |
| 1437 | #define HARB_HAPOR_UCHSEL (1 << 7) |
| 1438 | #define HARB_HAPOR_PRIO_BIT 0 |
| 1439 | #define HARB_HAPOR_PRIO_MASK (0xf << HARB_HAPOR_PRIO_BIT) |
| 1440 | |
| 1441 | /* AHB Monitor Control Register (HARB_HMCTR) */ |
| 1442 | |
| 1443 | #define HARB_HMCTR_HET3_BIT 20 |
| 1444 | #define HARB_HMCTR_HET3_MASK (0xf << HARB_HMCTR_HET3_BIT) |
| 1445 | #define HARB_HMCTR_HMS3_BIT 16 |
| 1446 | #define HARB_HMCTR_HMS3_MASK (0xf << HARB_HMCTR_HMS3_BIT) |
| 1447 | #define HARB_HMCTR_HET2_BIT 12 |
| 1448 | #define HARB_HMCTR_HET2_MASK (0xf << HARB_HMCTR_HET2_BIT) |
| 1449 | #define HARB_HMCTR_HMS2_BIT 8 |
| 1450 | #define HARB_HMCTR_HMS2_MASK (0xf << HARB_HMCTR_HMS2_BIT) |
| 1451 | #define HARB_HMCTR_HOVF3 (1 << 7) |
| 1452 | #define HARB_HMCTR_HOVF2 (1 << 6) |
| 1453 | #define HARB_HMCTR_HOVF1 (1 << 5) |
| 1454 | #define HARB_HMCTR_HRST (1 << 4) |
| 1455 | #define HARB_HMCTR_HEE3 (1 << 2) |
| 1456 | #define HARB_HMCTR_HEE2 (1 << 1) |
| 1457 | #define HARB_HMCTR_HEE1 (1 << 0) |
| 1458 | |
| 1459 | /* AHB Monitor Event 8bits High Register (HARB_HME8H) */ |
| 1460 | |
| 1461 | #define HARB_HME8H_HC8H1_BIT 16 |
| 1462 | #define HARB_HME8H_HC8H1_MASK (0xff << HARB_HME8H_HC8H1_BIT) |
| 1463 | #define HARB_HME8H_HC8H2_BIT 8 |
| 1464 | #define HARB_HME8H_HC8H2_MASK (0xff << HARB_HME8H_HC8H2_BIT) |
| 1465 | #define HARB_HME8H_HC8H3_BIT 0 |
| 1466 | #define HARB_HME8H_HC8H3_MASK (0xff << HARB_HME8H_HC8H3_BIT) |
| 1467 | |
| 1468 | /* AHB Monitor Latency Register (HARB_HMLTR) */ |
| 1469 | |
| 1470 | #define HARB_HMLTR_HLT2_BIT 16 |
| 1471 | #define HARB_HMLTR_HLT2_MASK (0xffff << HARB_HMLTR_HLT2_BIT) |
| 1472 | #define HARB_HMLTR_HLT3_BIT 0 |
| 1473 | #define HARB_HMLTR_HLT3_MASK (0xffff << HARB_HMLTR_HLT3_BIT) |
| 1474 | |
| 1475 | |
| 1476 | |
| 1477 | |
| 1478 | /************************************************************************* |
| 1479 | * I2C |
| 1480 | *************************************************************************/ |
| 1481 | #define I2C_DR (I2C_BASE + 0x000) |
| 1482 | #define I2C_CR (I2C_BASE + 0x004) |
| 1483 | #define I2C_SR (I2C_BASE + 0x008) |
| 1484 | #define I2C_GR (I2C_BASE + 0x00C) |
| 1485 | |
| 1486 | #define REG_I2C_DR REG8(I2C_DR) |
| 1487 | #define REG_I2C_CR REG8(I2C_CR) |
| 1488 | #define REG_I2C_SR REG8(I2C_SR) |
| 1489 | #define REG_I2C_GR REG16(I2C_GR) |
| 1490 | |
| 1491 | /* I2C Control Register (I2C_CR) */ |
| 1492 | |
| 1493 | #define I2C_CR_IEN (1 << 4) |
| 1494 | #define I2C_CR_STA (1 << 3) |
| 1495 | #define I2C_CR_STO (1 << 2) |
| 1496 | #define I2C_CR_AC (1 << 1) |
| 1497 | #define I2C_CR_I2CE (1 << 0) |
| 1498 | |
| 1499 | /* I2C Status Register (I2C_SR) */ |
| 1500 | |
| 1501 | #define I2C_SR_STX (1 << 4) |
| 1502 | #define I2C_SR_BUSY (1 << 3) |
| 1503 | #define I2C_SR_TEND (1 << 2) |
| 1504 | #define I2C_SR_DRF (1 << 1) |
| 1505 | #define I2C_SR_ACKF (1 << 0) |
| 1506 | |
| 1507 | |
| 1508 | |
| 1509 | |
| 1510 | /************************************************************************* |
| 1511 | * UDC |
| 1512 | *************************************************************************/ |
| 1513 | #define UDC_EP0InCR (UDC_BASE + 0x00) |
| 1514 | #define UDC_EP0InSR (UDC_BASE + 0x04) |
| 1515 | #define UDC_EP0InBSR (UDC_BASE + 0x08) |
| 1516 | #define UDC_EP0InMPSR (UDC_BASE + 0x0c) |
| 1517 | #define UDC_EP0InDesR (UDC_BASE + 0x14) |
| 1518 | #define UDC_EP1InCR (UDC_BASE + 0x20) |
| 1519 | #define UDC_EP1InSR (UDC_BASE + 0x24) |
| 1520 | #define UDC_EP1InBSR (UDC_BASE + 0x28) |
| 1521 | #define UDC_EP1InMPSR (UDC_BASE + 0x2c) |
| 1522 | #define UDC_EP1InDesR (UDC_BASE + 0x34) |
| 1523 | #define UDC_EP2InCR (UDC_BASE + 0x40) |
| 1524 | #define UDC_EP2InSR (UDC_BASE + 0x44) |
| 1525 | #define UDC_EP2InBSR (UDC_BASE + 0x48) |
| 1526 | #define UDC_EP2InMPSR (UDC_BASE + 0x4c) |
| 1527 | #define UDC_EP2InDesR (UDC_BASE + 0x54) |
| 1528 | #define UDC_EP3InCR (UDC_BASE + 0x60) |
| 1529 | #define UDC_EP3InSR (UDC_BASE + 0x64) |
| 1530 | #define UDC_EP3InBSR (UDC_BASE + 0x68) |
| 1531 | #define UDC_EP3InMPSR (UDC_BASE + 0x6c) |
| 1532 | #define UDC_EP3InDesR (UDC_BASE + 0x74) |
| 1533 | #define UDC_EP4InCR (UDC_BASE + 0x80) |
| 1534 | #define UDC_EP4InSR (UDC_BASE + 0x84) |
| 1535 | #define UDC_EP4InBSR (UDC_BASE + 0x88) |
| 1536 | #define UDC_EP4InMPSR (UDC_BASE + 0x8c) |
| 1537 | #define UDC_EP4InDesR (UDC_BASE + 0x94) |
| 1538 | |
| 1539 | #define UDC_EP0OutCR (UDC_BASE + 0x200) |
| 1540 | #define UDC_EP0OutSR (UDC_BASE + 0x204) |
| 1541 | #define UDC_EP0OutPFNR (UDC_BASE + 0x208) |
| 1542 | #define UDC_EP0OutMPSR (UDC_BASE + 0x20c) |
| 1543 | #define UDC_EP0OutSBPR (UDC_BASE + 0x210) |
| 1544 | #define UDC_EP0OutDesR (UDC_BASE + 0x214) |
| 1545 | #define UDC_EP5OutCR (UDC_BASE + 0x2a0) |
| 1546 | #define UDC_EP5OutSR (UDC_BASE + 0x2a4) |
| 1547 | #define UDC_EP5OutPFNR (UDC_BASE + 0x2a8) |
| 1548 | #define UDC_EP5OutMPSR (UDC_BASE + 0x2ac) |
| 1549 | #define UDC_EP5OutDesR (UDC_BASE + 0x2b4) |
| 1550 | #define UDC_EP6OutCR (UDC_BASE + 0x2c0) |
| 1551 | #define UDC_EP6OutSR (UDC_BASE + 0x2c4) |
| 1552 | #define UDC_EP6OutPFNR (UDC_BASE + 0x2c8) |
| 1553 | #define UDC_EP6OutMPSR (UDC_BASE + 0x2cc) |
| 1554 | #define UDC_EP6OutDesR (UDC_BASE + 0x2d4) |
| 1555 | #define UDC_EP7OutCR (UDC_BASE + 0x2e0) |
| 1556 | #define UDC_EP7OutSR (UDC_BASE + 0x2e4) |
| 1557 | #define UDC_EP7OutPFNR (UDC_BASE + 0x2e8) |
| 1558 | #define UDC_EP7OutMPSR (UDC_BASE + 0x2ec) |
| 1559 | #define UDC_EP7OutDesR (UDC_BASE + 0x2f4) |
| 1560 | |
| 1561 | #define UDC_DevCFGR (UDC_BASE + 0x400) |
| 1562 | #define UDC_DevCR (UDC_BASE + 0x404) |
| 1563 | #define UDC_DevSR (UDC_BASE + 0x408) |
| 1564 | #define UDC_DevIntR (UDC_BASE + 0x40c) |
| 1565 | #define UDC_DevIntMR (UDC_BASE + 0x410) |
| 1566 | #define UDC_EPIntR (UDC_BASE + 0x414) |
| 1567 | #define UDC_EPIntMR (UDC_BASE + 0x418) |
| 1568 | |
| 1569 | #define UDC_STCMAR (UDC_BASE + 0x500) |
| 1570 | #define UDC_EP0InfR (UDC_BASE + 0x504) |
| 1571 | #define UDC_EP1InfR (UDC_BASE + 0x508) |
| 1572 | #define UDC_EP2InfR (UDC_BASE + 0x50c) |
| 1573 | #define UDC_EP3InfR (UDC_BASE + 0x510) |
| 1574 | #define UDC_EP4InfR (UDC_BASE + 0x514) |
| 1575 | #define UDC_EP5InfR (UDC_BASE + 0x518) |
| 1576 | #define UDC_EP6InfR (UDC_BASE + 0x51c) |
| 1577 | #define UDC_EP7InfR (UDC_BASE + 0x520) |
| 1578 | |
| 1579 | #define UDC_TXCONFIRM (UDC_BASE + 0x41C) |
| 1580 | #define UDC_TXZLP (UDC_BASE + 0x420) |
| 1581 | #define UDC_RXCONFIRM (UDC_BASE + 0x41C) |
| 1582 | |
| 1583 | #define UDC_RXFIFO (UDC_BASE + 0x800) |
| 1584 | #define UDC_TXFIFOEP0 (UDC_BASE + 0x840) |
| 1585 | |
| 1586 | #define REG_UDC_EP0InCR REG32(UDC_EP0InCR) |
| 1587 | #define REG_UDC_EP0InSR REG32(UDC_EP0InSR) |
| 1588 | #define REG_UDC_EP0InBSR REG32(UDC_EP0InBSR) |
| 1589 | #define REG_UDC_EP0InMPSR REG32(UDC_EP0InMPSR) |
| 1590 | #define REG_UDC_EP0InDesR REG32(UDC_EP0InDesR) |
| 1591 | #define REG_UDC_EP1InCR REG32(UDC_EP1InCR) |
| 1592 | #define REG_UDC_EP1InSR REG32(UDC_EP1InSR) |
| 1593 | #define REG_UDC_EP1InBSR REG32(UDC_EP1InBSR) |
| 1594 | #define REG_UDC_EP1InMPSR REG32(UDC_EP1InMPSR) |
| 1595 | #define REG_UDC_EP1InDesR REG32(UDC_EP1InDesR) |
| 1596 | #define REG_UDC_EP2InCR REG32(UDC_EP2InCR) |
| 1597 | #define REG_UDC_EP2InSR REG32(UDC_EP2InSR) |
| 1598 | #define REG_UDC_EP2InBSR REG32(UDC_EP2InBSR) |
| 1599 | #define REG_UDC_EP2InMPSR REG32(UDC_EP2InMPSR) |
| 1600 | #define REG_UDC_EP2InDesR REG32(UDC_EP2InDesR) |
| 1601 | #define REG_UDC_EP3InCR REG32(UDC_EP3InCR) |
| 1602 | #define REG_UDC_EP3InSR REG32(UDC_EP3InSR) |
| 1603 | #define REG_UDC_EP3InBSR REG32(UDC_EP3InBSR) |
| 1604 | #define REG_UDC_EP3InMPSR REG32(UDC_EP3InMPSR) |
| 1605 | #define REG_UDC_EP3InDesR REG32(UDC_EP3InDesR) |
| 1606 | #define REG_UDC_EP4InCR REG32(UDC_EP4InCR) |
| 1607 | #define REG_UDC_EP4InSR REG32(UDC_EP4InSR) |
| 1608 | #define REG_UDC_EP4InBSR REG32(UDC_EP4InBSR) |
| 1609 | #define REG_UDC_EP4InMPSR REG32(UDC_EP4InMPSR) |
| 1610 | #define REG_UDC_EP4InDesR REG32(UDC_EP4InDesR) |
| 1611 | |
| 1612 | #define REG_UDC_EP0OutCR REG32(UDC_EP0OutCR) |
| 1613 | #define REG_UDC_EP0OutSR REG32(UDC_EP0OutSR) |
| 1614 | #define REG_UDC_EP0OutPFNR REG32(UDC_EP0OutPFNR) |
| 1615 | #define REG_UDC_EP0OutMPSR REG32(UDC_EP0OutMPSR) |
| 1616 | #define REG_UDC_EP0OutSBPR REG32(UDC_EP0OutSBPR) |
| 1617 | #define REG_UDC_EP0OutDesR REG32(UDC_EP0OutDesR) |
| 1618 | #define REG_UDC_EP5OutCR REG32(UDC_EP5OutCR) |
| 1619 | #define REG_UDC_EP5OutSR REG32(UDC_EP5OutSR) |
| 1620 | #define REG_UDC_EP5OutPFNR REG32(UDC_EP5OutPFNR) |
| 1621 | #define REG_UDC_EP5OutMPSR REG32(UDC_EP5OutMPSR) |
| 1622 | #define REG_UDC_EP5OutDesR REG32(UDC_EP5OutDesR) |
| 1623 | #define REG_UDC_EP6OutCR REG32(UDC_EP6OutCR) |
| 1624 | #define REG_UDC_EP6OutSR REG32(UDC_EP6OutSR) |
| 1625 | #define REG_UDC_EP6OutPFNR REG32(UDC_EP6OutPFNR) |
| 1626 | #define REG_UDC_EP6OutMPSR REG32(UDC_EP6OutMPSR) |
| 1627 | #define REG_UDC_EP6OutDesR REG32(UDC_EP6OutDesR) |
| 1628 | #define REG_UDC_EP7OutCR REG32(UDC_EP7OutCR) |
| 1629 | #define REG_UDC_EP7OutSR REG32(UDC_EP7OutSR) |
| 1630 | #define REG_UDC_EP7OutPFNR REG32(UDC_EP7OutPFNR) |
| 1631 | #define REG_UDC_EP7OutMPSR REG32(UDC_EP7OutMPSR) |
| 1632 | #define REG_UDC_EP7OutDesR REG32(UDC_EP7OutDesR) |
| 1633 | |
| 1634 | #define REG_UDC_DevCFGR REG32(UDC_DevCFGR) |
| 1635 | #define REG_UDC_DevCR REG32(UDC_DevCR) |
| 1636 | #define REG_UDC_DevSR REG32(UDC_DevSR) |
| 1637 | #define REG_UDC_DevIntR REG32(UDC_DevIntR) |
| 1638 | #define REG_UDC_DevIntMR REG32(UDC_DevIntMR) |
| 1639 | #define REG_UDC_EPIntR REG32(UDC_EPIntR) |
| 1640 | #define REG_UDC_EPIntMR REG32(UDC_EPIntMR) |
| 1641 | |
| 1642 | #define REG_UDC_STCMAR REG32(UDC_STCMAR) |
| 1643 | #define REG_UDC_EP0InfR REG32(UDC_EP0InfR) |
| 1644 | #define REG_UDC_EP1InfR REG32(UDC_EP1InfR) |
| 1645 | #define REG_UDC_EP2InfR REG32(UDC_EP2InfR) |
| 1646 | #define REG_UDC_EP3InfR REG32(UDC_EP3InfR) |
| 1647 | #define REG_UDC_EP4InfR REG32(UDC_EP4InfR) |
| 1648 | #define REG_UDC_EP5InfR REG32(UDC_EP5InfR) |
| 1649 | #define REG_UDC_EP6InfR REG32(UDC_EP6InfR) |
| 1650 | #define REG_UDC_EP7InfR REG32(UDC_EP7InfR) |
| 1651 | |
| 1652 | #define UDC_DevCFGR_PI (1 << 5) |
| 1653 | #define UDC_DevCFGR_SS (1 << 4) |
| 1654 | #define UDC_DevCFGR_SP (1 << 3) |
| 1655 | #define UDC_DevCFGR_RW (1 << 2) |
| 1656 | #define UDC_DevCFGR_SPD_BIT 0 |
| 1657 | #define UDC_DevCFGR_SPD_MASK (0x03 << UDC_DevCFGR_SPD_BIT) |
| 1658 | #define UDC_DevCFGR_SPD_HS (0 << UDC_DevCFGR_SPD_BIT) |
| 1659 | #define UDC_DevCFGR_SPD_LS (2 << UDC_DevCFGR_SPD_BIT) |
| 1660 | #define UDC_DevCFGR_SPD_FS (3 << UDC_DevCFGR_SPD_BIT) |
| 1661 | |
| 1662 | #define UDC_DevCR_DM (1 << 9) |
| 1663 | #define UDC_DevCR_BE (1 << 5) |
| 1664 | #define UDC_DevCR_RES (1 << 0) |
| 1665 | |
| 1666 | #define UDC_DevSR_ENUMSPD_BIT 13 |
| 1667 | #define UDC_DevSR_ENUMSPD_MASK (0x03 << UDC_DevSR_ENUMSPD_BIT) |
| 1668 | #define UDC_DevSR_ENUMSPD_HS (0 << UDC_DevSR_ENUMSPD_BIT) |
| 1669 | #define UDC_DevSR_ENUMSPD_LS (2 << UDC_DevSR_ENUMSPD_BIT) |
| 1670 | #define UDC_DevSR_ENUMSPD_FS (3 << UDC_DevSR_ENUMSPD_BIT) |
| 1671 | #define UDC_DevSR_SUSP (1 << 12) |
| 1672 | #define UDC_DevSR_ALT_BIT 8 |
| 1673 | #define UDC_DevSR_ALT_MASK (0x0f << UDC_DevSR_ALT_BIT) |
| 1674 | #define UDC_DevSR_INTF_BIT 4 |
| 1675 | #define UDC_DevSR_INTF_MASK (0x0f << UDC_DevSR_INTF_BIT) |
| 1676 | #define UDC_DevSR_CFG_BIT 0 |
| 1677 | #define UDC_DevSR_CFG_MASK (0x0f << UDC_DevSR_CFG_BIT) |
| 1678 | |
| 1679 | #define UDC_DevIntR_ENUM (1 << 6) |
| 1680 | #define UDC_DevIntR_SOF (1 << 5) |
| 1681 | #define UDC_DevIntR_US (1 << 4) |
| 1682 | #define UDC_DevIntR_UR (1 << 3) |
| 1683 | #define UDC_DevIntR_SI (1 << 1) |
| 1684 | #define UDC_DevIntR_SC (1 << 0) |
| 1685 | |
| 1686 | #define UDC_EPIntR_OUTEP_BIT 16 |
| 1687 | #define UDC_EPIntR_OUTEP_MASK (0xffff << UDC_EPIntR_OUTEP_BIT) |
| 1688 | #define UDC_EPIntR_OUTEP0 0x00010000 |
| 1689 | #define UDC_EPIntR_OUTEP5 0x00200000 |
| 1690 | #define UDC_EPIntR_OUTEP6 0x00400000 |
| 1691 | #define UDC_EPIntR_OUTEP7 0x00800000 |
| 1692 | #define UDC_EPIntR_INEP_BIT 0 |
| 1693 | #define UDC_EPIntR_INEP_MASK (0xffff << UDC_EPIntR_INEP_BIT) |
| 1694 | #define UDC_EPIntR_INEP0 0x00000001 |
| 1695 | #define UDC_EPIntR_INEP1 0x00000002 |
| 1696 | #define UDC_EPIntR_INEP2 0x00000004 |
| 1697 | #define UDC_EPIntR_INEP3 0x00000008 |
| 1698 | #define UDC_EPIntR_INEP4 0x00000010 |
| 1699 | |
| 1700 | |
| 1701 | #define UDC_EPIntMR_OUTEP_BIT 16 |
| 1702 | #define UDC_EPIntMR_OUTEP_MASK (0xffff << UDC_EPIntMR_OUTEP_BIT) |
| 1703 | #define UDC_EPIntMR_INEP_BIT 0 |
| 1704 | #define UDC_EPIntMR_INEP_MASK (0xffff << UDC_EPIntMR_INEP_BIT) |
| 1705 | |
| 1706 | #define UDC_EPCR_ET_BIT 4 |
| 1707 | #define UDC_EPCR_ET_MASK (0x03 << UDC_EPCR_ET_BIT) |
| 1708 | #define UDC_EPCR_ET_CTRL (0 << UDC_EPCR_ET_BIT) |
| 1709 | #define UDC_EPCR_ET_ISO (1 << UDC_EPCR_ET_BIT) |
| 1710 | #define UDC_EPCR_ET_BULK (2 << UDC_EPCR_ET_BIT) |
| 1711 | #define UDC_EPCR_ET_INTR (3 << UDC_EPCR_ET_BIT) |
| 1712 | #define UDC_EPCR_SN (1 << 2) |
| 1713 | #define UDC_EPCR_F (1 << 1) |
| 1714 | #define UDC_EPCR_S (1 << 0) |
| 1715 | |
| 1716 | #define UDC_EPSR_RXPKTSIZE_BIT 11 |
| 1717 | #define UDC_EPSR_RXPKTSIZE_MASK (0x7ff << UDC_EPSR_RXPKTSIZE_BIT) |
| 1718 | #define UDC_EPSR_IN (1 << 6) |
| 1719 | #define UDC_EPSR_OUT_BIT 4 |
| 1720 | #define UDC_EPSR_OUT_MASK (0x03 << UDC_EPSR_OUT_BIT) |
| 1721 | #define UDC_EPSR_OUT_NONE (0 << UDC_EPSR_OUT_BIT) |
| 1722 | #define UDC_EPSR_OUT_RCVDATA (1 << UDC_EPSR_OUT_BIT) |
| 1723 | #define UDC_EPSR_OUT_RCVSETUP (2 << UDC_EPSR_OUT_BIT) |
| 1724 | #define UDC_EPSR_PID_BIT 0 |
| 1725 | #define UDC_EPSR_PID_MASK (0x0f << UDC_EPSR_PID_BIT) |
| 1726 | |
| 1727 | #define UDC_EPInfR_MPS_BIT 19 |
| 1728 | #define UDC_EPInfR_MPS_MASK (0x3ff << UDC_EPInfR_MPS_BIT) |
| 1729 | #define UDC_EPInfR_ALTS_BIT 15 |
| 1730 | #define UDC_EPInfR_ALTS_MASK (0x0f << UDC_EPInfR_ALTS_BIT) |
| 1731 | #define UDC_EPInfR_IFN_BIT 11 |
| 1732 | #define UDC_EPInfR_IFN_MASK (0x0f << UDC_EPInfR_IFN_BIT) |
| 1733 | #define UDC_EPInfR_CGN_BIT 7 |
| 1734 | #define UDC_EPInfR_CGN_MASK (0x0f << UDC_EPInfR_CGN_BIT) |
| 1735 | #define UDC_EPInfR_EPT_BIT 5 |
| 1736 | #define UDC_EPInfR_EPT_MASK (0x03 << UDC_EPInfR_EPT_BIT) |
| 1737 | #define UDC_EPInfR_EPT_CTRL (0 << UDC_EPInfR_EPT_BIT) |
| 1738 | #define UDC_EPInfR_EPT_ISO (1 << UDC_EPInfR_EPT_BIT) |
| 1739 | #define UDC_EPInfR_EPT_BULK (2 << UDC_EPInfR_EPT_BIT) |
| 1740 | #define UDC_EPInfR_EPT_INTR (3 << UDC_EPInfR_EPT_BIT) |
| 1741 | #define UDC_EPInfR_EPD (1 << 4) |
| 1742 | #define UDC_EPInfR_EPD_OUT (0 << 4) |
| 1743 | #define UDC_EPInfR_EPD_IN (1 << 4) |
| 1744 | |
| 1745 | #define UDC_EPInfR_EPN_BIT 0 |
| 1746 | #define UDC_EPInfR_EPN_MASK (0xf << UDC_EPInfR_EPN_BIT) |
| 1747 | |
| 1748 | |
| 1749 | |
| 1750 | |
| 1751 | /************************************************************************* |
| 1752 | * DMAC |
| 1753 | *************************************************************************/ |
| 1754 | #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) |
| 1755 | #define DMAC_DDAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) |
| 1756 | #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) |
| 1757 | #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) |
| 1758 | #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) |
| 1759 | #define DMAC_DMAIPR (DMAC_BASE + 0xf8) |
| 1760 | #define DMAC_DMACR (DMAC_BASE + 0xfc) |
| 1761 | |
| 1762 | #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) |
| 1763 | #define REG_DMAC_DDAR(n) REG32(DMAC_DDAR((n))) |
| 1764 | #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) |
| 1765 | #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) |
| 1766 | #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) |
| 1767 | #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) |
| 1768 | #define REG_DMAC_DMACR REG32(DMAC_DMACR) |
| 1769 | |
| 1770 | #define DMAC_DRSR_RS_BIT 0 |
| 1771 | #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) |
| 1772 | #define DMAC_DRSR_RS_EXTREXTR (0 << DMAC_DRSR_RS_BIT) |
| 1773 | #define DMAC_DRSR_RS_PCMCIAOUT (4 << DMAC_DRSR_RS_BIT) |
| 1774 | #define DMAC_DRSR_RS_PCMCIAIN (5 << DMAC_DRSR_RS_BIT) |
| 1775 | #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) |
| 1776 | #define DMAC_DRSR_RS_DESOUT (10 << DMAC_DRSR_RS_BIT) |
| 1777 | #define DMAC_DRSR_RS_DESIN (11 << DMAC_DRSR_RS_BIT) |
| 1778 | #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT) |
| 1779 | #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT) |
| 1780 | #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT) |
| 1781 | #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT) |
| 1782 | #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT) |
| 1783 | #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT) |
| 1784 | #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) |
| 1785 | #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) |
| 1786 | #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) |
| 1787 | #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) |
| 1788 | #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) |
| 1789 | #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) |
| 1790 | #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) |
| 1791 | #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) |
| 1792 | #define DMAC_DRSR_RS_OST2 (28 << DMAC_DRSR_RS_BIT) |
| 1793 | |
| 1794 | #define DMAC_DCCSR_EACKS (1 << 31) |
| 1795 | #define DMAC_DCCSR_EACKM (1 << 30) |
| 1796 | #define DMAC_DCCSR_ERDM_BIT 28 |
| 1797 | #define DMAC_DCCSR_ERDM_MASK (0x03 << DMAC_DCCSR_ERDM_BIT) |
| 1798 | #define DMAC_DCCSR_ERDM_LLEVEL (0 << DMAC_DCCSR_ERDM_BIT) |
| 1799 | #define DMAC_DCCSR_ERDM_FEDGE (1 << DMAC_DCCSR_ERDM_BIT) |
| 1800 | #define DMAC_DCCSR_ERDM_HLEVEL (2 << DMAC_DCCSR_ERDM_BIT) |
| 1801 | #define DMAC_DCCSR_ERDM_REDGE (3 << DMAC_DCCSR_ERDM_BIT) |
| 1802 | #define DMAC_DCCSR_EOPM (1 << 27) |
| 1803 | #define DMAC_DCCSR_SAM (1 << 23) |
| 1804 | #define DMAC_DCCSR_DAM (1 << 22) |
| 1805 | #define DMAC_DCCSR_RDIL_BIT 16 |
| 1806 | #define DMAC_DCCSR_RDIL_MASK (0x0f << DMAC_DCCSR_RDIL_BIT) |
| 1807 | #define DMAC_DCCSR_RDIL_IGN (0 << DMAC_DCCSR_RDIL_BIT) |
| 1808 | #define DMAC_DCCSR_RDIL_2 (1 << DMAC_DCCSR_RDIL_BIT) |
| 1809 | #define DMAC_DCCSR_RDIL_4 (2 << DMAC_DCCSR_RDIL_BIT) |
| 1810 | #define DMAC_DCCSR_RDIL_8 (3 << DMAC_DCCSR_RDIL_BIT) |
| 1811 | #define DMAC_DCCSR_RDIL_12 (4 << DMAC_DCCSR_RDIL_BIT) |
| 1812 | #define DMAC_DCCSR_RDIL_16 (5 << DMAC_DCCSR_RDIL_BIT) |
| 1813 | #define DMAC_DCCSR_RDIL_20 (6 << DMAC_DCCSR_RDIL_BIT) |
| 1814 | #define DMAC_DCCSR_RDIL_24 (7 << DMAC_DCCSR_RDIL_BIT) |
| 1815 | #define DMAC_DCCSR_RDIL_28 (8 << DMAC_DCCSR_RDIL_BIT) |
| 1816 | #define DMAC_DCCSR_RDIL_32 (9 << DMAC_DCCSR_RDIL_BIT) |
| 1817 | #define DMAC_DCCSR_RDIL_48 (10 << DMAC_DCCSR_RDIL_BIT) |
| 1818 | #define DMAC_DCCSR_RDIL_60 (11 << DMAC_DCCSR_RDIL_BIT) |
| 1819 | #define DMAC_DCCSR_RDIL_64 (12 << DMAC_DCCSR_RDIL_BIT) |
| 1820 | #define DMAC_DCCSR_RDIL_124 (13 << DMAC_DCCSR_RDIL_BIT) |
| 1821 | #define DMAC_DCCSR_RDIL_128 (14 << DMAC_DCCSR_RDIL_BIT) |
| 1822 | #define DMAC_DCCSR_RDIL_200 (15 << DMAC_DCCSR_RDIL_BIT) |
| 1823 | #define DMAC_DCCSR_SWDH_BIT 14 |
| 1824 | #define DMAC_DCCSR_SWDH_MASK (0x03 << DMAC_DCCSR_SWDH_BIT) |
| 1825 | #define DMAC_DCCSR_SWDH_32 (0 << DMAC_DCCSR_SWDH_BIT) |
| 1826 | #define DMAC_DCCSR_SWDH_8 (1 << DMAC_DCCSR_SWDH_BIT) |
| 1827 | #define DMAC_DCCSR_SWDH_16 (2 << DMAC_DCCSR_SWDH_BIT) |
| 1828 | #define DMAC_DCCSR_DWDH_BIT 12 |
| 1829 | #define DMAC_DCCSR_DWDH_MASK (0x03 << DMAC_DCCSR_DWDH_BIT) |
| 1830 | #define DMAC_DCCSR_DWDH_32 (0 << DMAC_DCCSR_DWDH_BIT) |
| 1831 | #define DMAC_DCCSR_DWDH_8 (1 << DMAC_DCCSR_DWDH_BIT) |
| 1832 | #define DMAC_DCCSR_DWDH_16 (2 << DMAC_DCCSR_DWDH_BIT) |
| 1833 | #define DMAC_DCCSR_DS_BIT 8 |
| 1834 | #define DMAC_DCCSR_DS_MASK (0x07 << DMAC_DCCSR_DS_BIT) |
| 1835 | #define DMAC_DCCSR_DS_32b (0 << DMAC_DCCSR_DS_BIT) |
| 1836 | #define DMAC_DCCSR_DS_8b (1 << DMAC_DCCSR_DS_BIT) |
| 1837 | #define DMAC_DCCSR_DS_16b (2 << DMAC_DCCSR_DS_BIT) |
| 1838 | #define DMAC_DCCSR_DS_16B (3 << DMAC_DCCSR_DS_BIT) |
| 1839 | #define DMAC_DCCSR_DS_32B (4 << DMAC_DCCSR_DS_BIT) |
| 1840 | #define DMAC_DCCSR_TM (1 << 7) |
| 1841 | #define DMAC_DCCSR_AR (1 << 4) |
| 1842 | #define DMAC_DCCSR_TC (1 << 3) |
| 1843 | #define DMAC_DCCSR_HLT (1 << 2) |
| 1844 | #define DMAC_DCCSR_TCIE (1 << 1) |
| 1845 | #define DMAC_DCCSR_CHDE (1 << 0) |
| 1846 | |
| 1847 | #define DMAC_DMAIPR_CINT_BIT 8 |
| 1848 | #define DMAC_DMAIPR_CINT_MASK (0xff << DMAC_DMAIPR_CINT_BIT) |
| 1849 | |
| 1850 | #define DMAC_DMACR_PR_BIT 8 |
| 1851 | #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) |
| 1852 | #define DMAC_DMACR_PR_01234567 (0 << DMAC_DMACR_PR_BIT) |
| 1853 | #define DMAC_DMACR_PR_02314675 (1 << DMAC_DMACR_PR_BIT) |
| 1854 | #define DMAC_DMACR_PR_20136457 (2 << DMAC_DMACR_PR_BIT) |
| 1855 | #define DMAC_DMACR_PR_ROUNDROBIN (3 << DMAC_DMACR_PR_BIT) |
| 1856 | #define DMAC_DMACR_HTR (1 << 3) |
| 1857 | #define DMAC_DMACR_AER (1 << 2) |
| 1858 | #define DMAC_DMACR_DME (1 << 0) |
| 1859 | |
| 1860 | #define IRQ_DMA_0 32 |
| 1861 | #define NUM_DMA 6 |
| 1862 | |
| 1863 | |
| 1864 | /************************************************************************* |
| 1865 | * AIC |
| 1866 | *************************************************************************/ |
| 1867 | #define AIC_FR (AIC_BASE + 0x000) |
| 1868 | #define AIC_CR (AIC_BASE + 0x004) |
| 1869 | #define AIC_ACCR1 (AIC_BASE + 0x008) |
| 1870 | #define AIC_ACCR2 (AIC_BASE + 0x00C) |
| 1871 | #define AIC_I2SCR (AIC_BASE + 0x010) |
| 1872 | #define AIC_SR (AIC_BASE + 0x014) |
| 1873 | #define AIC_ACSR (AIC_BASE + 0x018) |
| 1874 | #define AIC_I2SSR (AIC_BASE + 0x01C) |
| 1875 | #define AIC_ACCAR (AIC_BASE + 0x020) |
| 1876 | #define AIC_ACCDR (AIC_BASE + 0x024) |
| 1877 | #define AIC_ACSAR (AIC_BASE + 0x028) |
| 1878 | #define AIC_ACSDR (AIC_BASE + 0x02C) |
| 1879 | #define AIC_I2SDIV (AIC_BASE + 0x030) |
| 1880 | #define AIC_DR (AIC_BASE + 0x034) |
| 1881 | |
| 1882 | #define REG_AIC_FR REG32(AIC_FR) |
| 1883 | #define REG_AIC_CR REG32(AIC_CR) |
| 1884 | #define REG_AIC_ACCR1 REG32(AIC_ACCR1) |
| 1885 | #define REG_AIC_ACCR2 REG32(AIC_ACCR2) |
| 1886 | #define REG_AIC_I2SCR REG32(AIC_I2SCR) |
| 1887 | #define REG_AIC_SR REG32(AIC_SR) |
| 1888 | #define REG_AIC_ACSR REG32(AIC_ACSR) |
| 1889 | #define REG_AIC_I2SSR REG32(AIC_I2SSR) |
| 1890 | #define REG_AIC_ACCAR REG32(AIC_ACCAR) |
| 1891 | #define REG_AIC_ACCDR REG32(AIC_ACCDR) |
| 1892 | #define REG_AIC_ACSAR REG32(AIC_ACSAR) |
| 1893 | #define REG_AIC_ACSDR REG32(AIC_ACSDR) |
| 1894 | #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) |
| 1895 | #define REG_AIC_DR REG32(AIC_DR) |
| 1896 | |
| 1897 | /* AIC Controller Configuration Register (AIC_FR) */ |
| 1898 | |
| 1899 | #define AIC_FR_RFTH_BIT 12 |
| 1900 | #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) |
| 1901 | #define AIC_FR_TFTH_BIT 8 |
| 1902 | #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) |
| 1903 | #define AIC_FR_AUSEL (1 << 4) |
| 1904 | #define AIC_FR_RST (1 << 3) |
| 1905 | #define AIC_FR_BCKD (1 << 2) |
| 1906 | #define AIC_FR_SYNCD (1 << 1) |
| 1907 | #define AIC_FR_ENB (1 << 0) |
| 1908 | |
| 1909 | /* AIC Controller Common Control Register (AIC_CR) */ |
| 1910 | |
| 1911 | #define AIC_CR_RDMS (1 << 15) |
| 1912 | #define AIC_CR_TDMS (1 << 14) |
| 1913 | #define AIC_CR_FLUSH (1 << 8) |
| 1914 | #define AIC_CR_EROR (1 << 6) |
| 1915 | #define AIC_CR_ETUR (1 << 5) |
| 1916 | #define AIC_CR_ERFS (1 << 4) |
| 1917 | #define AIC_CR_ETFS (1 << 3) |
| 1918 | #define AIC_CR_ENLBF (1 << 2) |
| 1919 | #define AIC_CR_ERPL (1 << 1) |
| 1920 | #define AIC_CR_EREC (1 << 0) |
| 1921 | |
| 1922 | /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ |
| 1923 | |
| 1924 | #define AIC_ACCR1_RS_BIT 16 |
| 1925 | #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) |
| 1926 | #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ |
| 1927 | #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ |
| 1928 | #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ |
| 1929 | #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit */ |
| 1930 | #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit */ |
| 1931 | #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit */ |
| 1932 | #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit */ |
| 1933 | #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ |
| 1934 | #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit */ |
| 1935 | #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit */ |
| 1936 | #define AIC_ACCR1_XS_BIT 0 |
| 1937 | #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) |
| 1938 | #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ |
| 1939 | #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ |
| 1940 | #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ |
| 1941 | #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit */ |
| 1942 | #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit */ |
| 1943 | #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit */ |
| 1944 | #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit */ |
| 1945 | #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ |
| 1946 | #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit */ |
| 1947 | #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit */ |
| 1948 | |
| 1949 | /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ |
| 1950 | |
| 1951 | #define AIC_ACCR2_ERSTO (1 << 18) |
| 1952 | #define AIC_ACCR2_ESADR (1 << 17) |
| 1953 | #define AIC_ACCR2_ECADT (1 << 16) |
| 1954 | #define AIC_ACCR2_OASS_BIT 8 |
| 1955 | #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) |
| 1956 | #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ |
| 1957 | #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ |
| 1958 | #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ |
| 1959 | #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ |
| 1960 | #define AIC_ACCR2_IASS_BIT 6 |
| 1961 | #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) |
| 1962 | #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ |
| 1963 | #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ |
| 1964 | #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ |
| 1965 | #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ |
| 1966 | #define AIC_ACCR2_SO (1 << 3) |
| 1967 | #define AIC_ACCR2_SR (1 << 2) |
| 1968 | #define AIC_ACCR2_SS (1 << 1) |
| 1969 | #define AIC_ACCR2_SA (1 << 0) |
| 1970 | |
| 1971 | /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ |
| 1972 | |
| 1973 | #define AIC_I2SCR_STPBK (1 << 12) |
| 1974 | #define AIC_I2SCR_WL_BIT 1 |
| 1975 | #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) |
| 1976 | #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ |
| 1977 | #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ |
| 1978 | #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ |
| 1979 | #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ |
| 1980 | #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ |
| 1981 | #define AIC_I2SCR_AMSL (1 << 0) |
| 1982 | |
| 1983 | /* AIC Controller FIFO Status Register (AIC_SR) */ |
| 1984 | |
| 1985 | #define AIC_SR_RFL_BIT 24 |
| 1986 | #define AIC_SR_RFL_MASK (0x1f << AIC_SR_RFL_BIT) |
| 1987 | #define AIC_SR_TFL_BIT 8 |
| 1988 | #define AIC_SR_TFL_MASK (0x1f << AIC_SR_TFL_BIT) |
| 1989 | #define AIC_SR_ROR (1 << 6) |
| 1990 | #define AIC_SR_TUR (1 << 5) |
| 1991 | #define AIC_SR_RFS (1 << 4) |
| 1992 | #define AIC_SR_TFS (1 << 3) |
| 1993 | |
| 1994 | /* AIC Controller AC-link Status Register (AIC_ACSR) */ |
| 1995 | |
| 1996 | #define AIC_ACSR_CRDY (1 << 20) |
| 1997 | #define AIC_ACSR_CLPM (1 << 19) |
| 1998 | #define AIC_ACSR_RSTO (1 << 18) |
| 1999 | #define AIC_ACSR_SADR (1 << 17) |
| 2000 | #define AIC_ACSR_CADT (1 << 16) |
| 2001 | |
| 2002 | /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ |
| 2003 | |
| 2004 | #define AIC_I2SSR_BSY (1 << 2) |
| 2005 | |
| 2006 | /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ |
| 2007 | |
| 2008 | #define AIC_ACCAR_CAR_BIT 0 |
| 2009 | #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) |
| 2010 | |
| 2011 | /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ |
| 2012 | |
| 2013 | #define AIC_ACCDR_CDR_BIT 0 |
| 2014 | #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) |
| 2015 | |
| 2016 | /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ |
| 2017 | |
| 2018 | #define AIC_ACSAR_SAR_BIT 0 |
| 2019 | #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) |
| 2020 | |
| 2021 | /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ |
| 2022 | |
| 2023 | #define AIC_ACSDR_SDR_BIT 0 |
| 2024 | #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) |
| 2025 | |
| 2026 | /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ |
| 2027 | |
| 2028 | #define AIC_I2SDIV_DIV_BIT 0 |
| 2029 | #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) |
| 2030 | #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ |
| 2031 | #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ |
| 2032 | #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ |
| 2033 | #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ |
| 2034 | #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ |
| 2035 | #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ |
| 2036 | |
| 2037 | |
| 2038 | |
| 2039 | |
| 2040 | /************************************************************************* |
| 2041 | * LCD |
| 2042 | *************************************************************************/ |
| 2043 | #define LCD_CFG (LCD_BASE + 0x00) |
| 2044 | #define LCD_VSYNC (LCD_BASE + 0x04) |
| 2045 | #define LCD_HSYNC (LCD_BASE + 0x08) |
| 2046 | #define LCD_VAT (LCD_BASE + 0x0c) |
| 2047 | #define LCD_DAH (LCD_BASE + 0x10) |
| 2048 | #define LCD_DAV (LCD_BASE + 0x14) |
| 2049 | #define LCD_PS (LCD_BASE + 0x18) |
| 2050 | #define LCD_CLS (LCD_BASE + 0x1c) |
| 2051 | #define LCD_SPL (LCD_BASE + 0x20) |
| 2052 | #define LCD_REV (LCD_BASE + 0x24) |
| 2053 | #define LCD_CTRL (LCD_BASE + 0x30) |
| 2054 | #define LCD_STATE (LCD_BASE + 0x34) |
| 2055 | #define LCD_IID (LCD_BASE + 0x38) |
| 2056 | #define LCD_DA0 (LCD_BASE + 0x40) |
| 2057 | #define LCD_SA0 (LCD_BASE + 0x44) |
| 2058 | #define LCD_FID0 (LCD_BASE + 0x48) |
| 2059 | #define LCD_CMD0 (LCD_BASE + 0x4c) |
| 2060 | #define LCD_DA1 (LCD_BASE + 0x50) |
| 2061 | #define LCD_SA1 (LCD_BASE + 0x54) |
| 2062 | #define LCD_FID1 (LCD_BASE + 0x58) |
| 2063 | #define LCD_CMD1 (LCD_BASE + 0x5c) |
| 2064 | |
| 2065 | #define REG_LCD_CFG REG32(LCD_CFG) |
| 2066 | #define REG_LCD_VSYNC REG32(LCD_VSYNC) |
| 2067 | #define REG_LCD_HSYNC REG32(LCD_HSYNC) |
| 2068 | #define REG_LCD_VAT REG32(LCD_VAT) |
| 2069 | #define REG_LCD_DAH REG32(LCD_DAH) |
| 2070 | #define REG_LCD_DAV REG32(LCD_DAV) |
| 2071 | #define REG_LCD_PS REG32(LCD_PS) |
| 2072 | #define REG_LCD_CLS REG32(LCD_CLS) |
| 2073 | #define REG_LCD_SPL REG32(LCD_SPL) |
| 2074 | #define REG_LCD_REV REG32(LCD_REV) |
| 2075 | #define REG_LCD_CTRL REG32(LCD_CTRL) |
| 2076 | #define REG_LCD_STATE REG32(LCD_STATE) |
| 2077 | #define REG_LCD_IID REG32(LCD_IID) |
| 2078 | #define REG_LCD_DA0 REG32(LCD_DA0) |
| 2079 | #define REG_LCD_SA0 REG32(LCD_SA0) |
| 2080 | #define REG_LCD_FID0 REG32(LCD_FID0) |
| 2081 | #define REG_LCD_CMD0 REG32(LCD_CMD0) |
| 2082 | #define REG_LCD_DA1 REG32(LCD_DA1) |
| 2083 | #define REG_LCD_SA1 REG32(LCD_SA1) |
| 2084 | #define REG_LCD_FID1 REG32(LCD_FID1) |
| 2085 | #define REG_LCD_CMD1 REG32(LCD_CMD1) |
| 2086 | |
| 2087 | #define LCD_CFG_PDW_BIT 4 |
| 2088 | #define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT) |
| 2089 | #define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT) |
| 2090 | #define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT) |
| 2091 | #define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT) |
| 2092 | #define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT) |
| 2093 | #define LCD_CFG_MODE_BIT 0 |
| 2094 | #define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT) |
| 2095 | #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT) |
| 2096 | #define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT) |
| 2097 | #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT) |
| 2098 | #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT) |
| 2099 | #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT) |
| 2100 | #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT) |
| 2101 | #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT) |
| 2102 | #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT) |
| 2103 | #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT) |
| 2104 | #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT) |
| 2105 | |
| 2106 | #define LCD_VSYNC_VPS_BIT 16 |
| 2107 | #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
| 2108 | #define LCD_VSYNC_VPE_BIT 0 |
| 2109 | #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) |
| 2110 | |
| 2111 | #define LCD_HSYNC_HPS_BIT 16 |
| 2112 | #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) |
| 2113 | #define LCD_HSYNC_HPE_BIT 0 |
| 2114 | #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) |
| 2115 | |
| 2116 | #define LCD_VAT_HT_BIT 16 |
| 2117 | #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) |
| 2118 | #define LCD_VAT_VT_BIT 0 |
| 2119 | #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) |
| 2120 | |
| 2121 | #define LCD_DAH_HDS_BIT 16 |
| 2122 | #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) |
| 2123 | #define LCD_DAH_HDE_BIT 0 |
| 2124 | #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) |
| 2125 | |
| 2126 | #define LCD_DAV_VDS_BIT 16 |
| 2127 | #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) |
| 2128 | #define LCD_DAV_VDE_BIT 0 |
| 2129 | #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) |
| 2130 | |
| 2131 | #define LCD_CTRL_BST_BIT 28 |
| 2132 | #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) |
| 2133 | #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) |
| 2134 | #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) |
| 2135 | #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) |
| 2136 | #define LCD_CTRL_RGB555 (1 << 27) |
| 2137 | #define LCD_CTRL_OFUP (1 << 26) |
| 2138 | #define LCD_CTRL_FRC_BIT 24 |
| 2139 | #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) |
| 2140 | #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) |
| 2141 | #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) |
| 2142 | #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) |
| 2143 | #define LCD_CTRL_PDD_BIT 16 |
| 2144 | #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) |
| 2145 | #define LCD_CTRL_EOFM (1 << 13) |
| 2146 | #define LCD_CTRL_SOFM (1 << 12) |
| 2147 | #define LCD_CTRL_OFUM (1 << 11) |
| 2148 | #define LCD_CTRL_IFUM0 (1 << 10) |
| 2149 | #define LCD_CTRL_IFUM1 (1 << 9) |
| 2150 | #define LCD_CTRL_LDDM (1 << 8) |
| 2151 | #define LCD_CTRL_QDM (1 << 7) |
| 2152 | #define LCD_CTRL_BEDN (1 << 6) |
| 2153 | #define LCD_CTRL_PEDN (1 << 5) |
| 2154 | #define LCD_CTRL_DIS (1 << 4) |
| 2155 | #define LCD_CTRL_ENA (1 << 3) |
| 2156 | #define LCD_CTRL_BPP_BIT 0 |
| 2157 | #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) |
| 2158 | #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) |
| 2159 | #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) |
| 2160 | #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) |
| 2161 | #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) |
| 2162 | #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) |
| 2163 | |
| 2164 | #define LCD_STATE_QD (1 << 7) |
| 2165 | #define LCD_STATE_EOF (1 << 5) |
| 2166 | #define LCD_STATE_SOF (1 << 4) |
| 2167 | #define LCD_STATE_OFU (1 << 3) |
| 2168 | #define LCD_STATE_IFU0 (1 << 2) |
| 2169 | #define LCD_STATE_IFU1 (1 << 1) |
| 2170 | #define LCD_STATE_LDD (1 << 0) |
| 2171 | |
| 2172 | #define LCD_CMD_SOFINT (1 << 31) |
| 2173 | #define LCD_CMD_EOFINT (1 << 30) |
| 2174 | #define LCD_CMD_PAL (1 << 28) |
| 2175 | #define LCD_CMD_LEN_BIT 0 |
| 2176 | #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) |
| 2177 | |
| 2178 | |
| 2179 | |
| 2180 | |
| 2181 | /************************************************************************* |
| 2182 | * DES |
| 2183 | *************************************************************************/ |
| 2184 | #define DES_CR1 (DES_BASE + 0x000) |
| 2185 | #define DES_CR2 (DES_BASE + 0x004) |
| 2186 | #define DES_SR (DES_BASE + 0x008) |
| 2187 | #define DES_K1L (DES_BASE + 0x010) |
| 2188 | #define DES_K1R (DES_BASE + 0x014) |
| 2189 | #define DES_K2L (DES_BASE + 0x018) |
| 2190 | #define DES_K2R (DES_BASE + 0x01C) |
| 2191 | #define DES_K3L (DES_BASE + 0x020) |
| 2192 | #define DES_K3R (DES_BASE + 0x024) |
| 2193 | #define DES_IVL (DES_BASE + 0x028) |
| 2194 | #define DES_IVR (DES_BASE + 0x02C) |
| 2195 | #define DES_DIN (DES_BASE + 0x030) |
| 2196 | #define DES_DOUT (DES_BASE + 0x034) |
| 2197 | |
| 2198 | #define REG_DES_CR1 REG32(DES_CR1) |
| 2199 | #define REG_DES_CR2 REG32(DES_CR2) |
| 2200 | #define REG_DES_SR REG32(DES_SR) |
| 2201 | #define REG_DES_K1L REG32(DES_K1L) |
| 2202 | #define REG_DES_K1R REG32(DES_K1R) |
| 2203 | #define REG_DES_K2L REG32(DES_K2L) |
| 2204 | #define REG_DES_K2R REG32(DES_K2R) |
| 2205 | #define REG_DES_K3L REG32(DES_K3L) |
| 2206 | #define REG_DES_K3R REG32(DES_K3R) |
| 2207 | #define REG_DES_IVL REG32(DES_IVL) |
| 2208 | #define REG_DES_IVR REG32(DES_IVR) |
| 2209 | #define REG_DES_DIN REG32(DES_DIN) |
| 2210 | #define REG_DES_DOUT REG32(DES_DOUT) |
| 2211 | |
| 2212 | /* DES Control Register 1 (DES_CR1) */ |
| 2213 | |
| 2214 | #define DES_CR1_EN (1 << 0) |
| 2215 | |
| 2216 | /* DES Control Register 2 (DES_CR2) */ |
| 2217 | |
| 2218 | #define DES_CR2_ENDEC (1 << 3) |
| 2219 | #define DES_CR2_MODE (1 << 2) |
| 2220 | #define DES_CR2_ALG (1 << 1) |
| 2221 | #define DES_CR2_DMAE (1 << 0) |
| 2222 | |
| 2223 | /* DES State Register (DES_SR) */ |
| 2224 | |
| 2225 | #define DES_SR_IN_FULL (1 << 5) |
| 2226 | #define DES_SR_IN_LHF (1 << 4) |
| 2227 | #define DES_SR_IN_EMPTY (1 << 3) |
| 2228 | #define DES_SR_OUT_FULL (1 << 2) |
| 2229 | #define DES_SR_OUT_GHF (1 << 1) |
| 2230 | #define DES_SR_OUT_EMPTY (1 << 0) |
| 2231 | |
| 2232 | |
| 2233 | |
| 2234 | |
| 2235 | /************************************************************************* |
| 2236 | * CPM |
| 2237 | *************************************************************************/ |
| 2238 | #define CPM_CFCR (CPM_BASE+0x00) |
| 2239 | #define CPM_PLCR1 (CPM_BASE+0x10) |
| 2240 | #define CPM_OCR (CPM_BASE+0x1c) |
| 2241 | #define CPM_CFCR2 (CPM_BASE+0x60) |
| 2242 | #define CPM_LPCR (CPM_BASE+0x04) |
| 2243 | #define CPM_RSTR (CPM_BASE+0x08) |
| 2244 | #define CPM_MSCR (CPM_BASE+0x20) |
| 2245 | #define CPM_SCR (CPM_BASE+0x24) |
| 2246 | #define CPM_WRER (CPM_BASE+0x28) |
| 2247 | #define CPM_WFER (CPM_BASE+0x2c) |
| 2248 | #define CPM_WER (CPM_BASE+0x30) |
| 2249 | #define CPM_WSR (CPM_BASE+0x34) |
| 2250 | #define CPM_GSR0 (CPM_BASE+0x38) |
| 2251 | #define CPM_GSR1 (CPM_BASE+0x3c) |
| 2252 | #define CPM_GSR2 (CPM_BASE+0x40) |
| 2253 | #define CPM_SPR (CPM_BASE+0x44) |
| 2254 | #define CPM_GSR3 (CPM_BASE+0x48) |
| 2255 | |
| 2256 | #define REG_CPM_CFCR REG32(CPM_CFCR) |
| 2257 | #define REG_CPM_PLCR1 REG32(CPM_PLCR1) |
| 2258 | #define REG_CPM_OCR REG32(CPM_OCR) |
| 2259 | #define REG_CPM_CFCR2 REG32(CPM_CFCR2) |
| 2260 | #define REG_CPM_LPCR REG32(CPM_LPCR) |
| 2261 | #define REG_CPM_RSTR REG32(CPM_RSTR) |
| 2262 | #define REG_CPM_MSCR REG32(CPM_MSCR) |
| 2263 | #define REG_CPM_SCR REG32(CPM_SCR) |
| 2264 | #define REG_CPM_WRER REG32(CPM_WRER) |
| 2265 | #define REG_CPM_WFER REG32(CPM_WFER) |
| 2266 | #define REG_CPM_WER REG32(CPM_WER) |
| 2267 | #define REG_CPM_WSR REG32(CPM_WSR) |
| 2268 | #define REG_CPM_GSR0 REG32(CPM_GSR0) |
| 2269 | #define REG_CPM_GSR1 REG32(CPM_GSR1) |
| 2270 | #define REG_CPM_GSR2 REG32(CPM_GSR2) |
| 2271 | #define REG_CPM_SPR REG32(CPM_SPR) |
| 2272 | #define REG_CPM_GSR3 REG32(CPM_GSR3) |
| 2273 | |
| 2274 | #define CPM_CFCR_SSI (1 << 31) |
| 2275 | #define CPM_CFCR_LCD (1 << 30) |
| 2276 | #define CPM_CFCR_I2S (1 << 29) |
| 2277 | #define CPM_CFCR_UCS (1 << 28) |
| 2278 | #define CPM_CFCR_UFR_BIT 25 |
| 2279 | #define CPM_CFCR_UFR_MASK (0x07 << CPM_CFCR_UFR_BIT) |
| 2280 | #define CPM_CFCR_MSC (1 << 24) |
| 2281 | #define CPM_CFCR_CKOEN2 (1 << 23) |
| 2282 | #define CPM_CFCR_CKOEN1 (1 << 22) |
| 2283 | #define CPM_CFCR_UPE (1 << 20) |
| 2284 | #define CPM_CFCR_MFR_BIT 16 |
| 2285 | #define CPM_CFCR_MFR_MASK (0x0f << CPM_CFCR_MFR_BIT) |
| 2286 | #define CFCR_MDIV_1 (0 << CPM_CFCR_MFR_BIT) |
| 2287 | #define CFCR_MDIV_2 (1 << CPM_CFCR_MFR_BIT) |
| 2288 | #define CFCR_MDIV_3 (2 << CPM_CFCR_MFR_BIT) |
| 2289 | #define CFCR_MDIV_4 (3 << CPM_CFCR_MFR_BIT) |
| 2290 | #define CFCR_MDIV_6 (4 << CPM_CFCR_MFR_BIT) |
| 2291 | #define CFCR_MDIV_8 (5 << CPM_CFCR_MFR_BIT) |
| 2292 | #define CFCR_MDIV_12 (6 << CPM_CFCR_MFR_BIT) |
| 2293 | #define CFCR_MDIV_16 (7 << CPM_CFCR_MFR_BIT) |
| 2294 | #define CFCR_MDIV_24 (8 << CPM_CFCR_MFR_BIT) |
| 2295 | #define CFCR_MDIV_32 (9 << CPM_CFCR_MFR_BIT) |
| 2296 | #define CPM_CFCR_LFR_BIT 12 |
| 2297 | #define CPM_CFCR_LFR_MASK (0x0f << CPM_CFCR_LFR_BIT) |
| 2298 | #define CPM_CFCR_PFR_BIT 8 |
| 2299 | #define CPM_CFCR_PFR_MASK (0x0f << CPM_CFCR_PFR_BIT) |
| 2300 | #define CFCR_PDIV_1 (0 << CPM_CFCR_PFR_BIT) |
| 2301 | #define CFCR_PDIV_2 (1 << CPM_CFCR_PFR_BIT) |
| 2302 | #define CFCR_PDIV_3 (2 << CPM_CFCR_PFR_BIT) |
| 2303 | #define CFCR_PDIV_4 (3 << CPM_CFCR_PFR_BIT) |
| 2304 | #define CFCR_PDIV_6 (4 << CPM_CFCR_PFR_BIT) |
| 2305 | #define CFCR_PDIV_8 (5 << CPM_CFCR_PFR_BIT) |
| 2306 | #define CFCR_PDIV_12 (6 << CPM_CFCR_PFR_BIT) |
| 2307 | #define CFCR_PDIV_16 (7 << CPM_CFCR_PFR_BIT) |
| 2308 | #define CFCR_PDIV_24 (8 << CPM_CFCR_PFR_BIT) |
| 2309 | #define CFCR_PDIV_32 (9 << CPM_CFCR_PFR_BIT) |
| 2310 | #define CPM_CFCR_SFR_BIT 4 |
| 2311 | #define CPM_CFCR_SFR_MASK (0x0f << CPM_CFCR_SFR_BIT) |
| 2312 | #define CFCR_SDIV_1 (0 << CPM_CFCR_SFR_BIT) |
| 2313 | #define CFCR_SDIV_2 (1 << CPM_CFCR_SFR_BIT) |
| 2314 | #define CFCR_SDIV_3 (2 << CPM_CFCR_SFR_BIT) |
| 2315 | #define CFCR_SDIV_4 (3 << CPM_CFCR_SFR_BIT) |
| 2316 | #define CFCR_SDIV_6 (4 << CPM_CFCR_SFR_BIT) |
| 2317 | #define CFCR_SDIV_8 (5 << CPM_CFCR_SFR_BIT) |
| 2318 | #define CFCR_SDIV_12 (6 << CPM_CFCR_SFR_BIT) |
| 2319 | #define CFCR_SDIV_16 (7 << CPM_CFCR_SFR_BIT) |
| 2320 | #define CFCR_SDIV_24 (8 << CPM_CFCR_SFR_BIT) |
| 2321 | #define CFCR_SDIV_32 (9 << CPM_CFCR_SFR_BIT) |
| 2322 | #define CPM_CFCR_IFR_BIT 0 |
| 2323 | #define CPM_CFCR_IFR_MASK (0x0f << CPM_CFCR_IFR_BIT) |
| 2324 | #define CFCR_IDIV_1 (0 << CPM_CFCR_IFR_BIT) |
| 2325 | #define CFCR_IDIV_2 (1 << CPM_CFCR_IFR_BIT) |
| 2326 | #define CFCR_IDIV_3 (2 << CPM_CFCR_IFR_BIT) |
| 2327 | #define CFCR_IDIV_4 (3 << CPM_CFCR_IFR_BIT) |
| 2328 | #define CFCR_IDIV_6 (4 << CPM_CFCR_IFR_BIT) |
| 2329 | #define CFCR_IDIV_8 (5 << CPM_CFCR_IFR_BIT) |
| 2330 | #define CFCR_IDIV_12 (6 << CPM_CFCR_IFR_BIT) |
| 2331 | #define CFCR_IDIV_16 (7 << CPM_CFCR_IFR_BIT) |
| 2332 | #define CFCR_IDIV_24 (8 << CPM_CFCR_IFR_BIT) |
| 2333 | #define CFCR_IDIV_32 (9 << CPM_CFCR_IFR_BIT) |
| 2334 | |
| 2335 | #define CPM_PLCR1_PLL1FD_BIT 23 |
| 2336 | #define CPM_PLCR1_PLL1FD_MASK (0x1ff << CPM_PLCR1_PLL1FD_BIT) |
| 2337 | #define CPM_PLCR1_PLL1RD_BIT 18 |
| 2338 | #define CPM_PLCR1_PLL1RD_MASK (0x1f << CPM_PLCR1_PLL1RD_BIT) |
| 2339 | #define CPM_PLCR1_PLL1OD_BIT 16 |
| 2340 | #define CPM_PLCR1_PLL1OD_MASK (0x03 << CPM_PLCR1_PLL1OD_BIT) |
| 2341 | #define CPM_PLCR1_PLL1S (1 << 10) |
| 2342 | #define CPM_PLCR1_PLL1BP (1 << 9) |
| 2343 | #define CPM_PLCR1_PLL1EN (1 << 8) |
| 2344 | #define CPM_PLCR1_PLL1ST_BIT 0 |
| 2345 | #define CPM_PLCR1_PLL1ST_MASK (0xff << CPM_PLCR1_PLL1ST_BIT) |
| 2346 | |
| 2347 | #define CPM_OCR_O1ST_BIT 16 |
| 2348 | #define CPM_OCR_O1ST_MASK (0xff << CPM_OCR_O1ST_BIT) |
| 2349 | #define CPM_OCR_O2SE_BIT 8 |
| 2350 | #define CPM_OCR_O2SE (1 << CPM_OCR_O2SE_BIT) |
| 2351 | #define CPM_OCR_SUSPEND1_BIT 7 |
| 2352 | #define CPM_OCR_SUSPEND1 (1 << CPM_OCR_SUSPEND1_BIT) |
| 2353 | #define CPM_OCR_SUSPEND0_BIT 6 |
| 2354 | #define CPM_OCR_SUSPEND0 (1 << CPM_OCR_SUSPEND0_BIT) |
| 2355 | |
| 2356 | #define CPM_CFCR2_PXFR_BIT 0 |
| 2357 | #define CPM_CFCR2_PXFR_MASK (0x1ff << CPM_CFCR2_PXFR_BIT) |
| 2358 | |
| 2359 | #define CPM_LPCR_DUTY_BIT 3 |
| 2360 | #define CPM_LPCR_DUTY_MASK (0x1f << CPM_LPCR_DUTY_BIT) |
| 2361 | #define CPM_LPCR_DOZE (1 << 2) |
| 2362 | #define CPM_LPCR_LPM_BIT 0 |
| 2363 | #define CPM_LPCR_LPM_MASK (0x03 << CPM_LPCR_LPM_BIT) |
| 2364 | #define CPM_LPCR_LPM_IDLE (0 << CPM_LPCR_LPM_BIT) |
| 2365 | #define CPM_LPCR_LPM_SLEEP (1 << CPM_LPCR_LPM_BIT) |
| 2366 | #define CPM_LPCR_LPM_HIBERNATE (2 << CPM_LPCR_LPM_BIT) |
| 2367 | |
| 2368 | #define CPM_RSTR_SR (1 << 2) |
| 2369 | #define CPM_RSTR_WR (1 << 1) |
| 2370 | #define CPM_RSTR_HR (1 << 0) |
| 2371 | |
| 2372 | #define CPM_MSCR_MSTP_BIT 0 |
| 2373 | #define CPM_MSCR_MSTP_MASK (0x1ffffff << CPM_MSCR_MSTP_BIT) |
| 2374 | #define CPM_MSCR_MSTP_UART0 0 |
| 2375 | #define CPM_MSCR_MSTP_UART1 1 |
| 2376 | #define CPM_MSCR_MSTP_UART2 2 |
| 2377 | #define CPM_MSCR_MSTP_OST 3 |
| 2378 | #define CPM_MSCR_MSTP_RTC 4 |
| 2379 | #define CPM_MSCR_MSTP_DMAC 5 |
| 2380 | #define CPM_MSCR_MSTP_UHC 6 |
| 2381 | #define CPM_MSCR_MSTP_LCD 7 |
| 2382 | #define CPM_MSCR_MSTP_I2C 8 |
| 2383 | #define CPM_MSCR_MSTP_AIC1 9 |
| 2384 | #define CPM_MSCR_MSTP_PWM0 10 |
| 2385 | #define CPM_MSCR_MSTP_PWM1 11 |
| 2386 | #define CPM_MSCR_MSTP_SSI 12 |
| 2387 | #define CPM_MSCR_MSTP_MSC 13 |
| 2388 | #define CPM_MSCR_MSTP_SCC 14 |
| 2389 | #define CPM_MSCR_MSTP_FIR 16 |
| 2390 | #define CPM_MSCR_MSTP_AIC2 18 |
| 2391 | #define CPM_MSCR_MSTP_DES 19 |
| 2392 | #define CPM_MSCR_MSTP_UART3 20 |
| 2393 | #define CPM_MSCR_MSTP_ETH 21 |
| 2394 | #define CPM_MSCR_MSTP_PS2 22 |
| 2395 | #define CPM_MSCR_MSTP_CIM 23 |
| 2396 | #define CPM_MSCR_MSTP_UDC 24 |
| 2397 | |
| 2398 | #define CPM_SCR_O1SE (1 << 4) |
| 2399 | #define CPM_SCR_HGP (1 << 3) |
| 2400 | #define CPM_SCR_HZP (1 << 2) |
| 2401 | #define CPM_SCR_HZM (1 << 1) |
| 2402 | |
| 2403 | #define CPM_WRER_RE_BIT 0 |
| 2404 | #define CPM_WRER_RE_MASK (0xffff << CPM_WRER_RE_BIT) |
| 2405 | |
| 2406 | #define CPM_WFER_FE_BIT 0 |
| 2407 | #define CPM_WFER_FE_MASK (0xffff << CPM_WFER_FE_BIT) |
| 2408 | |
| 2409 | #define CPM_WER_WERTC (1 << 31) |
| 2410 | #define CPM_WER_WEETH (1 << 30) |
| 2411 | #define CPM_WER_WE_BIT 0 |
| 2412 | #define CPM_WER_WE_MASK (0xffff << CPM_WER_WE_BIT) |
| 2413 | |
| 2414 | #define CPM_WSR_WSRTC (1 << 31) |
| 2415 | #define CPM_WSR_WSETH (1 << 30) |
| 2416 | #define CPM_WSR_WS_BIT 0 |
| 2417 | #define CPM_WSR_WS_MASK (0xffff << CPM_WSR_WS_BIT) |
| 2418 | |
| 2419 | |
| 2420 | |
| 2421 | |
| 2422 | /************************************************************************* |
| 2423 | * SSI |
| 2424 | *************************************************************************/ |
| 2425 | #define SSI_DR (SSI_BASE + 0x000) |
| 2426 | #define SSI_CR0 (SSI_BASE + 0x004) |
| 2427 | #define SSI_CR1 (SSI_BASE + 0x008) |
| 2428 | #define SSI_SR (SSI_BASE + 0x00C) |
| 2429 | #define SSI_ITR (SSI_BASE + 0x010) |
| 2430 | #define SSI_ICR (SSI_BASE + 0x014) |
| 2431 | #define SSI_GR (SSI_BASE + 0x018) |
| 2432 | |
| 2433 | #define REG_SSI_DR REG32(SSI_DR) |
| 2434 | #define REG_SSI_CR0 REG16(SSI_CR0) |
| 2435 | #define REG_SSI_CR1 REG32(SSI_CR1) |
| 2436 | #define REG_SSI_SR REG32(SSI_SR) |
| 2437 | #define REG_SSI_ITR REG16(SSI_ITR) |
| 2438 | #define REG_SSI_ICR REG8(SSI_ICR) |
| 2439 | #define REG_SSI_GR REG16(SSI_GR) |
| 2440 | |
| 2441 | /* SSI Data Register (SSI_DR) */ |
| 2442 | |
| 2443 | #define SSI_DR_GPC_BIT 0 |
| 2444 | #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) |
| 2445 | |
| 2446 | /* SSI Control Register 0 (SSI_CR0) */ |
| 2447 | |
| 2448 | #define SSI_CR0_SSIE (1 << 15) |
| 2449 | #define SSI_CR0_TIE (1 << 14) |
| 2450 | #define SSI_CR0_RIE (1 << 13) |
| 2451 | #define SSI_CR0_TEIE (1 << 12) |
| 2452 | #define SSI_CR0_REIE (1 << 11) |
| 2453 | #define SSI_CR0_LOOP (1 << 10) |
| 2454 | #define SSI_CR0_RFINE (1 << 9) |
| 2455 | #define SSI_CR0_RFINC (1 << 8) |
| 2456 | #define SSI_CR0_FSEL (1 << 6) |
| 2457 | #define SSI_CR0_TFLUSH (1 << 2) |
| 2458 | #define SSI_CR0_RFLUSH (1 << 1) |
| 2459 | #define SSI_CR0_DISREV (1 << 0) |
| 2460 | |
| 2461 | /* SSI Control Register 1 (SSI_CR1) */ |
| 2462 | |
| 2463 | #define SSI_CR1_FRMHL_BIT 30 |
| 2464 | #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) |
| 2465 | #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ |
| 2466 | #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ |
| 2467 | #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ |
| 2468 | #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ |
| 2469 | #define SSI_CR1_TFVCK_BIT 28 |
| 2470 | #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) |
| 2471 | #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) |
| 2472 | #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) |
| 2473 | #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) |
| 2474 | #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) |
| 2475 | #define SSI_CR1_TCKFI_BIT 26 |
| 2476 | #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) |
| 2477 | #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) |
| 2478 | #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) |
| 2479 | #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) |
| 2480 | #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) |
| 2481 | #define SSI_CR1_LFST (1 << 25) |
| 2482 | #define SSI_CR1_ITFRM (1 << 24) |
| 2483 | #define SSI_CR1_UNFIN (1 << 23) |
| 2484 | #define SSI_CR1_MULTS (1 << 22) |
| 2485 | #define SSI_CR1_FMAT_BIT 20 |
| 2486 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) |
| 2487 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ |
| 2488 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ |
| 2489 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ |
| 2490 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ |
| 2491 | #define SSI_CR1_MCOM_BIT 12 |
| 2492 | #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) |
| 2493 | #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ |
| 2494 | #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ |
| 2495 | #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ |
| 2496 | #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ |
| 2497 | #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ |
| 2498 | #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ |
| 2499 | #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ |
| 2500 | #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ |
| 2501 | #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ |
| 2502 | #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ |
| 2503 | #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ |
| 2504 | #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ |
| 2505 | #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ |
| 2506 | #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ |
| 2507 | #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ |
| 2508 | #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ |
| 2509 | #define SSI_CR1_TTRG_BIT 10 |
| 2510 | #define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT) |
| 2511 | #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */ |
| 2512 | #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */ |
| 2513 | #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */ |
| 2514 | #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */ |
| 2515 | #define SSI_CR1_RTRG_BIT 8 |
| 2516 | #define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT) |
| 2517 | #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */ |
| 2518 | #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */ |
| 2519 | #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */ |
| 2520 | #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */ |
| 2521 | #define SSI_CR1_FLEN_BIT 4 |
| 2522 | #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) |
| 2523 | #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) |
| 2524 | #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) |
| 2525 | #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) |
| 2526 | #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) |
| 2527 | #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) |
| 2528 | #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) |
| 2529 | #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) |
| 2530 | #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) |
| 2531 | #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) |
| 2532 | #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) |
| 2533 | #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) |
| 2534 | #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) |
| 2535 | #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) |
| 2536 | #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) |
| 2537 | #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) |
| 2538 | #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) |
| 2539 | #define SSI_CR1_PHA (1 << 1) |
| 2540 | #define SSI_CR1_POL (1 << 0) |
| 2541 | |
| 2542 | /* SSI Status Register (SSI_SR) */ |
| 2543 | |
| 2544 | #define SSI_SR_TFIFONUM_BIT 13 |
| 2545 | #define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT) |
| 2546 | #define SSI_SR_RFIFONUM_BIT 8 |
| 2547 | #define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT) |
| 2548 | #define SSI_SR_END (1 << 7) |
| 2549 | #define SSI_SR_BUSY (1 << 6) |
| 2550 | #define SSI_SR_TFF (1 << 5) |
| 2551 | #define SSI_SR_RFE (1 << 4) |
| 2552 | #define SSI_SR_TFHE (1 << 3) |
| 2553 | #define SSI_SR_RFHF (1 << 2) |
| 2554 | #define SSI_SR_UNDR (1 << 1) |
| 2555 | #define SSI_SR_OVER (1 << 0) |
| 2556 | |
| 2557 | /* SSI Interval Time Control Register (SSI_ITR) */ |
| 2558 | |
| 2559 | #define SSI_ITR_CNTCLK (1 << 15) |
| 2560 | #define SSI_ITR_IVLTM_BIT 0 |
| 2561 | #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) |
| 2562 | |
| 2563 | #ifndef __ASSEMBLY__ |
| 2564 | |
| 2565 | /*************************************************************************** |
| 2566 | * MSC |
| 2567 | ***************************************************************************/ |
| 2568 | |
| 2569 | #define __msc_start_op() \ |
| 2570 | ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) |
| 2571 | |
| 2572 | #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) |
| 2573 | #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) |
| 2574 | #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) |
| 2575 | #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) |
| 2576 | #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) |
| 2577 | #define __msc_get_nob() ( REG_MSC_NOB ) |
| 2578 | #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) |
| 2579 | #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) |
| 2580 | #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) |
| 2581 | #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) |
| 2582 | |
| 2583 | #define __msc_set_cmdat_bus_width1() \ |
| 2584 | do { \ |
| 2585 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ |
| 2586 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ |
| 2587 | } while(0) |
| 2588 | |
| 2589 | #define __msc_set_cmdat_bus_width4() \ |
| 2590 | do { \ |
| 2591 | REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ |
| 2592 | REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ |
| 2593 | } while(0) |
| 2594 | |
| 2595 | #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) |
| 2596 | #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) |
| 2597 | #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) |
| 2598 | #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) |
| 2599 | #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) |
| 2600 | #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) |
| 2601 | #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) |
| 2602 | #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) |
| 2603 | |
| 2604 | /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ |
| 2605 | #define __msc_set_cmdat_res_format(r) \ |
| 2606 | do { \ |
| 2607 | REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ |
| 2608 | REG_MSC_CMDAT |= (r); \ |
| 2609 | } while(0) |
| 2610 | |
| 2611 | #define __msc_clear_cmdat() \ |
| 2612 | REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ |
| 2613 | MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ |
| 2614 | MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) |
| 2615 | |
| 2616 | #define __msc_get_imask() ( REG_MSC_IMASK ) |
| 2617 | #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) |
| 2618 | #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) |
| 2619 | #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) |
| 2620 | #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) |
| 2621 | #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) |
| 2622 | #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) |
| 2623 | #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) |
| 2624 | #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) |
| 2625 | #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) |
| 2626 | #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) |
| 2627 | #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) |
| 2628 | #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) |
| 2629 | |
| 2630 | /* n=1,2,4,8,16,32,64,128 */ |
| 2631 | #define __msc_set_clkrt_div(n) \ |
| 2632 | do { \ |
| 2633 | REG_MSC_CLKRT &= ~MSC_CLKRT_CLK_RATE_MASK; \ |
| 2634 | REG_MSC_CLKRT |= MSC_CLKRT_CLK_RATE_DIV_##n; \ |
| 2635 | } while(0) |
| 2636 | |
| 2637 | #define __msc_get_ireg() ( REG_MSC_IREG ) |
| 2638 | #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) |
| 2639 | #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) |
| 2640 | #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) |
| 2641 | #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) |
| 2642 | #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) |
| 2643 | #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) |
| 2644 | #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) |
| 2645 | #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) |
| 2646 | |
| 2647 | #define __msc_get_stat() ( REG_MSC_STAT ) |
| 2648 | #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) |
| 2649 | #define __msc_stat_crc_err() \ |
| 2650 | ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) |
| 2651 | #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) |
| 2652 | #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) |
| 2653 | #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) |
| 2654 | #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) |
| 2655 | #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) |
| 2656 | |
| 2657 | #define __msc_rd_resfifo() ( REG_MSC_RES ) |
| 2658 | #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) |
| 2659 | #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) |
| 2660 | |
| 2661 | #define __msc_reset() \ |
| 2662 | do { \ |
| 2663 | REG_MSC_STRPCL = MSC_STRPCL_RESET; \ |
| 2664 | while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ |
| 2665 | } while (0) |
| 2666 | |
| 2667 | #define __msc_start_clk() \ |
| 2668 | do { \ |
| 2669 | REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ |
| 2670 | REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_START; \ |
| 2671 | } while (0) |
| 2672 | |
| 2673 | #define __msc_stop_clk() \ |
| 2674 | do { \ |
| 2675 | REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ |
| 2676 | REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_STOP; \ |
| 2677 | } while (0) |
| 2678 | |
| 2679 | #define MMC_CLK 19169200 |
| 2680 | #define SD_CLK 24576000 |
| 2681 | |
| 2682 | /* msc_clk should little than pclk and little than clk retrieve from card */ |
| 2683 | #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ |
| 2684 | do { \ |
| 2685 | unsigned int rate, pclk, i; \ |
| 2686 | pclk = dev_clk; \ |
| 2687 | rate = type?SD_CLK:MMC_CLK; \ |
| 2688 | if (msc_clk && msc_clk < pclk) \ |
| 2689 | pclk = msc_clk; \ |
| 2690 | i = 0; \ |
| 2691 | while (pclk < rate) \ |
| 2692 | { \ |
| 2693 | i ++; \ |
| 2694 | rate >>= 1; \ |
| 2695 | } \ |
| 2696 | lv = i; \ |
| 2697 | } while(0) |
| 2698 | |
| 2699 | /* divide rate to little than or equal to 400kHz */ |
| 2700 | #define __msc_calc_slow_clk_divisor(type, lv) \ |
| 2701 | do { \ |
| 2702 | unsigned int rate, i; \ |
| 2703 | rate = (type?SD_CLK:MMC_CLK)/1000/400; \ |
| 2704 | i = 0; \ |
| 2705 | while (rate > 0) \ |
| 2706 | { \ |
| 2707 | rate >>= 1; \ |
| 2708 | i ++; \ |
| 2709 | } \ |
| 2710 | lv = i; \ |
| 2711 | } while(0) |
| 2712 | |
| 2713 | /*************************************************************************** |
| 2714 | * RTC |
| 2715 | ***************************************************************************/ |
| 2716 | |
| 2717 | #define __rtc_start() ( REG_RTC_RCR |= RTC_RCR_START ) |
| 2718 | #define __rtc_stop() ( REG_RTC_RCR &= ~RTC_RCR_START ) |
| 2719 | |
| 2720 | #define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE ) |
| 2721 | #define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE ) |
| 2722 | #define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE ) |
| 2723 | #define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE ) |
| 2724 | |
| 2725 | #define __rtc_enable_1hz_irq() ( REG_RTC_RCR |= RTC_RCR_HZIE ) |
| 2726 | #define __rtc_disable_1hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_HZIE ) |
| 2727 | |
| 2728 | #define __rtc_is_alarm_flag() ( REG_RTC_RCR & RTC_RCR_AF ) |
| 2729 | #define __rtc_is_1hz_flag() ( REG_RTC_RCR & RTC_RCR_HZ ) |
| 2730 | #define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF ) |
| 2731 | #define __rtc_clear_1hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_HZ ) |
| 2732 | |
| 2733 | #define __rtc_set_second(s) ( REG_RTC_RSR = (s) ) |
| 2734 | #define __rtc_get_second() REG_RTC_RSR |
| 2735 | #define __rtc_set_alarm(s) ( REG_RTC_RSAR = (s) ) |
| 2736 | #define __rtc_get_alarm() REG_RTC_RSAR |
| 2737 | |
| 2738 | #define __rtc_adjust_1hz(f32k) \ |
| 2739 | ( REG_RTC_RGR = (REG_RTC_RGR & ~(RTC_REG_DIV_MASK | RTC_RGR_ADJ_MASK)) | f32k | 0 ) |
| 2740 | #define __rtc_lock_1hz() ( REG_RTC_RGR |= RTC_RGR_LOCK ) |
| 2741 | |
| 2742 | |
| 2743 | /*************************************************************************** |
| 2744 | * FIR |
| 2745 | ***************************************************************************/ |
| 2746 | |
| 2747 | /* enable/disable fir unit */ |
| 2748 | #define __fir_enable() ( REG_FIR_CR1 |= FIR_CR1_FIRUE ) |
| 2749 | #define __fir_disable() ( REG_FIR_CR1 &= ~FIR_CR1_FIRUE ) |
| 2750 | |
| 2751 | /* enable/disable address comparison */ |
| 2752 | #define __fir_enable_ac() ( REG_FIR_CR1 |= FIR_CR1_ACE ) |
| 2753 | #define __fir_disable_ac() ( REG_FIR_CR1 &= ~FIR_CR1_ACE ) |
| 2754 | |
| 2755 | /* select frame end mode as underrun or normal */ |
| 2756 | #define __fir_set_eous() ( REG_FIR_CR1 |= FIR_CR1_EOUS ) |
| 2757 | #define __fir_clear_eous() ( REG_FIR_CR1 &= ~FIR_CR1_EOUS ) |
| 2758 | |
| 2759 | /* enable/disable transmitter idle interrupt */ |
| 2760 | #define __fir_enable_tii() ( REG_FIR_CR1 |= FIR_CR1_TIIE ) |
| 2761 | #define __fir_disable_tii() ( REG_FIR_CR1 &= ~FIR_CR1_TIIE ) |
| 2762 | |
| 2763 | /* enable/disable transmit FIFO service request interrupt */ |
| 2764 | #define __fir_enable_tfi() ( REG_FIR_CR1 |= FIR_CR1_TFIE ) |
| 2765 | #define __fir_disable_tfi() ( REG_FIR_CR1 &= ~FIR_CR1_TFIE ) |
| 2766 | |
| 2767 | /* enable/disable receive FIFO service request interrupt */ |
| 2768 | #define __fir_enable_rfi() ( REG_FIR_CR1 |= FIR_CR1_RFIE ) |
| 2769 | #define __fir_disable_rfi() ( REG_FIR_CR1 &= ~FIR_CR1_RFIE ) |
| 2770 | |
| 2771 | /* enable/disable tx function */ |
| 2772 | #define __fir_tx_enable() ( REG_FIR_CR1 |= FIR_CR1_TXE ) |
| 2773 | #define __fir_tx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_TXE ) |
| 2774 | |
| 2775 | /* enable/disable rx function */ |
| 2776 | #define __fir_rx_enable() ( REG_FIR_CR1 |= FIR_CR1_RXE ) |
| 2777 | #define __fir_rx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_RXE ) |
| 2778 | |
| 2779 | |
| 2780 | /* enable/disable serial infrared interaction pulse (SIP) */ |
| 2781 | #define __fir_enable_sip() ( REG_FIR_CR2 |= FIR_CR2_SIPE ) |
| 2782 | #define __fir_disable_sip() ( REG_FIR_CR2 &= ~FIR_CR2_SIPE ) |
| 2783 | |
| 2784 | /* un-inverted CRC value is sent out */ |
| 2785 | #define __fir_enable_bcrc() ( REG_FIR_CR2 |= FIR_CR2_BCRC ) |
| 2786 | |
| 2787 | /* inverted CRC value is sent out */ |
| 2788 | #define __fir_disable_bcrc() ( REG_FIR_CR2 &= ~FIR_CR2_BCRC ) |
| 2789 | |
| 2790 | /* enable/disable Transmit Frame Length Register */ |
| 2791 | #define __fir_enable_tflr() ( REG_FIR_CR2 |= FIR_CR2_TFLRS ) |
| 2792 | #define __fir_disable_tflr() ( REG_FIR_CR2 &= ~FIR_CR2_TFLRS ) |
| 2793 | |
| 2794 | /* Preamble is transmitted in idle state */ |
| 2795 | #define __fir_set_iss() ( REG_FIR_CR2 |= FIR_CR2_ISS ) |
| 2796 | |
| 2797 | /* Abort symbol is transmitted in idle state */ |
| 2798 | #define __fir_clear_iss() ( REG_FIR_CR2 &= ~FIR_CR2_ISS ) |
| 2799 | |
| 2800 | /* enable/disable loopback mode */ |
| 2801 | #define __fir_enable_loopback() ( REG_FIR_CR2 |= FIR_CR2_LMS ) |
| 2802 | #define __fir_disable_loopback() ( REG_FIR_CR2 &= ~FIR_CR2_LMS ) |
| 2803 | |
| 2804 | /* select transmit pin polarity */ |
| 2805 | #define __fir_tpp_negative() ( REG_FIR_CR2 |= FIR_CR2_TPPS ) |
| 2806 | #define __fir_tpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_TPPS ) |
| 2807 | |
| 2808 | /* select receive pin polarity */ |
| 2809 | #define __fir_rpp_negative() ( REG_FIR_CR2 |= FIR_CR2_RPPS ) |
| 2810 | #define __fir_rpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_RPPS ) |
| 2811 | |
| 2812 | /* n=16,32,64,128 */ |
| 2813 | #define __fir_set_txfifo_trigger(n) \ |
| 2814 | do { \ |
| 2815 | REG_FIR_CR2 &= ~FIR_CR2_TTRG_MASK; \ |
| 2816 | REG_FIR_CR2 |= FIR_CR2_TTRG_##n; \ |
| 2817 | } while (0) |
| 2818 | |
| 2819 | /* n=16,32,64,128 */ |
| 2820 | #define __fir_set_rxfifo_trigger(n) \ |
| 2821 | do { \ |
| 2822 | REG_FIR_CR2 &= ~FIR_CR2_RTRG_MASK; \ |
| 2823 | REG_FIR_CR2 |= FIR_CR2_RTRG_##n; \ |
| 2824 | } while (0) |
| 2825 | |
| 2826 | |
| 2827 | /* FIR status checking */ |
| 2828 | |
| 2829 | #define __fir_test_rfw() ( REG_FIR_SR & FIR_SR_RFW ) |
| 2830 | #define __fir_test_rfa() ( REG_FIR_SR & FIR_SR_RFA ) |
| 2831 | #define __fir_test_tfrtl() ( REG_FIR_SR & FIR_SR_TFRTL ) |
| 2832 | #define __fir_test_rfrtl() ( REG_FIR_SR & FIR_SR_RFRTL ) |
| 2833 | #define __fir_test_urun() ( REG_FIR_SR & FIR_SR_URUN ) |
| 2834 | #define __fir_test_rfte() ( REG_FIR_SR & FIR_SR_RFTE ) |
| 2835 | #define __fir_test_orun() ( REG_FIR_SR & FIR_SR_ORUN ) |
| 2836 | #define __fir_test_crce() ( REG_FIR_SR & FIR_SR_CRCE ) |
| 2837 | #define __fir_test_fend() ( REG_FIR_SR & FIR_SR_FEND ) |
| 2838 | #define __fir_test_tff() ( REG_FIR_SR & FIR_SR_TFF ) |
| 2839 | #define __fir_test_rfe() ( REG_FIR_SR & FIR_SR_RFE ) |
| 2840 | #define __fir_test_tidle() ( REG_FIR_SR & FIR_SR_TIDLE ) |
| 2841 | #define __fir_test_rb() ( REG_FIR_SR & FIR_SR_RB ) |
| 2842 | |
| 2843 | #define __fir_clear_status() \ |
| 2844 | do { \ |
| 2845 | REG_FIR_SR |= FIR_SR_RFW | FIR_SR_RFA | FIR_SR_URUN; \ |
| 2846 | } while (0) |
| 2847 | |
| 2848 | #define __fir_clear_rfw() ( REG_FIR_SR |= FIR_SR_RFW ) |
| 2849 | #define __fir_clear_rfa() ( REG_FIR_SR |= FIR_SR_RFA ) |
| 2850 | #define __fir_clear_urun() ( REG_FIR_SR |= FIR_SR_URUN ) |
| 2851 | |
| 2852 | #define __fir_set_tflr(len) \ |
| 2853 | do { \ |
| 2854 | REG_FIR_TFLR = len; \ |
| 2855 | } while (0) |
| 2856 | |
| 2857 | #define __fir_set_addr(a) ( REG_FIR_AR = (a) ) |
| 2858 | |
| 2859 | #define __fir_write_data(data) ( REG_FIR_TDR = data ) |
| 2860 | #define __fir_read_data(data) ( data = REG_FIR_RDR ) |
| 2861 | |
| 2862 | /*************************************************************************** |
| 2863 | * SCC |
| 2864 | ***************************************************************************/ |
| 2865 | |
| 2866 | #define __scc_enable(base) ( REG_SCC_CR(base) |= SCC_CR_SCCE ) |
| 2867 | #define __scc_disable(base) ( REG_SCC_CR(base) &= ~SCC_CR_SCCE ) |
| 2868 | |
| 2869 | #define __scc_set_tx_mode(base) ( REG_SCC_CR(base) |= SCC_CR_TRS ) |
| 2870 | #define __scc_set_rx_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_TRS ) |
| 2871 | |
| 2872 | #define __scc_enable_t2r(base) ( REG_SCC_CR(base) |= SCC_CR_T2R ) |
| 2873 | #define __scc_disable_t2r(base) ( REG_SCC_CR(base) &= ~SCC_CR_T2R ) |
| 2874 | |
| 2875 | #define __scc_clk_as_devclk(base) \ |
| 2876 | do { \ |
| 2877 | REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ |
| 2878 | REG_SCC_CR(base) |= SCC_CR_FDIV_1; \ |
| 2879 | } while (0) |
| 2880 | |
| 2881 | #define __scc_clk_as_half_devclk(base) \ |
| 2882 | do { \ |
| 2883 | REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ |
| 2884 | REG_SCC_CR(base) |= SCC_CR_FDIV_2; \ |
| 2885 | } while (0) |
| 2886 | |
| 2887 | /* n=1,4,8,14 */ |
| 2888 | #define __scc_set_fifo_trigger(base, n) \ |
| 2889 | do { \ |
| 2890 | REG_SCC_CR(base) &= ~SCC_CR_TRIG_MASK; \ |
| 2891 | REG_SCC_CR(base) |= SCC_CR_TRIG_##n; \ |
| 2892 | } while (0) |
| 2893 | |
| 2894 | #define __scc_set_protocol(base, p) \ |
| 2895 | do { \ |
| 2896 | if (p) \ |
| 2897 | REG_SCC_CR(base) |= SCC_CR_TP; \ |
| 2898 | else \ |
| 2899 | REG_SCC_CR(base) &= ~SCC_CR_TP; \ |
| 2900 | } while (0) |
| 2901 | |
| 2902 | #define __scc_flush_fifo(base) ( REG_SCC_CR(base) |= SCC_CR_FLUSH ) |
| 2903 | |
| 2904 | #define __scc_set_invert_mode(base) ( REG_SCC_CR(base) |= SCC_CR_CONV ) |
| 2905 | #define __scc_set_direct_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_CONV ) |
| 2906 | |
| 2907 | #define SCC_ERR_INTRS \ |
| 2908 | ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) |
| 2909 | #define SCC_ALL_INTRS \ |
| 2910 | ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \ |
| 2911 | SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) |
| 2912 | |
| 2913 | #define __scc_enable_err_intrs(base) ( REG_SCC_CR(base) |= SCC_ERR_INTRS ) |
| 2914 | #define __scc_disable_err_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ERR_INTRS ) |
| 2915 | |
| 2916 | #define SCC_ALL_ERRORS \ |
| 2917 | ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO) |
| 2918 | |
| 2919 | #define __scc_clear_errors(base) ( REG_SCC_SR(base) &= ~SCC_ALL_ERRORS ) |
| 2920 | |
| 2921 | #define __scc_enable_all_intrs(base) ( REG_SCC_CR(base) |= SCC_ALL_INTRS ) |
| 2922 | #define __scc_disable_all_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ALL_INTRS ) |
| 2923 | |
| 2924 | #define __scc_enable_tx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_TXIE | SCC_CR_TENDIE ) |
| 2925 | #define __scc_disable_tx_intr(base) ( REG_SCC_CR(base) &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) ) |
| 2926 | |
| 2927 | #define __scc_enable_rx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_RXIE) |
| 2928 | #define __scc_disable_rx_intr(base) ( REG_SCC_CR(base) &= ~SCC_CR_RXIE) |
| 2929 | |
| 2930 | #define __scc_set_tsend(base) ( REG_SCC_CR(base) |= SCC_CR_TSEND ) |
| 2931 | #define __scc_clear_tsend(base) ( REG_SCC_CR(base) &= ~SCC_CR_TSEND ) |
| 2932 | |
| 2933 | #define __scc_set_clockstop(base) ( REG_SCC_CR(base) |= SCC_CR_CLKSTP ) |
| 2934 | #define __scc_clear_clockstop(base) ( REG_SCC_CR(base) &= ~SCC_CR_CLKSTP ) |
| 2935 | |
| 2936 | #define __scc_clockstop_low(base) \ |
| 2937 | do { \ |
| 2938 | REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ |
| 2939 | REG_SCC_CR(base) |= SCC_CR_PX_STOP_LOW; \ |
| 2940 | } while (0) |
| 2941 | |
| 2942 | #define __scc_clockstop_high(base) \ |
| 2943 | do { \ |
| 2944 | REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ |
| 2945 | REG_SCC_CR(base) |= SCC_CR_PX_STOP_HIGH; \ |
| 2946 | } while (0) |
| 2947 | |
| 2948 | |
| 2949 | /* SCC status checking */ |
| 2950 | #define __scc_check_transfer_status(base) ( REG_SCC_SR(base) & SCC_SR_TRANS ) |
| 2951 | #define __scc_check_rx_overrun_error(base) ( REG_SCC_SR(base) & SCC_SR_ORER ) |
| 2952 | #define __scc_check_rx_timeout(base) ( REG_SCC_SR(base) & SCC_SR_RTO ) |
| 2953 | #define __scc_check_parity_error(base) ( REG_SCC_SR(base) & SCC_SR_PER ) |
| 2954 | #define __scc_check_txfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_TFTG ) |
| 2955 | #define __scc_check_rxfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_RFTG ) |
| 2956 | #define __scc_check_tx_end(base) ( REG_SCC_SR(base) & SCC_SR_TEND ) |
| 2957 | #define __scc_check_retx_3(base) ( REG_SCC_SR(base) & SCC_SR_RETR_3 ) |
| 2958 | #define __scc_check_ecnt_overflow(base) ( REG_SCC_SR(base) & SCC_SR_ECNTO ) |
| 2959 | |
| 2960 | |
| 2961 | /*************************************************************************** |
| 2962 | * WDT |
| 2963 | ***************************************************************************/ |
| 2964 | |
| 2965 | #define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) ) |
| 2966 | #define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START ) |
| 2967 | #define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START ) |
| 2968 | |
| 2969 | |
| 2970 | /*************************************************************************** |
| 2971 | * OST |
| 2972 | ***************************************************************************/ |
| 2973 | |
| 2974 | #define __ost_enable_all() ( REG_OST_TER |= 0x07 ) |
| 2975 | #define __ost_disable_all() ( REG_OST_TER &= ~0x07 ) |
| 2976 | #define __ost_enable_channel(n) ( REG_OST_TER |= (1 << (n)) ) |
| 2977 | #define __ost_disable_channel(n) ( REG_OST_TER &= ~(1 << (n)) ) |
| 2978 | #define __ost_set_reload(n, val) ( REG_OST_TRDR(n) = (val) ) |
| 2979 | #define __ost_set_count(n, val) ( REG_OST_TCNT(n) = (val) ) |
| 2980 | #define __ost_get_count(n) ( REG_OST_TCNT(n) ) |
| 2981 | #define __ost_set_clock(n, cs) ( REG_OST_TCSR(n) |= (cs) ) |
| 2982 | #define __ost_set_mode(n, val) ( REG_OST_TCSR(n) = (val) ) |
| 2983 | #define __ost_enable_interrupt(n) ( REG_OST_TCSR(n) |= OST_TCSR_UIE ) |
| 2984 | #define __ost_disable_interrupt(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UIE ) |
| 2985 | #define __ost_uf_detected(n) ( REG_OST_TCSR(n) & OST_TCSR_UF ) |
| 2986 | #define __ost_clear_uf(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UF ) |
| 2987 | #define __ost_is_busy(n) ( REG_OST_TCSR(n) & OST_TCSR_BUSY ) |
| 2988 | #define __ost_clear_busy(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_BUSY ) |
| 2989 | |
| 2990 | |
| 2991 | /*************************************************************************** |
| 2992 | * UART |
| 2993 | ***************************************************************************/ |
| 2994 | |
| 2995 | #define __uart_enable(n) \ |
| 2996 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = UARTFCR_UUE | UARTFCR_FE ) |
| 2997 | #define __uart_disable(n) \ |
| 2998 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE ) |
| 2999 | |
| 3000 | #define __uart_enable_transmit_irq(n) \ |
| 3001 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE ) |
| 3002 | #define __uart_disable_transmit_irq(n) \ |
| 3003 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE ) |
| 3004 | |
| 3005 | #define __uart_enable_receive_irq(n) \ |
| 3006 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) |
| 3007 | #define __uart_disable_receive_irq(n) \ |
| 3008 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) |
| 3009 | |
| 3010 | #define __uart_enable_loopback(n) \ |
| 3011 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP ) |
| 3012 | #define __uart_disable_loopback(n) \ |
| 3013 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP ) |
| 3014 | |
| 3015 | #define __uart_set_8n1(n) \ |
| 3016 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 ) |
| 3017 | |
| 3018 | #define __uart_set_baud(n, devclk, baud) \ |
| 3019 | do { \ |
| 3020 | REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \ |
| 3021 | REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \ |
| 3022 | REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ |
| 3023 | REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \ |
| 3024 | } while (0) |
| 3025 | |
| 3026 | #define __uart_parity_error(n) \ |
| 3027 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 ) |
| 3028 | |
| 3029 | #define __uart_clear_errors(n) \ |
| 3030 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTSR_RFER) ) |
| 3031 | |
| 3032 | #define __uart_transmit_fifo_empty(n) \ |
| 3033 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 ) |
| 3034 | |
| 3035 | #define __uart_transmit_end(n) \ |
| 3036 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 ) |
| 3037 | |
| 3038 | #define __uart_transmit_char(n, ch) \ |
| 3039 | REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch) |
| 3040 | |
| 3041 | #define __uart_receive_fifo_full(n) \ |
| 3042 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) |
| 3043 | |
| 3044 | #define __uart_receive_ready(n) \ |
| 3045 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) |
| 3046 | |
| 3047 | #define __uart_receive_char(n) \ |
| 3048 | REG8(UART_BASE + UART_OFF*(n) + OFF_RDR) |
| 3049 | |
| 3050 | #define __uart_disable_irda() \ |
| 3051 | ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) |
| 3052 | #define __uart_enable_irda() \ |
| 3053 | /* Tx high pulse as 0, Rx low pulse as 0 */ \ |
| 3054 | ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) |
| 3055 | |
| 3056 | |
| 3057 | /*************************************************************************** |
| 3058 | * INTC |
| 3059 | ***************************************************************************/ |
| 3060 | #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) |
| 3061 | #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) |
| 3062 | #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) |
| 3063 | |
| 3064 | /*************************************************************************** |
| 3065 | * CIM |
| 3066 | ***************************************************************************/ |
| 3067 | |
| 3068 | #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) |
| 3069 | #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) |
| 3070 | |
| 3071 | #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) |
| 3072 | #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) |
| 3073 | |
| 3074 | #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) |
| 3075 | #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) |
| 3076 | |
| 3077 | #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) |
| 3078 | #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) |
| 3079 | |
| 3080 | #define __cim_sample_data_at_pclk_falling_edge() \ |
| 3081 | ( REG_CIM_CFG |= CIM_CFG_PCP ) |
| 3082 | #define __cim_sample_data_at_pclk_rising_edge() \ |
| 3083 | ( REG_CIM_CFG &= ~CIM_CFG_PCP ) |
| 3084 | |
| 3085 | #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) |
| 3086 | #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) |
| 3087 | |
| 3088 | #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) |
| 3089 | #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) |
| 3090 | |
| 3091 | /* n=0-7 */ |
| 3092 | #define __cim_set_data_packing_mode(n) \ |
| 3093 | do { \ |
| 3094 | REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ |
| 3095 | REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ |
| 3096 | } while (0) |
| 3097 | |
| 3098 | #define __cim_enable_ccir656_progressive_mode() \ |
| 3099 | do { \ |
| 3100 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| 3101 | REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ |
| 3102 | } while (0) |
| 3103 | |
| 3104 | #define __cim_enable_ccir656_interlace_mode() \ |
| 3105 | do { \ |
| 3106 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| 3107 | REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ |
| 3108 | } while (0) |
| 3109 | |
| 3110 | #define __cim_enable_gated_clock_mode() \ |
| 3111 | do { \ |
| 3112 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| 3113 | REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ |
| 3114 | } while (0) |
| 3115 | |
| 3116 | #define __cim_enable_nongated_clock_mode() \ |
| 3117 | do { \ |
| 3118 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ |
| 3119 | REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ |
| 3120 | } while (0) |
| 3121 | |
| 3122 | /* sclk:system bus clock |
| 3123 | * mclk: CIM master clock |
| 3124 | */ |
| 3125 | #define __cim_set_master_clk(sclk, mclk) \ |
| 3126 | do { \ |
| 3127 | REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ |
| 3128 | REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ |
| 3129 | } while (0) |
| 3130 | |
| 3131 | #define __cim_enable_sof_intr() \ |
| 3132 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) |
| 3133 | #define __cim_disable_sof_intr() \ |
| 3134 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) |
| 3135 | |
| 3136 | #define __cim_enable_eof_intr() \ |
| 3137 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) |
| 3138 | #define __cim_disable_eof_intr() \ |
| 3139 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) |
| 3140 | |
| 3141 | #define __cim_enable_stop_intr() \ |
| 3142 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) |
| 3143 | #define __cim_disable_stop_intr() \ |
| 3144 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) |
| 3145 | |
| 3146 | #define __cim_enable_trig_intr() \ |
| 3147 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) |
| 3148 | #define __cim_disable_trig_intr() \ |
| 3149 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) |
| 3150 | |
| 3151 | #define __cim_enable_rxfifo_overflow_intr() \ |
| 3152 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) |
| 3153 | #define __cim_disable_rxfifo_overflow_intr() \ |
| 3154 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) |
| 3155 | |
| 3156 | /* n=1-16 */ |
| 3157 | #define __cim_set_frame_rate(n) \ |
| 3158 | do { \ |
| 3159 | REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ |
| 3160 | REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ |
| 3161 | } while (0) |
| 3162 | |
| 3163 | #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) |
| 3164 | #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) |
| 3165 | |
| 3166 | #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) |
| 3167 | #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) |
| 3168 | |
| 3169 | /* n=4,8,12,16,20,24,28,32 */ |
| 3170 | #define __cim_set_rxfifo_trigger(n) \ |
| 3171 | do { \ |
| 3172 | REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ |
| 3173 | REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ |
| 3174 | } while (0) |
| 3175 | |
| 3176 | #define __cim_clear_state() ( REG_CIM_STATE = 0 ) |
| 3177 | |
| 3178 | #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) |
| 3179 | #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) |
| 3180 | #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) |
| 3181 | #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) |
| 3182 | #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) |
| 3183 | #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) |
| 3184 | #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) |
| 3185 | #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) |
| 3186 | |
| 3187 | #define __cim_get_iid() ( REG_CIM_IID ) |
| 3188 | #define __cim_get_image_data() ( REG_CIM_RXFIFO ) |
| 3189 | #define __cim_get_dam_cmd() ( REG_CIM_CMD ) |
| 3190 | |
| 3191 | #define __cim_set_da(a) ( REG_CIM_DA = (a) ) |
| 3192 | |
| 3193 | /*************************************************************************** |
| 3194 | * PWM |
| 3195 | ***************************************************************************/ |
| 3196 | |
| 3197 | /* n is the pwm channel (0,1,..) */ |
| 3198 | #define __pwm_enable_module(n) ( REG_PWM_CTR(n) |= PWM_CTR_EN ) |
| 3199 | #define __pwm_disable_module(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_EN ) |
| 3200 | #define __pwm_graceful_shutdown_mode(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_SD ) |
| 3201 | #define __pwm_abrupt_shutdown_mode(n) ( REG_PWM_CTR(n) |= PWM_CTR_SD ) |
| 3202 | #define __pwm_set_full_duty(n) ( REG_PWM_DUT(n) |= PWM_DUT_FDUTY ) |
| 3203 | |
| 3204 | #define __pwm_set_prescale(n, p) \ |
| 3205 | ( REG_PWM_CTR(n) = ((REG_PWM_CTR(n) & ~PWM_CTR_PRESCALE_MASK) | (p) ) ) |
| 3206 | #define __pwm_set_period(n, p) \ |
| 3207 | ( REG_PWM_PER(n) = ( (REG_PWM_PER(n) & ~PWM_PER_PERIOD_MASK) | (p) ) ) |
| 3208 | #define __pwm_set_duty(n, d) \ |
| 3209 | ( REG_PWM_DUT(n) = ( (REG_PWM_DUT(n) & ~PWM_DUT_FDUTY) | (d) ) ) |
| 3210 | |
| 3211 | /*************************************************************************** |
| 3212 | * EMC |
| 3213 | ***************************************************************************/ |
| 3214 | |
| 3215 | #define __emc_enable_split() ( REG_EMC_BCR = EMC_BCR_BRE ) |
| 3216 | #define __emc_disable_split() ( REG_EMC_BCR = 0 ) |
| 3217 | |
| 3218 | #define __emc_smem_bus_width(n) /* 8, 16 or 32*/ \ |
| 3219 | ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BW_MASK) | \ |
| 3220 | EMC_SMCR_BW_##n##BIT ) |
| 3221 | #define __emc_smem_byte_control() \ |
| 3222 | ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_BCM ) |
| 3223 | #define __emc_normal_smem() \ |
| 3224 | ( REG_EMC_SMCR = (REG_EMC_SMCR & ~EMC_SMCR_SMT ) |
| 3225 | #define __emc_burst_smem() \ |
| 3226 | ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_SMT ) |
| 3227 | #define __emc_smem_burstlen(n) /* 4, 8, 16 or 32 */ \ |
| 3228 | ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BL_MASK) | (EMC_SMCR_BL_##n ) |
| 3229 | |
| 3230 | /*************************************************************************** |
| 3231 | * GPIO |
| 3232 | ***************************************************************************/ |
| 3233 | |
| 3234 | /* p is the port number (0,1,2,3) |
| 3235 | * o is the pin offset (0-31) inside the port |
| 3236 | * n is the absolute number of a pin (0-124), regardless of the port |
| 3237 | * m is the interrupt manner (low/high/falling/rising) |
| 3238 | */ |
| 3239 | |
| 3240 | #define __gpio_port_data(p) ( REG_GPIO_GPDR(p) ) |
| 3241 | |
| 3242 | #define __gpio_port_as_output(p, o) \ |
| 3243 | do { \ |
| 3244 | unsigned int tmp; \ |
| 3245 | REG_GPIO_GPIER(p) &= ~(1 << (o)); \ |
| 3246 | REG_GPIO_GPDIR(p) |= (1 << (o)); \ |
| 3247 | if (o < 16) { \ |
| 3248 | tmp = REG_GPIO_GPALR(p); \ |
| 3249 | tmp &= ~(3 << ((o) << 1)); \ |
| 3250 | REG_GPIO_GPALR(p) = tmp; \ |
| 3251 | } else { \ |
| 3252 | tmp = REG_GPIO_GPAUR(p); \ |
| 3253 | tmp &= ~(3 << (((o) - 16)<< 1)); \ |
| 3254 | REG_GPIO_GPAUR(p) = tmp; \ |
| 3255 | } \ |
| 3256 | } while (0) |
| 3257 | |
| 3258 | #define __gpio_port_as_input(p, o) \ |
| 3259 | do { \ |
| 3260 | unsigned int tmp; \ |
| 3261 | REG_GPIO_GPIER(p) &= ~(1 << (o)); \ |
| 3262 | REG_GPIO_GPDIR(p) &= ~(1 << (o)); \ |
| 3263 | if (o < 16) { \ |
| 3264 | tmp = REG_GPIO_GPALR(p); \ |
| 3265 | tmp &= ~(3 << ((o) << 1)); \ |
| 3266 | REG_GPIO_GPALR(p) = tmp; \ |
| 3267 | } else { \ |
| 3268 | tmp = REG_GPIO_GPAUR(p); \ |
| 3269 | tmp &= ~(3 << (((o) - 16)<< 1)); \ |
| 3270 | REG_GPIO_GPAUR(p) = tmp; \ |
| 3271 | } \ |
| 3272 | } while (0) |
| 3273 | |
| 3274 | #define __gpio_as_output(n) \ |
| 3275 | do { \ |
| 3276 | unsigned int p, o; \ |
| 3277 | p = (n) / 32; \ |
| 3278 | o = (n) % 32; \ |
| 3279 | __gpio_port_as_output(p, o); \ |
| 3280 | } while (0) |
| 3281 | |
| 3282 | #define __gpio_as_input(n) \ |
| 3283 | do { \ |
| 3284 | unsigned int p, o; \ |
| 3285 | p = (n) / 32; \ |
| 3286 | o = (n) % 32; \ |
| 3287 | __gpio_port_as_input(p, o); \ |
| 3288 | } while (0) |
| 3289 | |
| 3290 | #define __gpio_set_pin(n) \ |
| 3291 | do { \ |
| 3292 | unsigned int p, o; \ |
| 3293 | p = (n) / 32; \ |
| 3294 | o = (n) % 32; \ |
| 3295 | __gpio_port_data(p) |= (1 << o); \ |
| 3296 | } while (0) |
| 3297 | |
| 3298 | #define __gpio_clear_pin(n) \ |
| 3299 | do { \ |
| 3300 | unsigned int p, o; \ |
| 3301 | p = (n) / 32; \ |
| 3302 | o = (n) % 32; \ |
| 3303 | __gpio_port_data(p) &= ~(1 << o); \ |
| 3304 | } while (0) |
| 3305 | |
| 3306 | static __inline__ unsigned int __gpio_get_pin(unsigned int n) |
| 3307 | { |
| 3308 | unsigned int p, o; |
| 3309 | p = (n) / 32; |
| 3310 | o = (n) % 32; |
| 3311 | if (__gpio_port_data(p) & (1 << o)) |
| 3312 | return 1; |
| 3313 | else |
| 3314 | return 0; |
| 3315 | } |
| 3316 | |
| 3317 | |
| 3318 | #define __gpio_set_irq_detect_manner(p, o, m) \ |
| 3319 | do { \ |
| 3320 | unsigned int tmp; \ |
| 3321 | if (o < 16) { \ |
| 3322 | tmp = REG_GPIO_GPIDLR(p); \ |
| 3323 | tmp &= ~(3 << ((o) << 1)); \ |
| 3324 | tmp |= ((m) << ((o) << 1)); \ |
| 3325 | REG_GPIO_GPIDLR(p) = tmp; \ |
| 3326 | } else { \ |
| 3327 | o -= 16; \ |
| 3328 | tmp = REG_GPIO_GPIDUR(p); \ |
| 3329 | tmp &= ~(3 << ((o) << 1)); \ |
| 3330 | tmp |= ((m) << ((o) << 1)); \ |
| 3331 | REG_GPIO_GPIDUR(p) = tmp; \ |
| 3332 | } \ |
| 3333 | } while (0) |
| 3334 | |
| 3335 | #define __gpio_port_as_irq(p, o, m) \ |
| 3336 | do { \ |
| 3337 | __gpio_set_irq_detect_manner(p, o, m); \ |
| 3338 | __gpio_port_as_input(p, o); \ |
| 3339 | REG_GPIO_GPIER(p) |= (1 << o); \ |
| 3340 | } while (0) |
| 3341 | |
| 3342 | #define __gpio_as_irq(n, m) \ |
| 3343 | do { \ |
| 3344 | unsigned int p, o; \ |
| 3345 | p = (n) / 32; \ |
| 3346 | o = (n) % 32; \ |
| 3347 | __gpio_port_as_irq(p, o, m); \ |
| 3348 | } while (0) |
| 3349 | |
| 3350 | |
| 3351 | #define __gpio_as_irq_high_level(n) __gpio_as_irq(n, GPIO_IRQ_HILEVEL) |
| 3352 | #define __gpio_as_irq_low_level(n) __gpio_as_irq(n, GPIO_IRQ_LOLEVEL) |
| 3353 | #define __gpio_as_irq_fall_edge(n) __gpio_as_irq(n, GPIO_IRQ_FALLEDG) |
| 3354 | #define __gpio_as_irq_rise_edge(n) __gpio_as_irq(n, GPIO_IRQ_RAISEDG) |
| 3355 | |
| 3356 | |
| 3357 | #define __gpio_mask_irq(n) \ |
| 3358 | do { \ |
| 3359 | unsigned int p, o; \ |
| 3360 | p = (n) / 32; \ |
| 3361 | o = (n) % 32; \ |
| 3362 | REG_GPIO_GPIER(p) &= ~(1 << o); \ |
| 3363 | } while (0) |
| 3364 | |
| 3365 | #define __gpio_unmask_irq(n) \ |
| 3366 | do { \ |
| 3367 | unsigned int p, o; \ |
| 3368 | p = (n) / 32; \ |
| 3369 | o = (n) % 32; \ |
| 3370 | REG_GPIO_GPIER(n) |= (1 << o); \ |
| 3371 | } while (0) |
| 3372 | |
| 3373 | #define __gpio_ack_irq(n) \ |
| 3374 | do { \ |
| 3375 | unsigned int p, o; \ |
| 3376 | p = (n) / 32; \ |
| 3377 | o = (n) % 32; \ |
| 3378 | REG_GPIO_GPFR(p) |= (1 << o); \ |
| 3379 | } while (0) |
| 3380 | |
| 3381 | |
| 3382 | static __inline__ unsigned int __gpio_get_irq(void) |
| 3383 | { |
| 3384 | unsigned int tmp, i; |
| 3385 | |
| 3386 | tmp = REG_GPIO_GPFR(3); |
| 3387 | for (i=0; i<32; i++) |
| 3388 | if (tmp & (1 << i)) |
| 3389 | return 0x60 + i; |
| 3390 | tmp = REG_GPIO_GPFR(2); |
| 3391 | for (i=0; i<32; i++) |
| 3392 | if (tmp & (1 << i)) |
| 3393 | return 0x40 + i; |
| 3394 | tmp = REG_GPIO_GPFR(1); |
| 3395 | for (i=0; i<32; i++) |
| 3396 | if (tmp & (1 << i)) |
| 3397 | return 0x20 + i; |
| 3398 | tmp = REG_GPIO_GPFR(0); |
| 3399 | for (i=0; i<32; i++) |
| 3400 | if (tmp & (1 << i)) |
| 3401 | return i; |
| 3402 | return 0; |
| 3403 | } |
| 3404 | |
| 3405 | #define __gpio_group_irq(n) \ |
| 3406 | ({ \ |
| 3407 | register int tmp, i; \ |
| 3408 | tmp = REG_GPIO_GPFR((n)); \ |
| 3409 | for (i=31;i>=0;i--) \ |
| 3410 | if (tmp & (1 << i)) \ |
| 3411 | break; \ |
| 3412 | i; \ |
| 3413 | }) |
| 3414 | |
| 3415 | #define __gpio_enable_pullupdown(n) \ |
| 3416 | do { \ |
| 3417 | unsigned int p, o; \ |
| 3418 | p = (n) / 32; \ |
| 3419 | o = (n) % 32; \ |
| 3420 | REG_GPIO_GPPUR(p) |= (1 << o); \ |
| 3421 | } while (0) |
| 3422 | |
| 3423 | #define __gpio_disable_pullupdown(n) \ |
| 3424 | do { \ |
| 3425 | unsigned int p, o; \ |
| 3426 | p = (n) / 32; \ |
| 3427 | o = (n) % 32; \ |
| 3428 | REG_GPIO_GPPUR(p) &= ~(1 << o); \ |
| 3429 | } while (0) |
| 3430 | |
| 3431 | /* Init the alternate function pins */ |
| 3432 | |
| 3433 | |
| 3434 | #define __gpio_as_ssi() \ |
| 3435 | do { \ |
| 3436 | REG_GPIO_GPALR(2) &= 0xFC00FFFF; \ |
| 3437 | REG_GPIO_GPALR(2) |= 0x01550000; \ |
| 3438 | } while (0) |
| 3439 | |
| 3440 | #define __gpio_as_uart3() \ |
| 3441 | do { \ |
| 3442 | REG_GPIO_GPAUR(0) &= 0xFFFF0000; \ |
| 3443 | REG_GPIO_GPAUR(0) |= 0x00005555; \ |
| 3444 | } while (0) |
| 3445 | |
| 3446 | #define __gpio_as_uart2() \ |
| 3447 | do { \ |
| 3448 | REG_GPIO_GPALR(3) &= 0x3FFFFFFF; \ |
| 3449 | REG_GPIO_GPALR(3) |= 0x40000000; \ |
| 3450 | REG_GPIO_GPAUR(3) &= 0xF3FFFFFF; \ |
| 3451 | REG_GPIO_GPAUR(3) |= 0x04000000; \ |
| 3452 | } while (0) |
| 3453 | |
| 3454 | #define __gpio_as_uart1() \ |
| 3455 | do { \ |
| 3456 | REG_GPIO_GPAUR(0) &= 0xFFF0FFFF; \ |
| 3457 | REG_GPIO_GPAUR(0) |= 0x00050000; \ |
| 3458 | } while (0) |
| 3459 | |
| 3460 | #define __gpio_as_uart0() \ |
| 3461 | do { \ |
| 3462 | REG_GPIO_GPAUR(3) &= 0x0FFFFFFF; \ |
| 3463 | REG_GPIO_GPAUR(3) |= 0x50000000; \ |
| 3464 | } while (0) |
| 3465 | |
| 3466 | |
| 3467 | #define __gpio_as_scc0() \ |
| 3468 | do { \ |
| 3469 | REG_GPIO_GPALR(2) &= 0xFFFFFFCC; \ |
| 3470 | REG_GPIO_GPALR(2) |= 0x00000011; \ |
| 3471 | } while (0) |
| 3472 | |
| 3473 | #define __gpio_as_scc1() \ |
| 3474 | do { \ |
| 3475 | REG_GPIO_GPALR(2) &= 0xFFFFFF33; \ |
| 3476 | REG_GPIO_GPALR(2) |= 0x00000044; \ |
| 3477 | } while (0) |
| 3478 | |
| 3479 | #define __gpio_as_scc() \ |
| 3480 | do { \ |
| 3481 | __gpio_as_scc0(); \ |
| 3482 | __gpio_as_scc1(); \ |
| 3483 | } while (0) |
| 3484 | |
| 3485 | #define __gpio_as_dma() \ |
| 3486 | do { \ |
| 3487 | REG_GPIO_GPALR(0) &= 0x00FFFFFF; \ |
| 3488 | REG_GPIO_GPALR(0) |= 0x55000000; \ |
| 3489 | REG_GPIO_GPAUR(0) &= 0xFF0FFFFF; \ |
| 3490 | REG_GPIO_GPAUR(0) |= 0x00500000; \ |
| 3491 | } while (0) |
| 3492 | |
| 3493 | #define __gpio_as_msc() \ |
| 3494 | do { \ |
| 3495 | REG_GPIO_GPALR(1) &= 0xFFFF000F; \ |
| 3496 | REG_GPIO_GPALR(1) |= 0x00005550; \ |
| 3497 | } while (0) |
| 3498 | |
| 3499 | #define __gpio_as_pcmcia() \ |
| 3500 | do { \ |
| 3501 | REG_GPIO_GPAUR(2) &= 0xF000FFFF; \ |
| 3502 | REG_GPIO_GPAUR(2) |= 0x05550000; \ |
| 3503 | } while (0) |
| 3504 | |
| 3505 | #define __gpio_as_emc() \ |
| 3506 | do { \ |
| 3507 | REG_GPIO_GPALR(2) &= 0x3FFFFFFF; \ |
| 3508 | REG_GPIO_GPALR(2) |= 0x40000000; \ |
| 3509 | REG_GPIO_GPAUR(2) &= 0xFFFF0000; \ |
| 3510 | REG_GPIO_GPAUR(2) |= 0x00005555; \ |
| 3511 | } while (0) |
| 3512 | |
| 3513 | #define __gpio_as_lcd_slave() \ |
| 3514 | do { \ |
| 3515 | REG_GPIO_GPALR(1) &= 0x0000FFFF; \ |
| 3516 | REG_GPIO_GPALR(1) |= 0x55550000; \ |
| 3517 | REG_GPIO_GPAUR(1) &= 0x00000000; \ |
| 3518 | REG_GPIO_GPAUR(1) |= 0x55555555; \ |
| 3519 | } while (0) |
| 3520 | |
| 3521 | #define __gpio_as_lcd_master() \ |
| 3522 | do { \ |
| 3523 | REG_GPIO_GPALR(1) &= 0x0000FFFF; \ |
| 3524 | REG_GPIO_GPALR(1) |= 0x55550000; \ |
| 3525 | REG_GPIO_GPAUR(1) &= 0x00000000; \ |
| 3526 | REG_GPIO_GPAUR(1) |= 0x556A5555; \ |
| 3527 | } while (0) |
| 3528 | |
| 3529 | #define __gpio_as_usb() \ |
| 3530 | do { \ |
| 3531 | REG_GPIO_GPAUR(0) &= 0x00FFFFFF; \ |
| 3532 | REG_GPIO_GPAUR(0) |= 0x55000000; \ |
| 3533 | } while (0) |
| 3534 | |
| 3535 | #define __gpio_as_ac97() \ |
| 3536 | do { \ |
| 3537 | REG_GPIO_GPALR(2) &= 0xC3FF03FF; \ |
| 3538 | REG_GPIO_GPALR(2) |= 0x24005400; \ |
| 3539 | } while (0) |
| 3540 | |
| 3541 | #define __gpio_as_i2s_slave() \ |
| 3542 | do { \ |
| 3543 | REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ |
| 3544 | REG_GPIO_GPALR(2) |= 0x14005100; \ |
| 3545 | } while (0) |
| 3546 | |
| 3547 | #define __gpio_as_i2s_master() \ |
| 3548 | do { \ |
| 3549 | REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ |
| 3550 | REG_GPIO_GPALR(2) |= 0x28005100; \ |
| 3551 | } while (0) |
| 3552 | |
| 3553 | #define __gpio_as_eth() \ |
| 3554 | do { \ |
| 3555 | REG_GPIO_GPAUR(3) &= 0xFC000000; \ |
| 3556 | REG_GPIO_GPAUR(3) |= 0x01555555; \ |
| 3557 | } while (0) |
| 3558 | |
| 3559 | #define __gpio_as_pwm() \ |
| 3560 | do { \ |
| 3561 | REG_GPIO_GPAUR(2) &= 0x0FFFFFFF; \ |
| 3562 | REG_GPIO_GPAUR(2) |= 0x50000000; \ |
| 3563 | } while (0) |
| 3564 | |
| 3565 | #define __gpio_as_ps2() \ |
| 3566 | do { \ |
| 3567 | REG_GPIO_GPALR(1) &= 0xFFFFFFF0; \ |
| 3568 | REG_GPIO_GPALR(1) |= 0x00000005; \ |
| 3569 | } while (0) |
| 3570 | |
| 3571 | #define __gpio_as_uprt() \ |
| 3572 | do { \ |
| 3573 | REG_GPIO_GPALR(1) &= 0x0000000F; \ |
| 3574 | REG_GPIO_GPALR(1) |= 0x55555550; \ |
| 3575 | REG_GPIO_GPALR(3) &= 0xC0000000; \ |
| 3576 | REG_GPIO_GPALR(3) |= 0x15555555; \ |
| 3577 | } while (0) |
| 3578 | |
| 3579 | #define __gpio_as_cim() \ |
| 3580 | do { \ |
| 3581 | REG_GPIO_GPALR(0) &= 0xFF000000; \ |
| 3582 | REG_GPIO_GPALR(0) |= 0x00555555; \ |
| 3583 | } while (0) |
| 3584 | |
| 3585 | /*************************************************************************** |
| 3586 | * HARB |
| 3587 | ***************************************************************************/ |
| 3588 | |
| 3589 | #define __harb_usb0_udc() \ |
| 3590 | do { \ |
| 3591 | REG_HARB_HAPOR &= ~HARB_HAPOR_UCHSEL; \ |
| 3592 | } while (0) |
| 3593 | |
| 3594 | #define __harb_usb0_uhc() \ |
| 3595 | do { \ |
| 3596 | REG_HARB_HAPOR |= HARB_HAPOR_UCHSEL; \ |
| 3597 | } while (0) |
| 3598 | |
| 3599 | #define __harb_set_priority(n) \ |
| 3600 | do { \ |
| 3601 | REG_HARB_HAPOR = ((REG_HARB_HAPOR & ~HARB_HAPOR_PRIO_MASK) | n); \ |
| 3602 | } while (0) |
| 3603 | |
| 3604 | /*************************************************************************** |
| 3605 | * I2C |
| 3606 | ***************************************************************************/ |
| 3607 | |
| 3608 | #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) |
| 3609 | #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) |
| 3610 | |
| 3611 | #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) |
| 3612 | #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) |
| 3613 | #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) |
| 3614 | #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) |
| 3615 | |
| 3616 | #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) |
| 3617 | #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) |
| 3618 | #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) |
| 3619 | |
| 3620 | #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) |
| 3621 | #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) |
| 3622 | #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) |
| 3623 | |
| 3624 | #define __i2c_set_clk(dev_clk, i2c_clk) \ |
| 3625 | ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) |
| 3626 | |
| 3627 | #define __i2c_read() ( REG_I2C_DR ) |
| 3628 | #define __i2c_write(val) ( REG_I2C_DR = (val) ) |
| 3629 | |
| 3630 | /*************************************************************************** |
| 3631 | * UDC |
| 3632 | ***************************************************************************/ |
| 3633 | |
| 3634 | #define __udc_set_16bit_phy() ( REG_UDC_DevCFGR |= UDC_DevCFGR_PI ) |
| 3635 | #define __udc_set_8bit_phy() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_PI ) |
| 3636 | |
| 3637 | #define __udc_enable_sync_frame() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SS ) |
| 3638 | #define __udc_disable_sync_frame() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SS ) |
| 3639 | |
| 3640 | #define __udc_self_powered() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SP ) |
| 3641 | #define __udc_bus_powered() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SP ) |
| 3642 | |
| 3643 | #define __udc_enable_remote_wakeup() ( REG_UDC_DevCFGR |= UDC_DevCFGR_RW ) |
| 3644 | #define __udc_disable_remote_wakeup() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_RW ) |
| 3645 | |
| 3646 | #define __udc_set_speed_high() \ |
| 3647 | do { \ |
| 3648 | REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ |
| 3649 | REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_HS; \ |
| 3650 | } while (0) |
| 3651 | |
| 3652 | #define __udc_set_speed_full() \ |
| 3653 | do { \ |
| 3654 | REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ |
| 3655 | REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_FS; \ |
| 3656 | } while (0) |
| 3657 | |
| 3658 | #define __udc_set_speed_low() \ |
| 3659 | do { \ |
| 3660 | REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ |
| 3661 | REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_LS; \ |
| 3662 | } while (0) |
| 3663 | |
| 3664 | |
| 3665 | #define __udc_set_dma_mode() ( REG_UDC_DevCR |= UDC_DevCR_DM ) |
| 3666 | #define __udc_set_slave_mode() ( REG_UDC_DevCR &= ~UDC_DevCR_DM ) |
| 3667 | #define __udc_set_big_endian() ( REG_UDC_DevCR |= UDC_DevCR_BE ) |
| 3668 | #define __udc_set_little_endian() ( REG_UDC_DevCR &= ~UDC_DevCR_BE ) |
| 3669 | #define __udc_generate_resume() ( REG_UDC_DevCR |= UDC_DevCR_RES ) |
| 3670 | #define __udc_clear_resume() ( REG_UDC_DevCR &= ~UDC_DevCR_RES ) |
| 3671 | |
| 3672 | |
| 3673 | #define __udc_get_enumarated_speed() ( REG_UDC_DevSR & UDC_DevSR_ENUMSPD_MASK ) |
| 3674 | #define __udc_suspend_detected() ( REG_UDC_DevSR & UDC_DevSR_SUSP ) |
| 3675 | #define __udc_get_alternate_setting() ( (REG_UDC_DevSR & UDC_DevSR_ALT_MASK) >> UDC_DevSR_ALT_BIT ) |
| 3676 | #define __udc_get_interface_number() ( (REG_UDC_DevSR & UDC_DevSR_INTF_MASK) >> UDC_DevSR_INTF_BIT ) |
| 3677 | #define __udc_get_config_number() ( (REG_UDC_DevSR & UDC_DevSR_CFG_MASK) >> UDC_DevSR_CFG_BIT ) |
| 3678 | |
| 3679 | |
| 3680 | #define __udc_sof_detected(r) ( (r) & UDC_DevIntR_SOF ) |
| 3681 | #define __udc_usb_suspend_detected(r) ( (r) & UDC_DevIntR_US ) |
| 3682 | #define __udc_usb_reset_detected(r) ( (r) & UDC_DevIntR_UR ) |
| 3683 | #define __udc_set_interface_detected(r) ( (r) & UDC_DevIntR_SI ) |
| 3684 | #define __udc_set_config_detected(r) ( (r) & UDC_DevIntR_SC ) |
| 3685 | |
| 3686 | #define __udc_clear_sof() ( REG_UDC_DevIntR |= UDC_DevIntR_SOF ) |
| 3687 | #define __udc_clear_usb_suspend() ( REG_UDC_DevIntR |= UDC_DevIntR_US ) |
| 3688 | #define __udc_clear_usb_reset() ( REG_UDC_DevIntR |= UDC_DevIntR_UR ) |
| 3689 | #define __udc_clear_set_interface() ( REG_UDC_DevIntR |= UDC_DevIntR_SI ) |
| 3690 | #define __udc_clear_set_config() ( REG_UDC_DevIntR |= UDC_DevIntR_SC ) |
| 3691 | |
| 3692 | #define __udc_mask_sof() ( REG_UDC_DevIntMR |= UDC_DevIntR_SOF ) |
| 3693 | #define __udc_mask_usb_suspend() ( REG_UDC_DevIntMR |= UDC_DevIntR_US ) |
| 3694 | #define __udc_mask_usb_reset() ( REG_UDC_DevIntMR |= UDC_DevIntR_UR ) |
| 3695 | #define __udc_mask_set_interface() ( REG_UDC_DevIntMR |= UDC_DevIntR_SI ) |
| 3696 | #define __udc_mask_set_config() ( REG_UDC_DevIntMR |= UDC_DevIntR_SC ) |
| 3697 | #define __udc_mask_all_dev_intrs() \ |
| 3698 | ( REG_UDC_DevIntMR = UDC_DevIntR_SOF | UDC_DevIntR_US | \ |
| 3699 | UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC ) |
| 3700 | |
| 3701 | #define __udc_unmask_sof() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SOF ) |
| 3702 | #define __udc_unmask_usb_suspend() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_US ) |
| 3703 | #define __udc_unmask_usb_reset() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_UR ) |
| 3704 | #define __udc_unmask_set_interface() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SI ) |
| 3705 | #define __udc_unmask_set_config() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SC ) |
| 3706 | #if 0 |
| 3707 | #define __udc_unmask_all_dev_intrs() \ |
| 3708 | ( REG_UDC_DevIntMR = ~(UDC_DevIntR_SOF | UDC_DevIntR_US | \ |
| 3709 | UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC) ) |
| 3710 | #else |
| 3711 | #define __udc_unmask_all_dev_intrs() \ |
| 3712 | ( REG_UDC_DevIntMR = 0x00000000 ) |
| 3713 | #endif |
| 3714 | |
| 3715 | |
| 3716 | #define __udc_ep0out_irq_detected(epintr) \ |
| 3717 | ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 0)) & 0x1 ) |
| 3718 | #define __udc_ep5out_irq_detected(epintr) \ |
| 3719 | ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 5)) & 0x1 ) |
| 3720 | #define __udc_ep6out_irq_detected(epintr) \ |
| 3721 | ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 6)) & 0x1 ) |
| 3722 | #define __udc_ep7out_irq_detected(epintr) \ |
| 3723 | ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 7)) & 0x1 ) |
| 3724 | |
| 3725 | #define __udc_ep0in_irq_detected(epintr) \ |
| 3726 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 0)) & 0x1 ) |
| 3727 | #define __udc_ep1in_irq_detected(epintr) \ |
| 3728 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 1)) & 0x1 ) |
| 3729 | #define __udc_ep2in_irq_detected(epintr) \ |
| 3730 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 2)) & 0x1 ) |
| 3731 | #define __udc_ep3in_irq_detected(epintr) \ |
| 3732 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 3)) & 0x1 ) |
| 3733 | #define __udc_ep4in_irq_detected(epintr) \ |
| 3734 | ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 4)) & 0x1 ) |
| 3735 | |
| 3736 | |
| 3737 | #define __udc_mask_ep0out_irq() \ |
| 3738 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) |
| 3739 | #define __udc_mask_ep5out_irq() \ |
| 3740 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) |
| 3741 | #define __udc_mask_ep6out_irq() \ |
| 3742 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) |
| 3743 | #define __udc_mask_ep7out_irq() \ |
| 3744 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) |
| 3745 | |
| 3746 | #define __udc_unmask_ep0out_irq() \ |
| 3747 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) |
| 3748 | #define __udc_unmask_ep5out_irq() \ |
| 3749 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) |
| 3750 | #define __udc_unmask_ep6out_irq() \ |
| 3751 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) |
| 3752 | #define __udc_unmask_ep7out_irq() \ |
| 3753 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) |
| 3754 | |
| 3755 | #define __udc_mask_ep0in_irq() \ |
| 3756 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 0)) ) |
| 3757 | #define __udc_mask_ep1in_irq() \ |
| 3758 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 1)) ) |
| 3759 | #define __udc_mask_ep2in_irq() \ |
| 3760 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 2)) ) |
| 3761 | #define __udc_mask_ep3in_irq() \ |
| 3762 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 3)) ) |
| 3763 | #define __udc_mask_ep4in_irq() \ |
| 3764 | ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 4)) ) |
| 3765 | |
| 3766 | #define __udc_unmask_ep0in_irq() \ |
| 3767 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 0)) ) |
| 3768 | #define __udc_unmask_ep1in_irq() \ |
| 3769 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 1)) ) |
| 3770 | #define __udc_unmask_ep2in_irq() \ |
| 3771 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 2)) ) |
| 3772 | #define __udc_unmask_ep3in_irq() \ |
| 3773 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 3)) ) |
| 3774 | #define __udc_unmask_ep4in_irq() \ |
| 3775 | ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 4)) ) |
| 3776 | |
| 3777 | #define __udc_mask_all_ep_intrs() \ |
| 3778 | ( REG_UDC_EPIntMR = 0xffffffff ) |
| 3779 | #define __udc_unmask_all_ep_intrs() \ |
| 3780 | ( REG_UDC_EPIntMR = 0x00000000 ) |
| 3781 | |
| 3782 | |
| 3783 | /* ep0 only CTRL, ep1 only INTR, ep2/3/5/6 only BULK, ep4/7 only ISO */ |
| 3784 | #define __udc_config_endpoint_type() \ |
| 3785 | do { \ |
| 3786 | REG_UDC_EP0InCR = (REG_UDC_EP0InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ |
| 3787 | REG_UDC_EP0OutCR = (REG_UDC_EP0OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ |
| 3788 | REG_UDC_EP1InCR = (REG_UDC_EP1InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_INTR; \ |
| 3789 | REG_UDC_EP2InCR = (REG_UDC_EP2InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ |
| 3790 | REG_UDC_EP3InCR = (REG_UDC_EP3InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ |
| 3791 | REG_UDC_EP4InCR = (REG_UDC_EP4InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ |
| 3792 | REG_UDC_EP5OutCR = (REG_UDC_EP5OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ |
| 3793 | REG_UDC_EP6OutCR = (REG_UDC_EP6OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ |
| 3794 | REG_UDC_EP7OutCR = (REG_UDC_EP7OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ |
| 3795 | } while (0) |
| 3796 | |
| 3797 | #define __udc_enable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR |= UDC_EPCR_SN ) |
| 3798 | #define __udc_enable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR |= UDC_EPCR_SN ) |
| 3799 | #define __udc_enable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR |= UDC_EPCR_SN ) |
| 3800 | #define __udc_enable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR |= UDC_EPCR_SN ) |
| 3801 | |
| 3802 | #define __udc_disable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_SN ) |
| 3803 | #define __udc_disable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_SN ) |
| 3804 | #define __udc_disable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_SN ) |
| 3805 | #define __udc_disable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_SN ) |
| 3806 | |
| 3807 | #define __udc_flush_ep0in_fifo() ( REG_UDC_EP0InCR |= UDC_EPCR_F ) |
| 3808 | #define __udc_flush_ep1in_fifo() ( REG_UDC_EP1InCR |= UDC_EPCR_F ) |
| 3809 | #define __udc_flush_ep2in_fifo() ( REG_UDC_EP2InCR |= UDC_EPCR_F ) |
| 3810 | #define __udc_flush_ep3in_fifo() ( REG_UDC_EP3InCR |= UDC_EPCR_F ) |
| 3811 | #define __udc_flush_ep4in_fifo() ( REG_UDC_EP4InCR |= UDC_EPCR_F ) |
| 3812 | |
| 3813 | #define __udc_unflush_ep0in_fifo() ( REG_UDC_EP0InCR &= ~UDC_EPCR_F ) |
| 3814 | #define __udc_unflush_ep1in_fifo() ( REG_UDC_EP1InCR &= ~UDC_EPCR_F ) |
| 3815 | #define __udc_unflush_ep2in_fifo() ( REG_UDC_EP2InCR &= ~UDC_EPCR_F ) |
| 3816 | #define __udc_unflush_ep3in_fifo() ( REG_UDC_EP3InCR &= ~UDC_EPCR_F ) |
| 3817 | #define __udc_unflush_ep4in_fifo() ( REG_UDC_EP4InCR &= ~UDC_EPCR_F ) |
| 3818 | |
| 3819 | #define __udc_enable_ep0in_stall() ( REG_UDC_EP0InCR |= UDC_EPCR_S ) |
| 3820 | #define __udc_enable_ep0out_stall() ( REG_UDC_EP0OutCR |= UDC_EPCR_S ) |
| 3821 | #define __udc_enable_ep1in_stall() ( REG_UDC_EP1InCR |= UDC_EPCR_S ) |
| 3822 | #define __udc_enable_ep2in_stall() ( REG_UDC_EP2InCR |= UDC_EPCR_S ) |
| 3823 | #define __udc_enable_ep3in_stall() ( REG_UDC_EP3InCR |= UDC_EPCR_S ) |
| 3824 | #define __udc_enable_ep4in_stall() ( REG_UDC_EP4InCR |= UDC_EPCR_S ) |
| 3825 | #define __udc_enable_ep5out_stall() ( REG_UDC_EP5OutCR |= UDC_EPCR_S ) |
| 3826 | #define __udc_enable_ep6out_stall() ( REG_UDC_EP6OutCR |= UDC_EPCR_S ) |
| 3827 | #define __udc_enable_ep7out_stall() ( REG_UDC_EP7OutCR |= UDC_EPCR_S ) |
| 3828 | |
| 3829 | #define __udc_disable_ep0in_stall() ( REG_UDC_EP0InCR &= ~UDC_EPCR_S ) |
| 3830 | #define __udc_disable_ep0out_stall() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_S ) |
| 3831 | #define __udc_disable_ep1in_stall() ( REG_UDC_EP1InCR &= ~UDC_EPCR_S ) |
| 3832 | #define __udc_disable_ep2in_stall() ( REG_UDC_EP2InCR &= ~UDC_EPCR_S ) |
| 3833 | #define __udc_disable_ep3in_stall() ( REG_UDC_EP3InCR &= ~UDC_EPCR_S ) |
| 3834 | #define __udc_disable_ep4in_stall() ( REG_UDC_EP4InCR &= ~UDC_EPCR_S ) |
| 3835 | #define __udc_disable_ep5out_stall() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_S ) |
| 3836 | #define __udc_disable_ep6out_stall() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_S ) |
| 3837 | #define __udc_disable_ep7out_stall() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_S ) |
| 3838 | |
| 3839 | |
| 3840 | #define __udc_ep0out_packet_size() \ |
| 3841 | ( (REG_UDC_EP0OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) |
| 3842 | #define __udc_ep5out_packet_size() \ |
| 3843 | ( (REG_UDC_EP5OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) |
| 3844 | #define __udc_ep6out_packet_size() \ |
| 3845 | ( (REG_UDC_EP6OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) |
| 3846 | #define __udc_ep7out_packet_size() \ |
| 3847 | ( (REG_UDC_EP7OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) |
| 3848 | |
| 3849 | #define __udc_ep0in_received_intoken() ( (REG_UDC_EP0InSR & UDC_EPSR_IN) ) |
| 3850 | #define __udc_ep1in_received_intoken() ( (REG_UDC_EP1InSR & UDC_EPSR_IN) ) |
| 3851 | #define __udc_ep2in_received_intoken() ( (REG_UDC_EP2InSR & UDC_EPSR_IN) ) |
| 3852 | #define __udc_ep3in_received_intoken() ( (REG_UDC_EP3InSR & UDC_EPSR_IN) ) |
| 3853 | #define __udc_ep4in_received_intoken() ( (REG_UDC_EP4InSR & UDC_EPSR_IN) ) |
| 3854 | |
| 3855 | #define __udc_ep0out_received_none() \ |
| 3856 | ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) |
| 3857 | #define __udc_ep0out_received_data() \ |
| 3858 | ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) |
| 3859 | #define __udc_ep0out_received_setup() \ |
| 3860 | ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) |
| 3861 | |
| 3862 | #define __udc_ep5out_received_none() \ |
| 3863 | ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) |
| 3864 | #define __udc_ep5out_received_data() \ |
| 3865 | ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) |
| 3866 | #define __udc_ep5out_received_setup() \ |
| 3867 | ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) |
| 3868 | |
| 3869 | #define __udc_ep6out_received_none() \ |
| 3870 | ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) |
| 3871 | #define __udc_ep6out_received_data() \ |
| 3872 | ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) |
| 3873 | #define __udc_ep6out_received_setup() \ |
| 3874 | ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) |
| 3875 | |
| 3876 | #define __udc_ep7out_received_none() \ |
| 3877 | ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) |
| 3878 | #define __udc_ep7out_received_data() \ |
| 3879 | ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) |
| 3880 | #define __udc_ep7out_received_setup() \ |
| 3881 | ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) |
| 3882 | |
| 3883 | /* ep7out ISO only */ |
| 3884 | #define __udc_ep7out_get_pid() \ |
| 3885 | ( (REG_UDC_EP7OutSR & UDC_EPSR_PID_MASK) >> UDC_EPSR_PID_BIT ) |
| 3886 | |
| 3887 | |
| 3888 | #define __udc_ep0in_set_buffer_size(n) ( REG_UDC_EP0InBSR = (n) ) |
| 3889 | #define __udc_ep1in_set_buffer_size(n) ( REG_UDC_EP1InBSR = (n) ) |
| 3890 | #define __udc_ep2in_set_buffer_size(n) ( REG_UDC_EP2InBSR = (n) ) |
| 3891 | #define __udc_ep3in_set_buffer_size(n) ( REG_UDC_EP3InBSR = (n) ) |
| 3892 | #define __udc_ep4in_set_buffer_size(n) ( REG_UDC_EP4InBSR = (n) ) |
| 3893 | |
| 3894 | #define __udc_ep0out_get_frame_number(n) ( UDC_EP0OutPFNR ) |
| 3895 | #define __udc_ep5out_get_frame_number(n) ( UDC_EP5OutPFNR ) |
| 3896 | #define __udc_ep6out_get_frame_number(n) ( UDC_EP6OutPFNR ) |
| 3897 | #define __udc_ep7out_get_frame_number(n) ( UDC_EP7OutPFNR ) |
| 3898 | |
| 3899 | |
| 3900 | #define __udc_ep0in_set_max_packet_size(n) ( REG_UDC_EP0InMPSR = (n) ) |
| 3901 | #define __udc_ep0out_set_max_packet_size(n) ( REG_UDC_EP0OutMPSR = (n) ) |
| 3902 | #define __udc_ep1in_set_max_packet_size(n) ( REG_UDC_EP1InMPSR = (n) ) |
| 3903 | #define __udc_ep2in_set_max_packet_size(n) ( REG_UDC_EP2InMPSR = (n) ) |
| 3904 | #define __udc_ep3in_set_max_packet_size(n) ( REG_UDC_EP3InMPSR = (n) ) |
| 3905 | #define __udc_ep4in_set_max_packet_size(n) ( REG_UDC_EP4InMPSR = (n) ) |
| 3906 | #define __udc_ep5out_set_max_packet_size(n) ( REG_UDC_EP5OutMPSR = (n) ) |
| 3907 | #define __udc_ep6out_set_max_packet_size(n) ( REG_UDC_EP6OutMPSR = (n) ) |
| 3908 | #define __udc_ep7out_set_max_packet_size(n) ( REG_UDC_EP7OutMPSR = (n) ) |
| 3909 | |
| 3910 | /* set to 0xFFFF for UDC */ |
| 3911 | #define __udc_set_setup_command_address(n) ( REG_UDC_STCMAR = (n) ) |
| 3912 | |
| 3913 | /* Init and configure EPxInfR(x=0,1,2,3,4,5,6,7) |
| 3914 | * c: Configuration number to which this endpoint belongs |
| 3915 | * i: Interface number to which this endpoint belongs |
| 3916 | * a: Alternate setting to which this endpoint belongs |
| 3917 | * p: max Packet size of this endpoint |
| 3918 | */ |
| 3919 | |
| 3920 | #define __udc_ep0info_init(c,i,a,p) \ |
| 3921 | do { \ |
| 3922 | REG_UDC_EP0InfR &= ~UDC_EPInfR_MPS_MASK; \ |
| 3923 | REG_UDC_EP0InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
| 3924 | REG_UDC_EP0InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
| 3925 | REG_UDC_EP0InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
| 3926 | REG_UDC_EP0InfR &= ~UDC_EPInfR_IFN_MASK; \ |
| 3927 | REG_UDC_EP0InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
| 3928 | REG_UDC_EP0InfR &= ~UDC_EPInfR_CGN_MASK; \ |
| 3929 | REG_UDC_EP0InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
| 3930 | REG_UDC_EP0InfR &= ~UDC_EPInfR_EPT_MASK; \ |
| 3931 | REG_UDC_EP0InfR |= UDC_EPInfR_EPT_CTRL; \ |
| 3932 | REG_UDC_EP0InfR &= ~UDC_EPInfR_EPD; \ |
| 3933 | REG_UDC_EP0InfR |= UDC_EPInfR_EPD_OUT; \ |
| 3934 | REG_UDC_EP0InfR &= ~UDC_EPInfR_EPN_MASK; \ |
| 3935 | REG_UDC_EP0InfR |= (0 << UDC_EPInfR_EPN_BIT); \ |
| 3936 | } while (0) |
| 3937 | |
| 3938 | #define __udc_ep1info_init(c,i,a,p) \ |
| 3939 | do { \ |
| 3940 | REG_UDC_EP1InfR &= ~UDC_EPInfR_MPS_MASK; \ |
| 3941 | REG_UDC_EP1InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
| 3942 | REG_UDC_EP1InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
| 3943 | REG_UDC_EP1InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
| 3944 | REG_UDC_EP1InfR &= ~UDC_EPInfR_IFN_MASK; \ |
| 3945 | REG_UDC_EP1InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
| 3946 | REG_UDC_EP1InfR &= ~UDC_EPInfR_CGN_MASK; \ |
| 3947 | REG_UDC_EP1InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
| 3948 | REG_UDC_EP1InfR &= ~UDC_EPInfR_EPT_MASK; \ |
| 3949 | REG_UDC_EP1InfR |= UDC_EPInfR_EPT_INTR; \ |
| 3950 | REG_UDC_EP1InfR &= ~UDC_EPInfR_EPD; \ |
| 3951 | REG_UDC_EP1InfR |= UDC_EPInfR_EPD_IN; \ |
| 3952 | REG_UDC_EP1InfR &= ~UDC_EPInfR_EPN_MASK; \ |
| 3953 | REG_UDC_EP1InfR |= (1 << UDC_EPInfR_EPN_BIT); \ |
| 3954 | } while (0) |
| 3955 | |
| 3956 | #define __udc_ep2info_init(c,i,a,p) \ |
| 3957 | do { \ |
| 3958 | REG_UDC_EP2InfR &= ~UDC_EPInfR_MPS_MASK; \ |
| 3959 | REG_UDC_EP2InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
| 3960 | REG_UDC_EP2InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
| 3961 | REG_UDC_EP2InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
| 3962 | REG_UDC_EP2InfR &= ~UDC_EPInfR_IFN_MASK; \ |
| 3963 | REG_UDC_EP2InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
| 3964 | REG_UDC_EP2InfR &= ~UDC_EPInfR_CGN_MASK; \ |
| 3965 | REG_UDC_EP2InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
| 3966 | REG_UDC_EP2InfR &= ~UDC_EPInfR_EPT_MASK; \ |
| 3967 | REG_UDC_EP2InfR |= UDC_EPInfR_EPT_BULK; \ |
| 3968 | REG_UDC_EP2InfR &= ~UDC_EPInfR_EPD; \ |
| 3969 | REG_UDC_EP2InfR |= UDC_EPInfR_EPD_IN; \ |
| 3970 | REG_UDC_EP2InfR &= ~UDC_EPInfR_EPN_MASK; \ |
| 3971 | REG_UDC_EP2InfR |= (2 << UDC_EPInfR_EPN_BIT); \ |
| 3972 | } while (0) |
| 3973 | |
| 3974 | #define __udc_ep3info_init(c,i,a,p) \ |
| 3975 | do { \ |
| 3976 | REG_UDC_EP3InfR &= ~UDC_EPInfR_MPS_MASK; \ |
| 3977 | REG_UDC_EP3InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
| 3978 | REG_UDC_EP3InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
| 3979 | REG_UDC_EP3InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
| 3980 | REG_UDC_EP3InfR &= ~UDC_EPInfR_IFN_MASK; \ |
| 3981 | REG_UDC_EP3InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
| 3982 | REG_UDC_EP3InfR &= ~UDC_EPInfR_CGN_MASK; \ |
| 3983 | REG_UDC_EP3InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
| 3984 | REG_UDC_EP3InfR &= ~UDC_EPInfR_EPT_MASK; \ |
| 3985 | REG_UDC_EP3InfR |= UDC_EPInfR_EPT_BULK; \ |
| 3986 | REG_UDC_EP3InfR &= ~UDC_EPInfR_EPD; \ |
| 3987 | REG_UDC_EP3InfR |= UDC_EPInfR_EPD_IN; \ |
| 3988 | REG_UDC_EP3InfR &= ~UDC_EPInfR_EPN_MASK; \ |
| 3989 | REG_UDC_EP3InfR |= (3 << UDC_EPInfR_EPN_BIT); \ |
| 3990 | } while (0) |
| 3991 | |
| 3992 | #define __udc_ep4info_init(c,i,a,p) \ |
| 3993 | do { \ |
| 3994 | REG_UDC_EP4InfR &= ~UDC_EPInfR_MPS_MASK; \ |
| 3995 | REG_UDC_EP4InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
| 3996 | REG_UDC_EP4InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
| 3997 | REG_UDC_EP4InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
| 3998 | REG_UDC_EP4InfR &= ~UDC_EPInfR_IFN_MASK; \ |
| 3999 | REG_UDC_EP4InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
| 4000 | REG_UDC_EP4InfR &= ~UDC_EPInfR_CGN_MASK; \ |
| 4001 | REG_UDC_EP4InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
| 4002 | REG_UDC_EP4InfR &= ~UDC_EPInfR_EPT_MASK; \ |
| 4003 | REG_UDC_EP4InfR |= UDC_EPInfR_EPT_ISO; \ |
| 4004 | REG_UDC_EP4InfR &= ~UDC_EPInfR_EPD; \ |
| 4005 | REG_UDC_EP4InfR |= UDC_EPInfR_EPD_IN; \ |
| 4006 | REG_UDC_EP4InfR &= ~UDC_EPInfR_EPN_MASK; \ |
| 4007 | REG_UDC_EP4InfR |= (4 << UDC_EPInfR_EPN_BIT); \ |
| 4008 | } while (0) |
| 4009 | |
| 4010 | #define __udc_ep5info_init(c,i,a,p) \ |
| 4011 | do { \ |
| 4012 | REG_UDC_EP5InfR &= ~UDC_EPInfR_MPS_MASK; \ |
| 4013 | REG_UDC_EP5InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
| 4014 | REG_UDC_EP5InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
| 4015 | REG_UDC_EP5InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
| 4016 | REG_UDC_EP5InfR &= ~UDC_EPInfR_IFN_MASK; \ |
| 4017 | REG_UDC_EP5InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
| 4018 | REG_UDC_EP5InfR &= ~UDC_EPInfR_CGN_MASK; \ |
| 4019 | REG_UDC_EP5InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
| 4020 | REG_UDC_EP5InfR &= ~UDC_EPInfR_EPT_MASK; \ |
| 4021 | REG_UDC_EP5InfR |= UDC_EPInfR_EPT_BULK; \ |
| 4022 | REG_UDC_EP5InfR &= ~UDC_EPInfR_EPD; \ |
| 4023 | REG_UDC_EP5InfR |= UDC_EPInfR_EPD_OUT; \ |
| 4024 | REG_UDC_EP5InfR &= ~UDC_EPInfR_EPN_MASK; \ |
| 4025 | REG_UDC_EP5InfR |= (5 << UDC_EPInfR_EPN_BIT); \ |
| 4026 | } while (0) |
| 4027 | |
| 4028 | #define __udc_ep6info_init(c,i,a,p) \ |
| 4029 | do { \ |
| 4030 | REG_UDC_EP6InfR &= ~UDC_EPInfR_MPS_MASK; \ |
| 4031 | REG_UDC_EP6InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
| 4032 | REG_UDC_EP6InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
| 4033 | REG_UDC_EP6InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
| 4034 | REG_UDC_EP6InfR &= ~UDC_EPInfR_IFN_MASK; \ |
| 4035 | REG_UDC_EP6InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
| 4036 | REG_UDC_EP6InfR &= ~UDC_EPInfR_CGN_MASK; \ |
| 4037 | REG_UDC_EP6InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
| 4038 | REG_UDC_EP6InfR &= ~UDC_EPInfR_EPT_MASK; \ |
| 4039 | REG_UDC_EP6InfR |= UDC_EPInfR_EPT_BULK; \ |
| 4040 | REG_UDC_EP6InfR &= ~UDC_EPInfR_EPD; \ |
| 4041 | REG_UDC_EP6InfR |= UDC_EPInfR_EPD_OUT; \ |
| 4042 | REG_UDC_EP6InfR &= ~UDC_EPInfR_EPN_MASK; \ |
| 4043 | REG_UDC_EP6InfR |= (6 << UDC_EPInfR_EPN_BIT); \ |
| 4044 | } while (0) |
| 4045 | |
| 4046 | #define __udc_ep7info_init(c,i,a,p) \ |
| 4047 | do { \ |
| 4048 | REG_UDC_EP7InfR &= ~UDC_EPInfR_MPS_MASK; \ |
| 4049 | REG_UDC_EP7InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ |
| 4050 | REG_UDC_EP7InfR &= ~UDC_EPInfR_ALTS_MASK; \ |
| 4051 | REG_UDC_EP7InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ |
| 4052 | REG_UDC_EP7InfR &= ~UDC_EPInfR_IFN_MASK; \ |
| 4053 | REG_UDC_EP7InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ |
| 4054 | REG_UDC_EP7InfR &= ~UDC_EPInfR_CGN_MASK; \ |
| 4055 | REG_UDC_EP7InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ |
| 4056 | REG_UDC_EP7InfR &= ~UDC_EPInfR_EPT_MASK; \ |
| 4057 | REG_UDC_EP7InfR |= UDC_EPInfR_EPT_ISO; \ |
| 4058 | REG_UDC_EP7InfR &= ~UDC_EPInfR_EPD; \ |
| 4059 | REG_UDC_EP7InfR |= UDC_EPInfR_EPD_OUT; \ |
| 4060 | REG_UDC_EP7InfR &= ~UDC_EPInfR_EPN_MASK; \ |
| 4061 | REG_UDC_EP7InfR |= (7 << UDC_EPInfR_EPN_BIT); \ |
| 4062 | } while (0) |
| 4063 | |
| 4064 | |
| 4065 | /*************************************************************************** |
| 4066 | * DMAC |
| 4067 | ***************************************************************************/ |
| 4068 | |
| 4069 | /* n is the DMA channel (0 - 7) */ |
| 4070 | |
| 4071 | #define __dmac_enable_all_channels() \ |
| 4072 | ( REG_DMAC_DMACR |= DMAC_DMACR_DME | DMAC_DMACR_PR_ROUNDROBIN ) |
| 4073 | #define __dmac_disable_all_channels() \ |
| 4074 | ( REG_DMAC_DMACR &= ~DMAC_DMACR_DME ) |
| 4075 | |
| 4076 | /* p=0,1,2,3 */ |
| 4077 | #define __dmac_set_priority(p) \ |
| 4078 | do { \ |
| 4079 | REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ |
| 4080 | REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ |
| 4081 | } while (0) |
| 4082 | |
| 4083 | #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HTR ) |
| 4084 | #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AER ) |
| 4085 | |
| 4086 | #define __dmac_enable_channel(n) \ |
| 4087 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_CHDE ) |
| 4088 | #define __dmac_disable_channel(n) \ |
| 4089 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_CHDE ) |
| 4090 | #define __dmac_channel_enabled(n) \ |
| 4091 | ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_CHDE ) |
| 4092 | |
| 4093 | #define __dmac_channel_enable_irq(n) \ |
| 4094 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TCIE ) |
| 4095 | #define __dmac_channel_disable_irq(n) \ |
| 4096 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TCIE ) |
| 4097 | |
| 4098 | #define __dmac_channel_transmit_halt_detected(n) \ |
| 4099 | ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_HLT ) |
| 4100 | #define __dmac_channel_transmit_end_detected(n) \ |
| 4101 | ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_TC ) |
| 4102 | #define __dmac_channel_address_error_detected(n) \ |
| 4103 | ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_AR ) |
| 4104 | |
| 4105 | #define __dmac_channel_clear_transmit_halt(n) \ |
| 4106 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) |
| 4107 | #define __dmac_channel_clear_transmit_end(n) \ |
| 4108 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TC ) |
| 4109 | #define __dmac_channel_clear_address_error(n) \ |
| 4110 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) |
| 4111 | |
| 4112 | #define __dmac_channel_set_single_mode(n) \ |
| 4113 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TM ) |
| 4114 | #define __dmac_channel_set_block_mode(n) \ |
| 4115 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TM ) |
| 4116 | |
| 4117 | #define __dmac_channel_set_transfer_unit_32bit(n) \ |
| 4118 | do { \ |
| 4119 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
| 4120 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32b; \ |
| 4121 | } while (0) |
| 4122 | |
| 4123 | #define __dmac_channel_set_transfer_unit_16bit(n) \ |
| 4124 | do { \ |
| 4125 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
| 4126 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16b; \ |
| 4127 | } while (0) |
| 4128 | |
| 4129 | #define __dmac_channel_set_transfer_unit_8bit(n) \ |
| 4130 | do { \ |
| 4131 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
| 4132 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_8b; \ |
| 4133 | } while (0) |
| 4134 | |
| 4135 | #define __dmac_channel_set_transfer_unit_16byte(n) \ |
| 4136 | do { \ |
| 4137 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
| 4138 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16B; \ |
| 4139 | } while (0) |
| 4140 | |
| 4141 | #define __dmac_channel_set_transfer_unit_32byte(n) \ |
| 4142 | do { \ |
| 4143 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ |
| 4144 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32B; \ |
| 4145 | } while (0) |
| 4146 | |
| 4147 | /* w=8,16,32 */ |
| 4148 | #define __dmac_channel_set_dest_port_width(n,w) \ |
| 4149 | do { \ |
| 4150 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DWDH_MASK; \ |
| 4151 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DWDH_##w; \ |
| 4152 | } while (0) |
| 4153 | |
| 4154 | /* w=8,16,32 */ |
| 4155 | #define __dmac_channel_set_src_port_width(n,w) \ |
| 4156 | do { \ |
| 4157 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ |
| 4158 | REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SWDH_##w; \ |
| 4159 | } while (0) |
| 4160 | |
| 4161 | /* v=0-15 */ |
| 4162 | #define __dmac_channel_set_rdil(n,v) \ |
| 4163 | do { \ |
| 4164 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_RDIL_MASK; \ |
| 4165 | REG_DMAC_DCCSR(n) |= ((v) << DMAC_DCCSR_RDIL_BIT); \ |
| 4166 | } while (0) |
| 4167 | |
| 4168 | #define __dmac_channel_dest_addr_fixed(n) \ |
| 4169 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DAM ) |
| 4170 | #define __dmac_channel_dest_addr_increment(n) \ |
| 4171 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DAM ) |
| 4172 | |
| 4173 | #define __dmac_channel_src_addr_fixed(n) \ |
| 4174 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SAM ) |
| 4175 | #define __dmac_channel_src_addr_increment(n) \ |
| 4176 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SAM ) |
| 4177 | |
| 4178 | #define __dmac_channel_set_eop_high(n) \ |
| 4179 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EOPM ) |
| 4180 | #define __dmac_channel_set_eop_low(n) \ |
| 4181 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EOPM ) |
| 4182 | |
| 4183 | #define __dmac_channel_set_erdm(n,m) \ |
| 4184 | do { \ |
| 4185 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ |
| 4186 | REG_DMAC_DCCSR(n) |= ((m) << DMAC_DCCSR_ERDM_BIT); \ |
| 4187 | } while (0) |
| 4188 | |
| 4189 | #define __dmac_channel_set_eackm(n) \ |
| 4190 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKM ) |
| 4191 | #define __dmac_channel_clear_eackm(n) \ |
| 4192 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKM ) |
| 4193 | |
| 4194 | #define __dmac_channel_set_eacks(n) \ |
| 4195 | ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKS ) |
| 4196 | #define __dmac_channel_clear_eacks(n) \ |
| 4197 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKS ) |
| 4198 | |
| 4199 | |
| 4200 | #define __dmac_channel_irq_detected(n) \ |
| 4201 | ( REG_DMAC_DCCSR(n) & (DMAC_DCCSR_TC | DMAC_DCCSR_AR) ) |
| 4202 | |
| 4203 | static __inline__ int __dmac_get_irq(void) |
| 4204 | { |
| 4205 | int i; |
| 4206 | for (i=0;i<NUM_DMA;i++) |
| 4207 | if (__dmac_channel_irq_detected(i)) |
| 4208 | return i; |
| 4209 | return -1; |
| 4210 | } |
| 4211 | |
| 4212 | /*************************************************************************** |
| 4213 | * AIC (AC'97 & I2S Controller) |
| 4214 | ***************************************************************************/ |
| 4215 | |
| 4216 | #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) |
| 4217 | #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) |
| 4218 | #define __aic_reset() ( REG_AIC_FR |= AIC_FR_RST ) |
| 4219 | #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) |
| 4220 | #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) |
| 4221 | |
| 4222 | #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) |
| 4223 | #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) |
| 4224 | |
| 4225 | #define __aic_set_transmit_trigger(n) \ |
| 4226 | do { \ |
| 4227 | REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ |
| 4228 | REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ |
| 4229 | } while(0) |
| 4230 | |
| 4231 | #define __aic_set_receive_trigger(n) \ |
| 4232 | do { \ |
| 4233 | REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ |
| 4234 | REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ |
| 4235 | } while(0) |
| 4236 | |
| 4237 | #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) |
| 4238 | #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) |
| 4239 | #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) |
| 4240 | #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) |
| 4241 | #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) |
| 4242 | #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) |
| 4243 | |
| 4244 | #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) |
| 4245 | #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) |
| 4246 | |
| 4247 | #define __aic_enable_transmit_intr() \ |
| 4248 | ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) |
| 4249 | #define __aic_disable_transmit_intr() \ |
| 4250 | ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) |
| 4251 | #define __aic_enable_receive_intr() \ |
| 4252 | ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) |
| 4253 | #define __aic_disable_receive_intr() \ |
| 4254 | ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) |
| 4255 | |
| 4256 | #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) |
| 4257 | #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) |
| 4258 | #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) |
| 4259 | #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) |
| 4260 | |
| 4261 | #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 |
| 4262 | #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 |
| 4263 | #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 |
| 4264 | #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 |
| 4265 | #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 |
| 4266 | #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 |
| 4267 | |
| 4268 | #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 |
| 4269 | #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 |
| 4270 | #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 |
| 4271 | #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 |
| 4272 | #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 |
| 4273 | #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 |
| 4274 | |
| 4275 | #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) |
| 4276 | #define __ac97_set_xs_mono() \ |
| 4277 | do { \ |
| 4278 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ |
| 4279 | REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ |
| 4280 | } while(0) |
| 4281 | #define __ac97_set_xs_stereo() \ |
| 4282 | do { \ |
| 4283 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ |
| 4284 | REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ |
| 4285 | } while(0) |
| 4286 | |
| 4287 | /* In fact, only stereo is support now. */ |
| 4288 | #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) |
| 4289 | #define __ac97_set_rs_mono() \ |
| 4290 | do { \ |
| 4291 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ |
| 4292 | REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ |
| 4293 | } while(0) |
| 4294 | #define __ac97_set_rs_stereo() \ |
| 4295 | do { \ |
| 4296 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ |
| 4297 | REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ |
| 4298 | } while(0) |
| 4299 | |
| 4300 | #define __ac97_warm_reset_codec() \ |
| 4301 | do { \ |
| 4302 | REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ |
| 4303 | REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ |
| 4304 | udelay(1); \ |
| 4305 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ |
| 4306 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ |
| 4307 | } while (0) |
| 4308 | |
| 4309 | //#define Jz_AC97_RESET_BUG 1 |
| 4310 | #ifndef Jz_AC97_RESET_BUG |
| 4311 | #define __ac97_cold_reset_codec() \ |
| 4312 | do { \ |
| 4313 | REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ |
| 4314 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ |
| 4315 | REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ |
| 4316 | udelay(1); \ |
| 4317 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ |
| 4318 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ |
| 4319 | } while (0) |
| 4320 | #else |
| 4321 | #define __ac97_cold_reset_codec() \ |
| 4322 | do { \ |
| 4323 | __gpio_as_output(111); /* SDATA_OUT */ \ |
| 4324 | __gpio_as_output(110); /* SDATA_IN */ \ |
| 4325 | __gpio_as_output(112); /* SYNC */ \ |
| 4326 | __gpio_as_output(114); /* RESET# */ \ |
| 4327 | __gpio_clear_pin(111); \ |
| 4328 | __gpio_clear_pin(110); \ |
| 4329 | __gpio_clear_pin(112); \ |
| 4330 | __gpio_clear_pin(114); \ |
| 4331 | udelay(2); \ |
| 4332 | __gpio_set_pin(114); \ |
| 4333 | udelay(1); \ |
| 4334 | __gpio_as_ac97(); \ |
| 4335 | } while (0) |
| 4336 | #endif |
| 4337 | |
| 4338 | /* n=8,16,18,20 */ |
| 4339 | #define __ac97_set_iass(n) \ |
| 4340 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) |
| 4341 | #define __ac97_set_oass(n) \ |
| 4342 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) |
| 4343 | |
| 4344 | #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) |
| 4345 | #define __i2s_select_left_justified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) |
| 4346 | |
| 4347 | /* n=8,16,18,20,24 */ |
| 4348 | #define __i2s_set_sample_size(n) \ |
| 4349 | ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT ) |
| 4350 | |
| 4351 | #define __i2s_stop_clock() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) |
| 4352 | #define __i2s_start_clock() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) |
| 4353 | |
| 4354 | #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) |
| 4355 | #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) |
| 4356 | #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) |
| 4357 | #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) |
| 4358 | |
| 4359 | #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) |
| 4360 | |
| 4361 | #define __aic_get_transmit_resident() \ |
| 4362 | ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) |
| 4363 | #define __aic_get_receive_count() \ |
| 4364 | ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) |
| 4365 | |
| 4366 | #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) |
| 4367 | #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) |
| 4368 | #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) |
| 4369 | #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) |
| 4370 | #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) |
| 4371 | |
| 4372 | #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) |
| 4373 | |
| 4374 | #define CODEC_READ_CMD (1 << 19) |
| 4375 | #define CODEC_WRITE_CMD (0 << 19) |
| 4376 | #define CODEC_REG_INDEX_BIT 12 |
| 4377 | #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ |
| 4378 | #define CODEC_REG_DATA_BIT 4 |
| 4379 | #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ |
| 4380 | |
| 4381 | #define __ac97_out_rcmd_addr(reg) \ |
| 4382 | do { \ |
| 4383 | REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ |
| 4384 | } while (0) |
| 4385 | |
| 4386 | #define __ac97_out_wcmd_addr(reg) \ |
| 4387 | do { \ |
| 4388 | REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ |
| 4389 | } while (0) |
| 4390 | |
| 4391 | #define __ac97_out_data(value) \ |
| 4392 | do { \ |
| 4393 | REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ |
| 4394 | } while (0) |
| 4395 | |
| 4396 | #define __ac97_in_data() \ |
| 4397 | ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) |
| 4398 | |
| 4399 | #define __ac97_in_status_addr() \ |
| 4400 | ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) |
| 4401 | |
| 4402 | #define __i2s_set_sample_rate(i2sclk, sync) \ |
| 4403 | ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) |
| 4404 | |
| 4405 | #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) |
| 4406 | #define __aic_read_rfifo() ( REG_AIC_DR ) |
| 4407 | |
| 4408 | // |
| 4409 | // Define next ops for AC97 compatible |
| 4410 | // |
| 4411 | |
| 4412 | #define AC97_ACSR AIC_ACSR |
| 4413 | |
| 4414 | #define __ac97_enable() __aic_enable(); __aic_select_ac97() |
| 4415 | #define __ac97_disable() __aic_disable() |
| 4416 | #define __ac97_reset() __aic_reset() |
| 4417 | |
| 4418 | #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) |
| 4419 | #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) |
| 4420 | |
| 4421 | #define __ac97_enable_record() __aic_enable_record() |
| 4422 | #define __ac97_disable_record() __aic_disable_record() |
| 4423 | #define __ac97_enable_replay() __aic_enable_replay() |
| 4424 | #define __ac97_disable_replay() __aic_disable_replay() |
| 4425 | #define __ac97_enable_loopback() __aic_enable_loopback() |
| 4426 | #define __ac97_disable_loopback() __aic_disable_loopback() |
| 4427 | |
| 4428 | #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() |
| 4429 | #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() |
| 4430 | #define __ac97_enable_receive_dma() __aic_enable_receive_dma() |
| 4431 | #define __ac97_disable_receive_dma() __aic_disable_receive_dma() |
| 4432 | |
| 4433 | #define __ac97_transmit_request() __aic_transmit_request() |
| 4434 | #define __ac97_receive_request() __aic_receive_request() |
| 4435 | #define __ac97_transmit_underrun() __aic_transmit_underrun() |
| 4436 | #define __ac97_receive_overrun() __aic_receive_overrun() |
| 4437 | |
| 4438 | #define __ac97_clear_errors() __aic_clear_errors() |
| 4439 | |
| 4440 | #define __ac97_get_transmit_resident() __aic_get_transmit_resident() |
| 4441 | #define __ac97_get_receive_count() __aic_get_receive_count() |
| 4442 | |
| 4443 | #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() |
| 4444 | #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() |
| 4445 | #define __ac97_enable_receive_intr() __aic_enable_receive_intr() |
| 4446 | #define __ac97_disable_receive_intr() __aic_disable_receive_intr() |
| 4447 | |
| 4448 | #define __ac97_write_tfifo(v) __aic_write_tfifo(v) |
| 4449 | #define __ac97_read_rfifo() __aic_read_rfifo() |
| 4450 | |
| 4451 | // |
| 4452 | // Define next ops for I2S compatible |
| 4453 | // |
| 4454 | |
| 4455 | #define I2S_ACSR AIC_I2SSR |
| 4456 | |
| 4457 | #define __i2s_enable() __aic_enable(); __aic_select_i2s() |
| 4458 | #define __i2s_disable() __aic_disable() |
| 4459 | #define __i2s_reset() __aic_reset() |
| 4460 | |
| 4461 | #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) |
| 4462 | #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) |
| 4463 | |
| 4464 | #define __i2s_enable_record() __aic_enable_record() |
| 4465 | #define __i2s_disable_record() __aic_disable_record() |
| 4466 | #define __i2s_enable_replay() __aic_enable_replay() |
| 4467 | #define __i2s_disable_replay() __aic_disable_replay() |
| 4468 | #define __i2s_enable_loopback() __aic_enable_loopback() |
| 4469 | #define __i2s_disable_loopback() __aic_disable_loopback() |
| 4470 | |
| 4471 | #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() |
| 4472 | #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() |
| 4473 | #define __i2s_enable_receive_dma() __aic_enable_receive_dma() |
| 4474 | #define __i2s_disable_receive_dma() __aic_disable_receive_dma() |
| 4475 | |
| 4476 | #define __i2s_transmit_request() __aic_transmit_request() |
| 4477 | #define __i2s_receive_request() __aic_receive_request() |
| 4478 | #define __i2s_transmit_underrun() __aic_transmit_underrun() |
| 4479 | #define __i2s_receive_overrun() __aic_receive_overrun() |
| 4480 | |
| 4481 | #define __i2s_clear_errors() __aic_clear_errors() |
| 4482 | |
| 4483 | #define __i2s_get_transmit_resident() __aic_get_transmit_resident() |
| 4484 | #define __i2s_get_receive_count() __aic_get_receive_count() |
| 4485 | |
| 4486 | #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() |
| 4487 | #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() |
| 4488 | #define __i2s_enable_receive_intr() __aic_enable_receive_intr() |
| 4489 | #define __i2s_disable_receive_intr() __aic_disable_receive_intr() |
| 4490 | |
| 4491 | #define __i2s_write_tfifo(v) __aic_write_tfifo(v) |
| 4492 | #define __i2s_read_rfifo() __aic_read_rfifo() |
| 4493 | |
| 4494 | #define __i2s_reset_codec() \ |
| 4495 | do { \ |
| 4496 | __gpio_as_output(111); /* SDATA_OUT */ \ |
| 4497 | __gpio_as_input(110); /* SDATA_IN */ \ |
| 4498 | __gpio_as_output(112); /* SYNC */ \ |
| 4499 | __gpio_as_output(114); /* RESET# */ \ |
| 4500 | __gpio_clear_pin(111); \ |
| 4501 | __gpio_clear_pin(110); \ |
| 4502 | __gpio_clear_pin(112); \ |
| 4503 | __gpio_clear_pin(114); \ |
| 4504 | __gpio_as_i2s_master(); \ |
| 4505 | } while (0) |
| 4506 | |
| 4507 | |
| 4508 | /*************************************************************************** |
| 4509 | * LCD |
| 4510 | ***************************************************************************/ |
| 4511 | |
| 4512 | #define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) |
| 4513 | #define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) |
| 4514 | |
| 4515 | #define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) |
| 4516 | #define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) |
| 4517 | |
| 4518 | /* n=1,2,4,8,16 */ |
| 4519 | #define __lcd_set_bpp(n) \ |
| 4520 | ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) |
| 4521 | |
| 4522 | /* n=4,8,16 */ |
| 4523 | #define __lcd_set_burst_length(n) \ |
| 4524 | do { \ |
| 4525 | REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ |
| 4526 | REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ |
| 4527 | } while (0) |
| 4528 | |
| 4529 | #define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) |
| 4530 | #define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) |
| 4531 | |
| 4532 | #define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) |
| 4533 | #define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) |
| 4534 | |
| 4535 | /* n=2,4,16 */ |
| 4536 | #define __lcd_set_stn_frc(n) \ |
| 4537 | do { \ |
| 4538 | REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ |
| 4539 | REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ |
| 4540 | } while (0) |
| 4541 | |
| 4542 | |
| 4543 | #define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) |
| 4544 | #define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) |
| 4545 | |
| 4546 | #define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) |
| 4547 | #define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) |
| 4548 | |
| 4549 | #define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) |
| 4550 | #define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) |
| 4551 | |
| 4552 | #define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) |
| 4553 | #define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) |
| 4554 | |
| 4555 | #define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) |
| 4556 | #define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) |
| 4557 | |
| 4558 | #define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) |
| 4559 | #define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) |
| 4560 | |
| 4561 | #define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) |
| 4562 | #define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) |
| 4563 | |
| 4564 | #define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) |
| 4565 | #define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) |
| 4566 | |
| 4567 | #define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) |
| 4568 | #define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) |
| 4569 | |
| 4570 | |
| 4571 | /* LCD status register indication */ |
| 4572 | |
| 4573 | #define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) |
| 4574 | #define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) |
| 4575 | #define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) |
| 4576 | #define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) |
| 4577 | #define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) |
| 4578 | #define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) |
| 4579 | #define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) |
| 4580 | |
| 4581 | #define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) |
| 4582 | #define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) |
| 4583 | #define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) |
| 4584 | |
| 4585 | #define __lcd_panel_white() ( REG_LCD_DEV |= LCD_DEV_WHITE ) |
| 4586 | #define __lcd_panel_black() ( REG_LCD_DEV &= ~LCD_DEV_WHITE ) |
| 4587 | |
| 4588 | /* n=1,2,4,8 for single mono-STN |
| 4589 | * n=4,8 for dual mono-STN |
| 4590 | */ |
| 4591 | #define __lcd_set_panel_datawidth(n) \ |
| 4592 | do { \ |
| 4593 | REG_LCD_DEV &= ~LCD_DEV_PDW_MASK; \ |
| 4594 | REG_LCD_DEV |= LCD_DEV_PDW_n##; \ |
| 4595 | } while (0) |
| 4596 | |
| 4597 | /* m=LCD_DEV_MODE_GENERUIC_TFT_xxx */ |
| 4598 | #define __lcd_set_panel_mode(m) \ |
| 4599 | do { \ |
| 4600 | REG_LCD_DEV &= ~LCD_DEV_MODE_MASK; \ |
| 4601 | REG_LCD_DEV |= (m); \ |
| 4602 | } while(0) |
| 4603 | |
| 4604 | /* n = 0-255 */ |
| 4605 | #define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) |
| 4606 | #define __lcd_set_ac_bias(n) \ |
| 4607 | do { \ |
| 4608 | REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ |
| 4609 | REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ |
| 4610 | } while(0) |
| 4611 | |
| 4612 | #define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) |
| 4613 | #define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) |
| 4614 | |
| 4615 | #define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) |
| 4616 | #define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) |
| 4617 | |
| 4618 | #define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) |
| 4619 | #define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) |
| 4620 | |
| 4621 | #define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) |
| 4622 | #define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) |
| 4623 | |
| 4624 | #define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) |
| 4625 | #define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) |
| 4626 | |
| 4627 | #define __lcd_vsync_get_vps() \ |
| 4628 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) |
| 4629 | |
| 4630 | #define __lcd_vsync_get_vpe() \ |
| 4631 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) |
| 4632 | #define __lcd_vsync_set_vpe(n) \ |
| 4633 | do { \ |
| 4634 | REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ |
| 4635 | REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ |
| 4636 | } while (0) |
| 4637 | |
| 4638 | #define __lcd_hsync_get_hps() \ |
| 4639 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) |
| 4640 | #define __lcd_hsync_set_hps(n) \ |
| 4641 | do { \ |
| 4642 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ |
| 4643 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ |
| 4644 | } while (0) |
| 4645 | |
| 4646 | #define __lcd_hsync_get_hpe() \ |
| 4647 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) |
| 4648 | #define __lcd_hsync_set_hpe(n) \ |
| 4649 | do { \ |
| 4650 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ |
| 4651 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ |
| 4652 | } while (0) |
| 4653 | |
| 4654 | #define __lcd_vat_get_ht() \ |
| 4655 | ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) |
| 4656 | #define __lcd_vat_set_ht(n) \ |
| 4657 | do { \ |
| 4658 | REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ |
| 4659 | REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ |
| 4660 | } while (0) |
| 4661 | |
| 4662 | #define __lcd_vat_get_vt() \ |
| 4663 | ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) |
| 4664 | #define __lcd_vat_set_vt(n) \ |
| 4665 | do { \ |
| 4666 | REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ |
| 4667 | REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ |
| 4668 | } while (0) |
| 4669 | |
| 4670 | #define __lcd_dah_get_hds() \ |
| 4671 | ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) |
| 4672 | #define __lcd_dah_set_hds(n) \ |
| 4673 | do { \ |
| 4674 | REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ |
| 4675 | REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ |
| 4676 | } while (0) |
| 4677 | |
| 4678 | #define __lcd_dah_get_hde() \ |
| 4679 | ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) |
| 4680 | #define __lcd_dah_set_hde(n) \ |
| 4681 | do { \ |
| 4682 | REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ |
| 4683 | REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ |
| 4684 | } while (0) |
| 4685 | |
| 4686 | #define __lcd_dav_get_vds() \ |
| 4687 | ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) |
| 4688 | #define __lcd_dav_set_vds(n) \ |
| 4689 | do { \ |
| 4690 | REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ |
| 4691 | REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ |
| 4692 | } while (0) |
| 4693 | |
| 4694 | #define __lcd_dav_get_vde() \ |
| 4695 | ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) |
| 4696 | #define __lcd_dav_set_vde(n) \ |
| 4697 | do { \ |
| 4698 | REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ |
| 4699 | REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ |
| 4700 | } while (0) |
| 4701 | |
| 4702 | #define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) |
| 4703 | #define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) |
| 4704 | #define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) |
| 4705 | #define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) |
| 4706 | |
| 4707 | #define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) |
| 4708 | #define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) |
| 4709 | #define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) |
| 4710 | #define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) |
| 4711 | |
| 4712 | #define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) |
| 4713 | #define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) |
| 4714 | |
| 4715 | #define __lcd_cmd0_get_len() \ |
| 4716 | ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
| 4717 | #define __lcd_cmd1_get_len() \ |
| 4718 | ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) |
| 4719 | |
| 4720 | |
| 4721 | |
| 4722 | /*************************************************************************** |
| 4723 | * DES |
| 4724 | ***************************************************************************/ |
| 4725 | |
| 4726 | |
| 4727 | /*************************************************************************** |
| 4728 | * CPM |
| 4729 | ***************************************************************************/ |
| 4730 | #define __cpm_plcr1_fd() \ |
| 4731 | ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT) |
| 4732 | #define __cpm_plcr1_rd() \ |
| 4733 | ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT) |
| 4734 | #define __cpm_plcr1_od() \ |
| 4735 | ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT) |
| 4736 | #define __cpm_cfcr_mfr() \ |
| 4737 | ((REG_CPM_CFCR & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT) |
| 4738 | #define __cpm_cfcr_pfr() \ |
| 4739 | ((REG_CPM_CFCR & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT) |
| 4740 | #define __cpm_cfcr_sfr() \ |
| 4741 | ((REG_CPM_CFCR & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT) |
| 4742 | #define __cpm_cfcr_ifr() \ |
| 4743 | ((REG_CPM_CFCR & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT) |
| 4744 | |
| 4745 | static __inline__ unsigned int __cpm_divisor_encode(unsigned int n) |
| 4746 | { |
| 4747 | unsigned int encode[10] = {1,2,3,4,6,8,12,16,24,32}; |
| 4748 | int i; |
| 4749 | for (i=0;i<10;i++) |
| 4750 | if (n < encode[i]) |
| 4751 | break; |
| 4752 | return i; |
| 4753 | } |
| 4754 | |
| 4755 | #define __cpm_set_mclk_div(n) \ |
| 4756 | do { \ |
| 4757 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_MFR_MASK) | \ |
| 4758 | ((n) << (CPM_CFCR_MFR_BIT)); \ |
| 4759 | } while (0) |
| 4760 | |
| 4761 | #define __cpm_set_pclk_div(n) \ |
| 4762 | do { \ |
| 4763 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_PFR_MASK) | \ |
| 4764 | ((n) << (CPM_CFCR_PFR_BIT)); \ |
| 4765 | } while (0) |
| 4766 | |
| 4767 | #define __cpm_set_sclk_div(n) \ |
| 4768 | do { \ |
| 4769 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_SFR_MASK) | \ |
| 4770 | ((n) << (CPM_CFCR_SFR_BIT)); \ |
| 4771 | } while (0) |
| 4772 | |
| 4773 | #define __cpm_set_iclk_div(n) \ |
| 4774 | do { \ |
| 4775 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_IFR_MASK) | \ |
| 4776 | ((n) << (CPM_CFCR_IFR_BIT)); \ |
| 4777 | } while (0) |
| 4778 | |
| 4779 | #define __cpm_set_lcdclk_div(n) \ |
| 4780 | do { \ |
| 4781 | REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_LFR_MASK) | \ |
| 4782 | ((n) << (CPM_CFCR_LFR_BIT)); \ |
| 4783 | } while (0) |
| 4784 | |
| 4785 | #define __cpm_enable_cko1() (REG_CPM_CFCR |= CPM_CFCR_CKOEN1) |
| 4786 | #define __cpm_enable_cko2() (REG_CPM_CFCR |= CPM_CFCR_CKOEN2) |
| 4787 | #define __cpm_disable_cko1() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN1) |
| 4788 | #define __cpm_disable_cko2() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN2) |
| 4789 | |
| 4790 | #define __cpm_idle_mode() \ |
| 4791 | (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ |
| 4792 | CPM_LPCR_LPM_IDLE) |
| 4793 | #define __cpm_sleep_mode() \ |
| 4794 | (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ |
| 4795 | CPM_LPCR_LPM_SLEEP) |
| 4796 | #define __cpm_hibernate_mode() \ |
| 4797 | (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ |
| 4798 | CPM_LPCR_LPM_HIBERNATE) |
| 4799 | |
| 4800 | #define __cpm_stop_uart(n) \ |
| 4801 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_UART##n << CPM_MSCR_MSTP_BIT)) |
| 4802 | #define __cpm_stop_pwm(n) \ |
| 4803 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_PWM##n << CPM_MSCR_MSTP_BIT)) |
| 4804 | #define __cpm_stop_aic(n) \ |
| 4805 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_AIC##n << CPM_MSCR_MSTP_BIT)) |
| 4806 | #define __cpm_stop_ost() \ |
| 4807 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_OST << CPM_MSCR_MSTP_BIT)) |
| 4808 | #define __cpm_stop_rtc() \ |
| 4809 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_RTC << CPM_MSCR_MSTP_BIT)) |
| 4810 | #define __cpm_stop_dmac() \ |
| 4811 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_DMAC << CPM_MSCR_MSTP_BIT)) |
| 4812 | #define __cpm_stop_uhc() \ |
| 4813 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_UHC << CPM_MSCR_MSTP_BIT)) |
| 4814 | #define __cpm_stop_lcd() \ |
| 4815 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_LCD << CPM_MSCR_MSTP_BIT)) |
| 4816 | #define __cpm_stop_i2c() \ |
| 4817 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_I2C << CPM_MSCR_MSTP_BIT)) |
| 4818 | #define __cpm_stop_ssi() \ |
| 4819 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_SSI << CPM_MSCR_MSTP_BIT)) |
| 4820 | #define __cpm_stop_msc() \ |
| 4821 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_MSC << CPM_MSCR_MSTP_BIT)) |
| 4822 | #define __cpm_stop_scc() \ |
| 4823 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_SCC << CPM_MSCR_MSTP_BIT)) |
| 4824 | #define __cpm_stop_fir() \ |
| 4825 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_FIR << CPM_MSCR_MSTP_BIT)) |
| 4826 | #define __cpm_stop_des() \ |
| 4827 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_DES << CPM_MSCR_MSTP_BIT)) |
| 4828 | #define __cpm_stop_eth() \ |
| 4829 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_eth << CPM_MSCR_MSTP_BIT)) |
| 4830 | #define __cpm_stop_ps2() \ |
| 4831 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_PS2 << CPM_MSCR_MSTP_BIT)) |
| 4832 | #define __cpm_stop_cim() \ |
| 4833 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_CIM << CPM_MSCR_MSTP_BIT)) |
| 4834 | #define __cpm_stop_udc() \ |
| 4835 | (REG_CPM_MSCR |= (CPM_MSCR_MSTP_UDC << CPM_MSCR_MSTP_BIT)) |
| 4836 | #define __cpm_stop_all() (REG_CPM_MSCR = 0xffffffff) |
| 4837 | |
| 4838 | #define __cpm_start_uart(n) \ |
| 4839 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_UART##n << CPM_MSCR_MSTP_BIT)) |
| 4840 | #define __cpm_start_pwm(n) \ |
| 4841 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_PWM##n << CPM_MSCR_MSTP_BIT)) |
| 4842 | #define __cpm_start_aic(n) \ |
| 4843 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_AIC##n << CPM_MSCR_MSTP_BIT)) |
| 4844 | #define __cpm_start_ost() \ |
| 4845 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_OST << CPM_MSCR_MSTP_BIT)) |
| 4846 | #define __cpm_start_rtc() \ |
| 4847 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_RTC << CPM_MSCR_MSTP_BIT)) |
| 4848 | #define __cpm_start_dmac() \ |
| 4849 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_DMAC << CPM_MSCR_MSTP_BIT)) |
| 4850 | #define __cpm_start_uhc() \ |
| 4851 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_UHC << CPM_MSCR_MSTP_BIT)) |
| 4852 | #define __cpm_start_lcd() \ |
| 4853 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_LCD << CPM_MSCR_MSTP_BIT)) |
| 4854 | #define __cpm_start_i2c() \ |
| 4855 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_I2C << CPM_MSCR_MSTP_BIT)) |
| 4856 | #define __cpm_start_ssi() \ |
| 4857 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_SSI << CPM_MSCR_MSTP_BIT)) |
| 4858 | #define __cpm_start_msc() \ |
| 4859 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_MSC << CPM_MSCR_MSTP_BIT)) |
| 4860 | #define __cpm_start_scc() \ |
| 4861 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_SCC << CPM_MSCR_MSTP_BIT)) |
| 4862 | #define __cpm_start_fir() \ |
| 4863 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_FIR << CPM_MSCR_MSTP_BIT)) |
| 4864 | #define __cpm_start_des() \ |
| 4865 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_DES << CPM_MSCR_MSTP_BIT)) |
| 4866 | #define __cpm_start_eth() \ |
| 4867 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_ETH << CPM_MSCR_MSTP_BIT)) |
| 4868 | #define __cpm_start_ps2() \ |
| 4869 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_PS2 << CPM_MSCR_MSTP_BIT)) |
| 4870 | #define __cpm_start_cim() \ |
| 4871 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_CIM << CPM_MSCR_MSTP_BIT)) |
| 4872 | #define __cpm_start_udc() \ |
| 4873 | (REG_CPM_MSCR &= ~(CPM_MSCR_MSTP_UDC << CPM_MSCR_MSTP_BIT)) |
| 4874 | #define __cpm_start_all() (REG_CPM_MSCR = 0x00000000) |
| 4875 | |
| 4876 | |
| 4877 | /*************************************************************************** |
| 4878 | * SSI |
| 4879 | ***************************************************************************/ |
| 4880 | |
| 4881 | #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) |
| 4882 | #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) |
| 4883 | #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) |
| 4884 | |
| 4885 | #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) |
| 4886 | |
| 4887 | #define __ssi_select_ce2() \ |
| 4888 | do { \ |
| 4889 | REG_SSI_CR0 |= SSI_CR0_FSEL; \ |
| 4890 | REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ |
| 4891 | } while (0) |
| 4892 | |
| 4893 | #define __ssi_select_gpc() \ |
| 4894 | do { \ |
| 4895 | REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ |
| 4896 | REG_SSI_CR1 |= SSI_CR1_MULTS; \ |
| 4897 | } while (0) |
| 4898 | |
| 4899 | #define __ssi_enable_tx_intr() \ |
| 4900 | ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) |
| 4901 | |
| 4902 | #define __ssi_disable_tx_intr() \ |
| 4903 | ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) |
| 4904 | |
| 4905 | #define __ssi_enable_rx_intr() \ |
| 4906 | ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) |
| 4907 | |
| 4908 | #define __ssi_disable_rx_intr() \ |
| 4909 | ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) |
| 4910 | |
| 4911 | #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) |
| 4912 | #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) |
| 4913 | |
| 4914 | #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) |
| 4915 | #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) |
| 4916 | |
| 4917 | #define __ssi_finish_receive() \ |
| 4918 | ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
| 4919 | |
| 4920 | #define __ssi_disable_recvfinish() \ |
| 4921 | ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) |
| 4922 | |
| 4923 | #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) |
| 4924 | #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) |
| 4925 | |
| 4926 | #define __ssi_flush_fifo() \ |
| 4927 | ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) |
| 4928 | |
| 4929 | #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) |
| 4930 | |
| 4931 | /* Motorola's SPI format, set 1 delay */ |
| 4932 | #define __ssi_spi_format() \ |
| 4933 | do { \ |
| 4934 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ |
| 4935 | REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ |
| 4936 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ |
| 4937 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ |
| 4938 | } while (0) |
| 4939 | |
| 4940 | /* TI's SSP format, must clear SSI_CR1.UNFIN */ |
| 4941 | #define __ssi_ssp_format() \ |
| 4942 | do { \ |
| 4943 | REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ |
| 4944 | REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ |
| 4945 | } while (0) |
| 4946 | |
| 4947 | /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ |
| 4948 | #define __ssi_microwire_format() \ |
| 4949 | do { \ |
| 4950 | REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ |
| 4951 | REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ |
| 4952 | REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ |
| 4953 | REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ |
| 4954 | REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ |
| 4955 | } while (0) |
| 4956 | |
| 4957 | /* CE# level (FRMHL), CE# in interval time (ITFRM), |
| 4958 | clock phase and polarity (PHA POL), |
| 4959 | interval time (SSIITR), interval characters/frame (SSIICR) */ |
| 4960 | |
| 4961 | /* frmhl,endian,mcom,flen,pha,pol MASK */ |
| 4962 | #define SSICR1_MISC_MASK \ |
| 4963 | ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ |
| 4964 | | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ |
| 4965 | |
| 4966 | #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ |
| 4967 | do { \ |
| 4968 | REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ |
| 4969 | REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ |
| 4970 | (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ |
| 4971 | ((pha) << 1) | (pol); \ |
| 4972 | } while(0) |
| 4973 | |
| 4974 | /* Transfer with MSB or LSB first */ |
| 4975 | #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) |
| 4976 | #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) |
| 4977 | |
| 4978 | /* n = 2 - 17 */ |
| 4979 | #define __ssi_set_frame_length(n) \ |
| 4980 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | SSI_CR1_FLEN_##n##BIT) ) |
| 4981 | |
| 4982 | /* n = 1 - 16 */ |
| 4983 | #define __ssi_set_microwire_command_length(n) \ |
| 4984 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) |
| 4985 | |
| 4986 | /* Set the clock phase for SPI */ |
| 4987 | #define __ssi_set_spi_clock_phase(n) \ |
| 4988 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) |
| 4989 | |
| 4990 | /* Set the clock polarity for SPI */ |
| 4991 | #define __ssi_set_spi_clock_polarity(n) \ |
| 4992 | ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) |
| 4993 | |
| 4994 | /* n = 1,4,8,14 */ |
| 4995 | #define __ssi_set_tx_trigger(n) \ |
| 4996 | do { \ |
| 4997 | REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ |
| 4998 | REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ |
| 4999 | } while (0) |
| 5000 | |
| 5001 | /* n = 1,4,8,14 */ |
| 5002 | #define __ssi_set_rx_trigger(n) \ |
| 5003 | do { \ |
| 5004 | REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ |
| 5005 | REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ |
| 5006 | } while (0) |
| 5007 | |
| 5008 | #define __ssi_get_txfifo_count() \ |
| 5009 | ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) |
| 5010 | |
| 5011 | #define __ssi_get_rxfifo_count() \ |
| 5012 | ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) |
| 5013 | |
| 5014 | #define __ssi_clear_errors() \ |
| 5015 | ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) |
| 5016 | |
| 5017 | #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) |
| 5018 | #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) |
| 5019 | |
| 5020 | #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) |
| 5021 | #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) |
| 5022 | #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) |
| 5023 | |
| 5024 | #define __ssi_set_clk(dev_clk, ssi_clk) \ |
| 5025 | ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) |
| 5026 | |
| 5027 | #define __ssi_receive_data() REG_SSI_DR |
| 5028 | #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) |
| 5029 | |
| 5030 | /* |
| 5031 | * CPU clocks |
| 5032 | */ |
| 5033 | #ifdef CFG_EXTAL |
| 5034 | #define JZ_EXTAL CFG_EXTAL |
| 5035 | #else |
| 5036 | #define JZ_EXTAL 3686400 |
| 5037 | #endif |
| 5038 | #define JZ_EXTAL2 32768 /* RTC clock */ |
| 5039 | |
| 5040 | static __inline__ unsigned int __cpm_get_pllout(void) |
| 5041 | { |
| 5042 | unsigned int nf, nr, no, pllout; |
| 5043 | unsigned long plcr = REG_CPM_PLCR1; |
| 5044 | unsigned long od[4] = {1, 2, 2, 4}; |
| 5045 | if (plcr & CPM_PLCR1_PLL1EN) { |
| 5046 | nf = (plcr & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT; |
| 5047 | nr = (plcr & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT; |
| 5048 | no = od[((plcr & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)]; |
| 5049 | pllout = (JZ_EXTAL) / ((nr+2) * no) * (nf+2); |
| 5050 | } else |
| 5051 | pllout = JZ_EXTAL; |
| 5052 | return pllout; |
| 5053 | } |
| 5054 | |
| 5055 | static __inline__ unsigned int __cpm_get_iclk(void) |
| 5056 | { |
| 5057 | unsigned int iclk; |
| 5058 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| 5059 | unsigned long cfcr = REG_CPM_CFCR; |
| 5060 | unsigned long plcr = REG_CPM_PLCR1; |
| 5061 | if (plcr & CPM_PLCR1_PLL1EN) |
| 5062 | iclk = __cpm_get_pllout() / |
| 5063 | div[(cfcr & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT]; |
| 5064 | else |
| 5065 | iclk = JZ_EXTAL; |
| 5066 | return iclk; |
| 5067 | } |
| 5068 | |
| 5069 | static __inline__ unsigned int __cpm_get_sclk(void) |
| 5070 | { |
| 5071 | unsigned int sclk; |
| 5072 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| 5073 | unsigned long cfcr = REG_CPM_CFCR; |
| 5074 | unsigned long plcr = REG_CPM_PLCR1; |
| 5075 | if (plcr & CPM_PLCR1_PLL1EN) |
| 5076 | sclk = __cpm_get_pllout() / |
| 5077 | div[(cfcr & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT]; |
| 5078 | else |
| 5079 | sclk = JZ_EXTAL; |
| 5080 | return sclk; |
| 5081 | } |
| 5082 | |
| 5083 | static __inline__ unsigned int __cpm_get_mclk(void) |
| 5084 | { |
| 5085 | unsigned int mclk; |
| 5086 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| 5087 | unsigned long cfcr = REG_CPM_CFCR; |
| 5088 | unsigned long plcr = REG_CPM_PLCR1; |
| 5089 | if (plcr & CPM_PLCR1_PLL1EN) |
| 5090 | mclk = __cpm_get_pllout() / |
| 5091 | div[(cfcr & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT]; |
| 5092 | else |
| 5093 | mclk = JZ_EXTAL; |
| 5094 | return mclk; |
| 5095 | } |
| 5096 | |
| 5097 | static __inline__ unsigned int __cpm_get_devclk(void) |
| 5098 | { |
| 5099 | unsigned int devclk; |
| 5100 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
| 5101 | unsigned long cfcr = REG_CPM_CFCR; |
| 5102 | unsigned long plcr = REG_CPM_PLCR1; |
| 5103 | if (plcr & CPM_PLCR1_PLL1EN) |
| 5104 | devclk = __cpm_get_pllout() / |
| 5105 | div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT]; |
| 5106 | else |
| 5107 | devclk = JZ_EXTAL; |
| 5108 | return devclk; |
| 5109 | } |
| 5110 | |
| 5111 | #endif /* !__ASSEMBLY__ */ |
| 5112 | |
| 5113 | #endif /* __JZ4730_H__ */ |
| 5114 | |
