Root/qiboot/include/glamo-regs.h

1#ifndef _GLAMO_REGS_H
2#define _GLAMO_REGS_H
3
4/* Smedia Glamo 336x/337x driver
5 *
6 * (C) 2007 by OpenMoko, Inc.
7 * Author: Harald Welte <laforge@openmoko.org>
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26enum glamo_regster_offsets {
27    GLAMO_REGOFS_GENERIC = 0x0000,
28    GLAMO_REGOFS_HOSTBUS = 0x0200,
29    GLAMO_REGOFS_MEMORY = 0x0300,
30    GLAMO_REGOFS_VIDCAP = 0x0400,
31    GLAMO_REGOFS_ISP = 0x0500,
32    GLAMO_REGOFS_JPEG = 0x0800,
33    GLAMO_REGOFS_MPEG = 0x0c00,
34    GLAMO_REGOFS_LCD = 0x1100,
35    GLAMO_REGOFS_MMC = 0x1400,
36    GLAMO_REGOFS_MPROC0 = 0x1500,
37    GLAMO_REGOFS_MPROC1 = 0x1580,
38    GLAMO_REGOFS_CMDQUEUE = 0x1600,
39    GLAMO_REGOFS_RISC = 0x1680,
40    GLAMO_REGOFS_2D = 0x1700,
41    GLAMO_REGOFS_3D = 0x1b00,
42    GLAMO_REGOFS_END = 0x2400,
43};
44
45
46enum glamo_register_generic {
47    GLAMO_REG_GCONF1 = 0x0000,
48    GLAMO_REG_GCONF2 = 0x0002,
49#define GLAMO_REG_DEVICE_ID GLAMO_REG_GCONF2
50    GLAMO_REG_GCONF3 = 0x0004,
51#define GLAMO_REG_REVISION_ID GLAMO_REG_GCONF3
52    GLAMO_REG_IRQ_GEN1 = 0x0006,
53#define GLAMO_REG_IRQ_ENABLE GLAMO_REG_IRQ_GEN1
54    GLAMO_REG_IRQ_GEN2 = 0x0008,
55#define GLAMO_REG_IRQ_SET GLAMO_REG_IRQ_GEN2
56    GLAMO_REG_IRQ_GEN3 = 0x000a,
57#define GLAMO_REG_IRQ_CLEAR GLAMO_REG_IRQ_GEN3
58    GLAMO_REG_IRQ_GEN4 = 0x000c,
59#define GLAMO_REG_IRQ_STATUS GLAMO_REG_IRQ_GEN4
60    GLAMO_REG_CLOCK_HOST = 0x0010,
61    GLAMO_REG_CLOCK_MEMORY = 0x0012,
62    GLAMO_REG_CLOCK_LCD = 0x0014,
63    GLAMO_REG_CLOCK_MMC = 0x0016,
64    GLAMO_REG_CLOCK_ISP = 0x0018,
65    GLAMO_REG_CLOCK_JPEG = 0x001a,
66    GLAMO_REG_CLOCK_3D = 0x001c,
67    GLAMO_REG_CLOCK_2D = 0x001e,
68    GLAMO_REG_CLOCK_RISC1 = 0x0020, /* 3365 only? */
69    GLAMO_REG_CLOCK_RISC2 = 0x0022, /* 3365 only? */
70    GLAMO_REG_CLOCK_MPEG = 0x0024,
71    GLAMO_REG_CLOCK_MPROC = 0x0026,
72
73    GLAMO_REG_CLOCK_GEN5_1 = 0x0030,
74    GLAMO_REG_CLOCK_GEN5_2 = 0x0032,
75    GLAMO_REG_CLOCK_GEN6 = 0x0034,
76    GLAMO_REG_CLOCK_GEN7 = 0x0036,
77    GLAMO_REG_CLOCK_GEN8 = 0x0038,
78    GLAMO_REG_CLOCK_GEN9 = 0x003a,
79    GLAMO_REG_CLOCK_GEN10 = 0x003c,
80    GLAMO_REG_CLOCK_GEN11 = 0x003e,
81    GLAMO_REG_PLL_GEN1 = 0x0040,
82    GLAMO_REG_PLL_GEN2 = 0x0042,
83    GLAMO_REG_PLL_GEN3 = 0x0044,
84    GLAMO_REG_PLL_GEN4 = 0x0046,
85    GLAMO_REG_PLL_GEN5 = 0x0048,
86    GLAMO_REG_GPIO_GEN1 = 0x0050,
87    GLAMO_REG_GPIO_GEN2 = 0x0052,
88    GLAMO_REG_GPIO_GEN3 = 0x0054,
89    GLAMO_REG_GPIO_GEN4 = 0x0056,
90    GLAMO_REG_GPIO_GEN5 = 0x0058,
91    GLAMO_REG_GPIO_GEN6 = 0x005a,
92    GLAMO_REG_GPIO_GEN7 = 0x005c,
93    GLAMO_REG_GPIO_GEN8 = 0x005e,
94    GLAMO_REG_GPIO_GEN9 = 0x0060,
95    GLAMO_REG_GPIO_GEN10 = 0x0062,
96    GLAMO_REG_DFT_GEN1 = 0x0070,
97    GLAMO_REG_DFT_GEN2 = 0x0072,
98    GLAMO_REG_DFT_GEN3 = 0x0074,
99    GLAMO_REG_DFT_GEN4 = 0x0076,
100
101        GLAMO_REG_PLL_GEN6 = 0x01e0,
102        GLAMO_REG_PLL_GEN7 = 0x01f0,
103};
104
105#define GLAMO_REG_HOSTBUS(x) (GLAMO_REGOFS_HOSTBUS-2+(x*2))
106
107#define REG_MEM(x) (GLAMO_REGOFS_MEMORY+(x))
108#define GLAMO_REG_MEM_TIMING(x) (GLAMO_REG_MEM_TIMING1-2+(x*2))
109
110enum glamo_register_mem {
111    GLAMO_REG_MEM_TYPE = REG_MEM(0x00),
112    GLAMO_REG_MEM_GEN = REG_MEM(0x02),
113    GLAMO_REG_MEM_TIMING1 = REG_MEM(0x04),
114    GLAMO_REG_MEM_TIMING2 = REG_MEM(0x06),
115    GLAMO_REG_MEM_TIMING3 = REG_MEM(0x08),
116    GLAMO_REG_MEM_TIMING4 = REG_MEM(0x0a),
117    GLAMO_REG_MEM_TIMING5 = REG_MEM(0x0c),
118    GLAMO_REG_MEM_TIMING6 = REG_MEM(0x0e),
119    GLAMO_REG_MEM_TIMING7 = REG_MEM(0x10),
120    GLAMO_REG_MEM_TIMING8 = REG_MEM(0x12),
121    GLAMO_REG_MEM_TIMING9 = REG_MEM(0x14),
122    GLAMO_REG_MEM_TIMING10 = REG_MEM(0x16),
123    GLAMO_REG_MEM_TIMING11 = REG_MEM(0x18),
124    GLAMO_REG_MEM_POWER1 = REG_MEM(0x1a),
125    GLAMO_REG_MEM_POWER2 = REG_MEM(0x1c),
126    GLAMO_REG_MEM_LCD_BUF1 = REG_MEM(0x1e),
127    GLAMO_REG_MEM_LCD_BUF2 = REG_MEM(0x20),
128    GLAMO_REG_MEM_LCD_BUF3 = REG_MEM(0x22),
129    GLAMO_REG_MEM_LCD_BUF4 = REG_MEM(0x24),
130    GLAMO_REG_MEM_BIST1 = REG_MEM(0x26),
131    GLAMO_REG_MEM_BIST2 = REG_MEM(0x28),
132    GLAMO_REG_MEM_BIST3 = REG_MEM(0x2a),
133    GLAMO_REG_MEM_BIST4 = REG_MEM(0x2c),
134    GLAMO_REG_MEM_BIST5 = REG_MEM(0x2e),
135    GLAMO_REG_MEM_MAH1 = REG_MEM(0x30),
136    GLAMO_REG_MEM_MAH2 = REG_MEM(0x32),
137    GLAMO_REG_MEM_DRAM1 = REG_MEM(0x34),
138    GLAMO_REG_MEM_DRAM2 = REG_MEM(0x36),
139    GLAMO_REG_MEM_CRC = REG_MEM(0x38),
140};
141
142#define GLAMO_MEM_TYPE_MASK 0x03
143
144enum glamo_reg_mem_dram1 {
145    GLAMO_MEM_DRAM1_EN_SDRAM_CLK = (1 << 11),
146    GLAMO_MEM_DRAM1_SELF_REFRESH = (1 << 12),
147};
148
149enum glamo_reg_mem_dram2 {
150    GLAMO_MEM_DRAM2_DEEP_PWRDOWN = (1 << 12),
151};
152
153enum glamo_irq_index {
154    GLAMO_IRQIDX_HOSTBUS = 0,
155    GLAMO_IRQIDX_JPEG = 1,
156    GLAMO_IRQIDX_MPEG = 2,
157    GLAMO_IRQIDX_MPROC1 = 3,
158    GLAMO_IRQIDX_MPROC0 = 4,
159    GLAMO_IRQIDX_CMDQUEUE = 5,
160    GLAMO_IRQIDX_2D = 6,
161    GLAMO_IRQIDX_MMC = 7,
162    GLAMO_IRQIDX_RISC = 8,
163};
164
165enum glamo_irq {
166    GLAMO_IRQ_HOSTBUS = (1 << GLAMO_IRQIDX_HOSTBUS),
167    GLAMO_IRQ_JPEG = (1 << GLAMO_IRQIDX_JPEG),
168    GLAMO_IRQ_MPEG = (1 << GLAMO_IRQIDX_MPEG),
169    GLAMO_IRQ_MPROC1 = (1 << GLAMO_IRQIDX_MPROC1),
170    GLAMO_IRQ_MPROC0 = (1 << GLAMO_IRQIDX_MPROC0),
171    GLAMO_IRQ_CMDQUEUE = (1 << GLAMO_IRQIDX_CMDQUEUE),
172    GLAMO_IRQ_2D = (1 << GLAMO_IRQIDX_2D),
173    GLAMO_IRQ_MMC = (1 << GLAMO_IRQIDX_MMC),
174    GLAMO_IRQ_RISC = (1 << GLAMO_IRQIDX_RISC),
175};
176
177enum glamo_reg_clock_host {
178    GLAMO_CLOCK_HOST_DG_BCLK = 0x0001,
179    GLAMO_CLOCK_HOST_DG_M0CLK = 0x0004,
180    GLAMO_CLOCK_HOST_RESET = 0x1000,
181};
182
183enum glamo_reg_clock_mem {
184    GLAMO_CLOCK_MEM_DG_M1CLK = 0x0001,
185    GLAMO_CLOCK_MEM_EN_M1CLK = 0x0002,
186    GLAMO_CLOCK_MEM_DG_MOCACLK = 0x0004,
187    GLAMO_CLOCK_MEM_EN_MOCACLK = 0x0008,
188    GLAMO_CLOCK_MEM_RESET = 0x1000,
189    GLAMO_CLOCK_MOCA_RESET = 0x2000,
190};
191
192enum glamo_reg_clock_lcd {
193    GLAMO_CLOCK_LCD_DG_DCLK = 0x0001,
194    GLAMO_CLOCK_LCD_EN_DCLK = 0x0002,
195    GLAMO_CLOCK_LCD_DG_DMCLK = 0x0004,
196    GLAMO_CLOCK_LCD_EN_DMCLK = 0x0008,
197    //
198    GLAMO_CLOCK_LCD_EN_DHCLK = 0x0020,
199    GLAMO_CLOCK_LCD_DG_M5CLK = 0x0040,
200    GLAMO_CLOCK_LCD_EN_M5CLK = 0x0080,
201    GLAMO_CLOCK_LCD_RESET = 0x1000,
202};
203
204enum glamo_reg_clock_mmc {
205    GLAMO_CLOCK_MMC_DG_TCLK = 0x0001,
206    GLAMO_CLOCK_MMC_EN_TCLK = 0x0002,
207    GLAMO_CLOCK_MMC_DG_M9CLK = 0x0004,
208    GLAMO_CLOCK_MMC_EN_M9CLK = 0x0008,
209    GLAMO_CLOCK_MMC_RESET = 0x1000,
210};
211
212enum glamo_reg_basic_mmc {
213    /* set to disable CRC error rejection */
214    GLAMO_BASIC_MMC_DISABLE_CRC = 0x0001,
215    /* enable completion interrupt */
216    GLAMO_BASIC_MMC_EN_COMPL_INT = 0x0002,
217    /* stop MMC clock while enforced idle waiting for data from card */
218    GLAMO_BASIC_MMC_NO_CLK_RD_WAIT = 0x0004,
219    /* 0 = 1-bit bus to card, 1 = use 4-bit bus (has to be negotiated) */
220    GLAMO_BASIC_MMC_EN_4BIT_DATA = 0x0008,
221    /* enable 75K pullups on D3..D0 */
222    GLAMO_BASIC_MMC_EN_DATA_PUPS = 0x0010,
223    /* enable 75K pullup on CMD */
224    GLAMO_BASIC_MMC_EN_CMD_PUP = 0x0020,
225    /* IO drive strength 00=weak -> 11=strongest */
226    GLAMO_BASIC_MMC_EN_DR_STR0 = 0x0040,
227    GLAMO_BASIC_MMC_EN_DR_STR1 = 0x0080,
228    /* TCLK delay stage A, 0000 = 500ps --> 1111 = 8ns */
229    GLAMO_BASIC_MMC_EN_TCLK_DLYA0 = 0x0100,
230    GLAMO_BASIC_MMC_EN_TCLK_DLYA1 = 0x0200,
231    GLAMO_BASIC_MMC_EN_TCLK_DLYA2 = 0x0400,
232    GLAMO_BASIC_MMC_EN_TCLK_DLYA3 = 0x0800,
233    /* TCLK delay stage B (cumulative), 0000 = 500ps --> 1111 = 8ns */
234    GLAMO_BASIC_MMC_EN_TCLK_DLYB0 = 0x1000,
235    GLAMO_BASIC_MMC_EN_TCLK_DLYB1 = 0x2000,
236    GLAMO_BASIC_MMC_EN_TCLK_DLYB2 = 0x4000,
237    GLAMO_BASIC_MMC_EN_TCLK_DLYB3 = 0x8000,
238};
239
240enum glamo_reg_stat1_mmc {
241    /* command "counter" (really: toggle) */
242    GLAMO_STAT1_MMC_CMD_CTR = 0x8000,
243    /* engine is idle */
244    GLAMO_STAT1_MMC_IDLE = 0x4000,
245    /* readback response is ready */
246    GLAMO_STAT1_MMC_RB_RRDY = 0x0200,
247    /* readback data is ready */
248    GLAMO_STAT1_MMC_RB_DRDY = 0x0100,
249    /* no response timeout */
250    GLAMO_STAT1_MMC_RTOUT = 0x0020,
251    /* no data timeout */
252    GLAMO_STAT1_MMC_DTOUT = 0x0010,
253    /* CRC error on block write */
254    GLAMO_STAT1_MMC_BWERR = 0x0004,
255    /* CRC error on block read */
256    GLAMO_STAT1_MMC_BRERR = 0x0002
257};
258
259enum glamo_reg_fire_mmc {
260    /* command "counter" (really: toggle)
261     * the STAT1 register reflects this so you can ensure you don't look
262     * at status for previous command
263     */
264    GLAMO_FIRE_MMC_CMD_CTR = 0x8000,
265    /* sets kind of response expected */
266    GLAMO_FIRE_MMC_RES_MASK = 0x0700,
267    /* sets command type */
268    GLAMO_FIRE_MMC_TYP_MASK = 0x00C0,
269    /* sets command class */
270    GLAMO_FIRE_MMC_CLS_MASK = 0x000F,
271};
272
273enum glamo_fire_mmc_response_types {
274    GLAMO_FIRE_MMC_RSPT_R1 = 0x0000,
275    GLAMO_FIRE_MMC_RSPT_R1b = 0x0100,
276    GLAMO_FIRE_MMC_RSPT_R2 = 0x0200,
277    GLAMO_FIRE_MMC_RSPT_R3 = 0x0300,
278    GLAMO_FIRE_MMC_RSPT_R4 = 0x0400,
279    GLAMO_FIRE_MMC_RSPT_R5 = 0x0500,
280};
281
282enum glamo_fire_mmc_command_types {
283    /* broadcast, no response */
284    GLAMO_FIRE_MMC_CMDT_BNR = 0x0000,
285    /* broadcast, with response */
286    GLAMO_FIRE_MMC_CMDT_BR = 0x0040,
287    /* addressed, no data */
288    GLAMO_FIRE_MMC_CMDT_AND = 0x0080,
289    /* addressed, with data */
290    GLAMO_FIRE_MMC_CMDT_AD = 0x00C0,
291};
292
293enum glamo_fire_mmc_command_class {
294    /* "Stream Read" */
295    GLAMO_FIRE_MMC_CC_STRR = 0x0000,
296    /* Single Block Read */
297    GLAMO_FIRE_MMC_CC_SBR = 0x0001,
298    /* Multiple Block Read With Stop */
299    GLAMO_FIRE_MMC_CC_MBRS = 0x0002,
300    /* Multiple Block Read No Stop */
301    GLAMO_FIRE_MMC_CC_MBRNS = 0x0003,
302    /* RESERVED for "Stream Write" */
303    GLAMO_FIRE_MMC_CC_STRW = 0x0004,
304    /* "Stream Write" */
305    GLAMO_FIRE_MMC_CC_SBW = 0x0005,
306    /* RESERVED for Multiple Block Write With Stop */
307    GLAMO_FIRE_MMC_CC_MBWS = 0x0006,
308    /* Multiple Block Write No Stop */
309    GLAMO_FIRE_MMC_CC_MBWNS = 0x0007,
310    /* STOP command */
311    GLAMO_FIRE_MMC_CC_STOP = 0x0008,
312    /* Cancel on Running Command */
313    GLAMO_FIRE_MMC_CC_CANCL = 0x0009,
314    /* "Basic Command" */
315    GLAMO_FIRE_MMC_CC_BASIC = 0x000a,
316};
317
318/* these are offsets from the start of the MMC register region */
319enum glamo_register_mmc {
320    /* MMC command, b15..8 = cmd arg b7..0; b7..1 = CRC; b0 = end bit */
321    GLAMO_REG_MMC_CMD_REG1 = 0x00,
322    /* MMC command, b15..0 = cmd arg b23 .. 8 */
323    GLAMO_REG_MMC_CMD_REG2 = 0x02,
324    /* MMC command, b15=start, b14=transmission,
325     * b13..8=cmd idx, b7..0=cmd arg b31..24
326     */
327    GLAMO_REG_MMC_CMD_REG3 = 0x04,
328    GLAMO_REG_MMC_CMD_FIRE = 0x06,
329    GLAMO_REG_MMC_CMD_RSP1 = 0x10,
330    GLAMO_REG_MMC_CMD_RSP2 = 0x12,
331    GLAMO_REG_MMC_CMD_RSP3 = 0x14,
332    GLAMO_REG_MMC_CMD_RSP4 = 0x16,
333    GLAMO_REG_MMC_CMD_RSP5 = 0x18,
334    GLAMO_REG_MMC_CMD_RSP6 = 0x1a,
335    GLAMO_REG_MMC_CMD_RSP7 = 0x1c,
336    GLAMO_REG_MMC_CMD_RSP8 = 0x1e,
337    GLAMO_REG_MMC_RB_STAT1 = 0x20,
338    GLAMO_REG_MMC_RB_BLKCNT = 0x22,
339    GLAMO_REG_MMC_RB_BLKLEN = 0x24,
340    GLAMO_REG_MMC_BASIC = 0x30,
341    GLAMO_REG_MMC_RDATADS1 = 0x34,
342    GLAMO_REG_MMC_RDATADS2 = 0x36,
343    GLAMO_REG_MMC_WDATADS1 = 0x38,
344    GLAMO_REG_MMC_WDATADS2 = 0x3a,
345    GLAMO_REG_MMC_DATBLKCNT = 0x3c,
346    GLAMO_REG_MMC_DATBLKLEN = 0x3e,
347    GLAMO_REG_MMC_TIMEOUT = 0x40,
348
349};
350
351enum glamo_reg_clock_isp {
352    GLAMO_CLOCK_ISP_DG_I1CLK = 0x0001,
353    GLAMO_CLOCK_ISP_EN_I1CLK = 0x0002,
354    GLAMO_CLOCK_ISP_DG_CCLK = 0x0004,
355    GLAMO_CLOCK_ISP_EN_CCLK = 0x0008,
356    //
357    GLAMO_CLOCK_ISP_EN_SCLK = 0x0020,
358    GLAMO_CLOCK_ISP_DG_M2CLK = 0x0040,
359    GLAMO_CLOCK_ISP_EN_M2CLK = 0x0080,
360    GLAMO_CLOCK_ISP_DG_M15CLK = 0x0100,
361    GLAMO_CLOCK_ISP_EN_M15CLK = 0x0200,
362    GLAMO_CLOCK_ISP1_RESET = 0x1000,
363    GLAMO_CLOCK_ISP2_RESET = 0x2000,
364};
365
366enum glamo_reg_clock_jpeg {
367    GLAMO_CLOCK_JPEG_DG_JCLK = 0x0001,
368    GLAMO_CLOCK_JPEG_EN_JCLK = 0x0002,
369    GLAMO_CLOCK_JPEG_DG_M3CLK = 0x0004,
370    GLAMO_CLOCK_JPEG_EN_M3CLK = 0x0008,
371    GLAMO_CLOCK_JPEG_RESET = 0x1000,
372};
373
374enum glamo_reg_clock_2d {
375    GLAMO_CLOCK_2D_DG_GCLK = 0x0001,
376    GLAMO_CLOCK_2D_EN_GCLK = 0x0002,
377    GLAMO_CLOCK_2D_DG_M7CLK = 0x0004,
378    GLAMO_CLOCK_2D_EN_M7CLK = 0x0008,
379    GLAMO_CLOCK_2D_DG_M6CLK = 0x0010,
380    GLAMO_CLOCK_2D_EN_M6CLK = 0x0020,
381    GLAMO_CLOCK_2D_RESET = 0x1000,
382    GLAMO_CLOCK_2D_CQ_RESET = 0x2000,
383};
384
385enum glamo_reg_clock_3d {
386    GLAMO_CLOCK_3D_DG_ECLK = 0x0001,
387    GLAMO_CLOCK_3D_EN_ECLK = 0x0002,
388    GLAMO_CLOCK_3D_DG_RCLK = 0x0004,
389    GLAMO_CLOCK_3D_EN_RCLK = 0x0008,
390    GLAMO_CLOCK_3D_DG_M8CLK = 0x0010,
391    GLAMO_CLOCK_3D_EN_M8CLK = 0x0020,
392    GLAMO_CLOCK_3D_BACK_RESET = 0x1000,
393    GLAMO_CLOCK_3D_FRONT_RESET = 0x2000,
394};
395
396enum glamo_reg_clock_mpeg {
397    GLAMO_CLOCK_MPEG_DG_X0CLK = 0x0001,
398    GLAMO_CLOCK_MPEG_EN_X0CLK = 0x0002,
399    GLAMO_CLOCK_MPEG_DG_X1CLK = 0x0004,
400    GLAMO_CLOCK_MPEG_EN_X1CLK = 0x0008,
401    GLAMO_CLOCK_MPEG_DG_X2CLK = 0x0010,
402    GLAMO_CLOCK_MPEG_EN_X2CLK = 0x0020,
403    GLAMO_CLOCK_MPEG_DG_X3CLK = 0x0040,
404    GLAMO_CLOCK_MPEG_EN_X3CLK = 0x0080,
405    GLAMO_CLOCK_MPEG_DG_X4CLK = 0x0100,
406    GLAMO_CLOCK_MPEG_EN_X4CLK = 0x0200,
407    GLAMO_CLOCK_MPEG_DG_X6CLK = 0x0400,
408    GLAMO_CLOCK_MPEG_EN_X6CLK = 0x0800,
409    GLAMO_CLOCK_MPEG_ENC_RESET = 0x1000,
410    GLAMO_CLOCK_MPEG_DEC_RESET = 0x2000,
411};
412
413enum glamo_reg_clock51 {
414    GLAMO_CLOCK_GEN51_EN_DIV_MCLK = 0x0001,
415    GLAMO_CLOCK_GEN51_EN_DIV_SCLK = 0x0002,
416    GLAMO_CLOCK_GEN51_EN_DIV_JCLK = 0x0004,
417    GLAMO_CLOCK_GEN51_EN_DIV_DCLK = 0x0008,
418    GLAMO_CLOCK_GEN51_EN_DIV_DMCLK = 0x0010,
419    GLAMO_CLOCK_GEN51_EN_DIV_DHCLK = 0x0020,
420    GLAMO_CLOCK_GEN51_EN_DIV_GCLK = 0x0040,
421    GLAMO_CLOCK_GEN51_EN_DIV_TCLK = 0x0080,
422    /* FIXME: higher bits */
423};
424
425enum glamo_reg_hostbus2 {
426    GLAMO_HOSTBUS2_MMIO_EN_ISP = 0x0001,
427    GLAMO_HOSTBUS2_MMIO_EN_JPEG = 0x0002,
428    GLAMO_HOSTBUS2_MMIO_EN_MPEG = 0x0004,
429    GLAMO_HOSTBUS2_MMIO_EN_LCD = 0x0008,
430    GLAMO_HOSTBUS2_MMIO_EN_MMC = 0x0010,
431    GLAMO_HOSTBUS2_MMIO_EN_MICROP0 = 0x0020,
432    GLAMO_HOSTBUS2_MMIO_EN_MICROP1 = 0x0040,
433    GLAMO_HOSTBUS2_MMIO_EN_CQ = 0x0080,
434    GLAMO_HOSTBUS2_MMIO_EN_RISC = 0x0100,
435    GLAMO_HOSTBUS2_MMIO_EN_2D = 0x0200,
436    GLAMO_HOSTBUS2_MMIO_EN_3D = 0x0400,
437};
438
439/* LCD Controller */
440
441#define REG_LCD(x) (x)
442enum glamo_reg_lcd {
443    GLAMO_REG_LCD_MODE1 = REG_LCD(0x00),
444    GLAMO_REG_LCD_MODE2 = REG_LCD(0x02),
445    GLAMO_REG_LCD_MODE3 = REG_LCD(0x04),
446    GLAMO_REG_LCD_WIDTH = REG_LCD(0x06),
447    GLAMO_REG_LCD_HEIGHT = REG_LCD(0x08),
448    GLAMO_REG_LCD_POLARITY = REG_LCD(0x0a),
449    GLAMO_REG_LCD_A_BASE1 = REG_LCD(0x0c),
450    GLAMO_REG_LCD_A_BASE2 = REG_LCD(0x0e),
451    GLAMO_REG_LCD_B_BASE1 = REG_LCD(0x10),
452    GLAMO_REG_LCD_B_BASE2 = REG_LCD(0x12),
453    GLAMO_REG_LCD_C_BASE1 = REG_LCD(0x14),
454    GLAMO_REG_LCD_C_BASE2 = REG_LCD(0x16),
455    GLAMO_REG_LCD_PITCH = REG_LCD(0x18),
456    /* RES */
457    GLAMO_REG_LCD_HORIZ_TOTAL = REG_LCD(0x1c),
458    /* RES */
459    GLAMO_REG_LCD_HORIZ_RETR_START = REG_LCD(0x20),
460    /* RES */
461    GLAMO_REG_LCD_HORIZ_RETR_END = REG_LCD(0x24),
462    /* RES */
463    GLAMO_REG_LCD_HORIZ_DISP_START = REG_LCD(0x28),
464    /* RES */
465    GLAMO_REG_LCD_HORIZ_DISP_END = REG_LCD(0x2c),
466    /* RES */
467    GLAMO_REG_LCD_VERT_TOTAL = REG_LCD(0x30),
468    /* RES */
469    GLAMO_REG_LCD_VERT_RETR_START = REG_LCD(0x34),
470    /* RES */
471    GLAMO_REG_LCD_VERT_RETR_END = REG_LCD(0x38),
472    /* RES */
473    GLAMO_REG_LCD_VERT_DISP_START = REG_LCD(0x3c),
474    /* RES */
475    GLAMO_REG_LCD_VERT_DISP_END = REG_LCD(0x40),
476    /* RES */
477    GLAMO_REG_LCD_POL = REG_LCD(0x44),
478    GLAMO_REG_LCD_DATA_START = REG_LCD(0x46),
479    GLAMO_REG_LCD_FRATE_CONTRO = REG_LCD(0x48),
480    GLAMO_REG_LCD_DATA_CMD_HDR = REG_LCD(0x4a),
481    GLAMO_REG_LCD_SP_START = REG_LCD(0x4c),
482    GLAMO_REG_LCD_SP_END = REG_LCD(0x4e),
483    GLAMO_REG_LCD_CURSOR_BASE1 = REG_LCD(0x50),
484    GLAMO_REG_LCD_CURSOR_BASE2 = REG_LCD(0x52),
485    GLAMO_REG_LCD_CURSOR_PITCH = REG_LCD(0x54),
486    GLAMO_REG_LCD_CURSOR_X_SIZE = REG_LCD(0x56),
487    GLAMO_REG_LCD_CURSOR_Y_SIZE = REG_LCD(0x58),
488    GLAMO_REG_LCD_CURSOR_X_POS = REG_LCD(0x5a),
489    GLAMO_REG_LCD_CURSOR_Y_POS = REG_LCD(0x5c),
490    GLAMO_REG_LCD_CURSOR_PRESET = REG_LCD(0x5e),
491    GLAMO_REG_LCD_CURSOR_FG_COLOR = REG_LCD(0x60),
492    /* RES */
493    GLAMO_REG_LCD_CURSOR_BG_COLOR = REG_LCD(0x64),
494    /* RES */
495    GLAMO_REG_LCD_CURSOR_DST_COLOR = REG_LCD(0x68),
496    /* RES */
497    GLAMO_REG_LCD_STATUS1 = REG_LCD(0x80),
498    GLAMO_REG_LCD_STATUS2 = REG_LCD(0x82),
499    GLAMO_REG_LCD_STATUS3 = REG_LCD(0x84),
500    GLAMO_REG_LCD_STATUS4 = REG_LCD(0x86),
501    /* RES */
502    GLAMO_REG_LCD_COMMAND1 = REG_LCD(0xa0),
503    GLAMO_REG_LCD_COMMAND2 = REG_LCD(0xa2),
504    /* RES */
505    GLAMO_REG_LCD_WFORM_DELAY1 = REG_LCD(0xb0),
506    GLAMO_REG_LCD_WFORM_DELAY2 = REG_LCD(0xb2),
507    /* RES */
508    GLAMO_REG_LCD_GAMMA_CORR = REG_LCD(0x100),
509    /* RES */
510    GLAMO_REG_LCD_GAMMA_R_ENTRY01 = REG_LCD(0x110),
511    GLAMO_REG_LCD_GAMMA_R_ENTRY23 = REG_LCD(0x112),
512    GLAMO_REG_LCD_GAMMA_R_ENTRY45 = REG_LCD(0x114),
513    GLAMO_REG_LCD_GAMMA_R_ENTRY67 = REG_LCD(0x116),
514    GLAMO_REG_LCD_GAMMA_R_ENTRY8 = REG_LCD(0x118),
515    /* RES */
516    GLAMO_REG_LCD_GAMMA_G_ENTRY01 = REG_LCD(0x130),
517    GLAMO_REG_LCD_GAMMA_G_ENTRY23 = REG_LCD(0x132),
518    GLAMO_REG_LCD_GAMMA_G_ENTRY45 = REG_LCD(0x134),
519    GLAMO_REG_LCD_GAMMA_G_ENTRY67 = REG_LCD(0x136),
520    GLAMO_REG_LCD_GAMMA_G_ENTRY8 = REG_LCD(0x138),
521    /* RES */
522    GLAMO_REG_LCD_GAMMA_B_ENTRY01 = REG_LCD(0x150),
523    GLAMO_REG_LCD_GAMMA_B_ENTRY23 = REG_LCD(0x152),
524    GLAMO_REG_LCD_GAMMA_B_ENTRY45 = REG_LCD(0x154),
525    GLAMO_REG_LCD_GAMMA_B_ENTRY67 = REG_LCD(0x156),
526    GLAMO_REG_LCD_GAMMA_B_ENTRY8 = REG_LCD(0x158),
527    /* RES */
528    GLAMO_REG_LCD_SRAM_DRIVING1 = REG_LCD(0x160),
529    GLAMO_REG_LCD_SRAM_DRIVING2 = REG_LCD(0x162),
530    GLAMO_REG_LCD_SRAM_DRIVING3 = REG_LCD(0x164),
531};
532
533enum glamo_reg_lcd_mode1 {
534    GLAMO_LCD_MODE1_PWRSAVE = 0x0001,
535    GLAMO_LCD_MODE1_PARTIAL_PRT = 0x0002,
536    GLAMO_LCD_MODE1_HWFLIP = 0x0004,
537    GLAMO_LCD_MODE1_LCD2 = 0x0008,
538    /* RES */
539    GLAMO_LCD_MODE1_PARTIAL_MODE = 0x0020,
540    GLAMO_LCD_MODE1_CURSOR_DSTCOLOR = 0x0040,
541    GLAMO_LCD_MODE1_PARTIAL_ENABLE = 0x0080,
542    GLAMO_LCD_MODE1_TVCLK_IN_ENABLE = 0x0100,
543    GLAMO_LCD_MODE1_HSYNC_HIGH_ACT = 0x0200,
544    GLAMO_LCD_MODE1_VSYNC_HIGH_ACT = 0x0400,
545    GLAMO_LCD_MODE1_HSYNC_FLIP = 0x0800,
546    GLAMO_LCD_MODE1_GAMMA_COR_EN = 0x1000,
547    GLAMO_LCD_MODE1_DITHER_EN = 0x2000,
548    GLAMO_LCD_MODE1_CURSOR_EN = 0x4000,
549    GLAMO_LCD_MODE1_ROTATE_EN = 0x8000,
550};
551
552enum glamo_reg_lcd_mode2 {
553    GLAMO_LCD_MODE2_CRC_CHECK_EN = 0x0001,
554    GLAMO_LCD_MODE2_DCMD_PER_LINE = 0x0002,
555    GLAMO_LCD_MODE2_NOUSE_BDEF = 0x0004,
556    GLAMO_LCD_MODE2_OUT_POS_MODE = 0x0008,
557    GLAMO_LCD_MODE2_FRATE_CTRL_EN = 0x0010,
558    GLAMO_LCD_MODE2_SINGLE_BUFFER = 0x0020,
559    GLAMO_LCD_MODE2_SER_LSB_TO_MSB = 0x0040,
560    /* FIXME */
561};
562
563enum glamo_reg_lcd_mode3 {
564    /* LCD color source data format */
565    GLAMO_LCD_SRC_RGB565 = 0x0000,
566    GLAMO_LCD_SRC_ARGB1555 = 0x4000,
567    GLAMO_LCD_SRC_ARGB4444 = 0x8000,
568    /* interface type */
569    GLAMO_LCD_MODE3_LCD = 0x1000,
570    GLAMO_LCD_MODE3_RGB = 0x0800,
571    GLAMO_LCD_MODE3_CPU = 0x0000,
572    /* mode */
573    GLAMO_LCD_MODE3_RGB332 = 0x0000,
574    GLAMO_LCD_MODE3_RGB444 = 0x0100,
575    GLAMO_LCD_MODE3_RGB565 = 0x0200,
576    GLAMO_LCD_MODE3_RGB666 = 0x0300,
577    /* depth */
578    GLAMO_LCD_MODE3_6BITS = 0x0000,
579    GLAMO_LCD_MODE3_8BITS = 0x0010,
580    GLAMO_LCD_MODE3_9BITS = 0x0020,
581    GLAMO_LCD_MODE3_16BITS = 0x0030,
582    GLAMO_LCD_MODE3_18BITS = 0x0040,
583};
584
585enum glamo_lcd_rot_mode {
586        GLAMO_LCD_ROT_MODE_0 = 0x0000,
587        GLAMO_LCD_ROT_MODE_180 = 0x2000,
588        GLAMO_LCD_ROT_MODE_MIRROR = 0x4000,
589        GLAMO_LCD_ROT_MODE_FLIP = 0x6000,
590        GLAMO_LCD_ROT_MODE_90 = 0x8000,
591        GLAMO_LCD_ROT_MODE_270 = 0xa000,
592};
593#define GLAMO_LCD_ROT_MODE_MASK 0xe000
594
595enum glamo_lcd_cmd_type {
596    GLAMO_LCD_CMD_TYPE_DISP = 0x0000,
597    GLAMO_LCD_CMD_TYPE_PARALLEL = 0x4000,
598    GLAMO_LCD_CMD_TYPE_SERIAL = 0x8000,
599    GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000,
600};
601#define GLAMO_LCD_CMD_TYPE_MASK 0xc000
602
603enum glamo_lcd_cmds {
604    GLAMO_LCD_CMD_DATA_DISP_FIRE = 0x00,
605    GLAMO_LCD_CMD_DATA_DISP_SYNC = 0x01, /* RGB only */
606    /* switch to command mode, no display */
607    GLAMO_LCD_CMD_DATA_FIRE_NO_DISP = 0x02,
608    /* display until VSYNC, switch to command */
609    GLAMO_LCD_CMD_DATA_FIRE_VSYNC = 0x11,
610    /* display until HSYNC, switch to command */
611    GLAMO_LCD_CMD_DATA_FIRE_HSYNC = 0x12,
612    /* display until VSYNC, 1 black frame, VSYNC, switch to command */
613    GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B = 0x13,
614    /* don't care about display and switch to command */
615    GLAMO_LCD_CMD_DATA_FIRE_FREE = 0x14, /* RGB only */
616    /* don't care about display, keep data display but disable data,
617     * and switch to command */
618    GLAMO_LCD_CMD_DATA_FIRE_FREE_D = 0x15, /* RGB only */
619};
620
621enum glamo_core_revisions {
622    GLAMO_CORE_REV_A0 = 0x0000,
623    GLAMO_CORE_REV_A1 = 0x0001,
624    GLAMO_CORE_REV_A2 = 0x0002,
625    GLAMO_CORE_REV_A3 = 0x0003,
626};
627
628#endif /* _GLAMO_REGS_H */
629

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