| 1 | /* |
| 2 | * (C) Copyright 2007 OpenMoko, Inc. |
| 3 | * Author: Andy Green <andy@openmoko.com> |
| 4 | * |
| 5 | * Generic i2c bitbang state machine |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | /* controls symbol sequencing on i2c */ |
| 25 | |
| 26 | enum i2c_bitbang_control { |
| 27 | IBCONTROL_DO_START = -1, |
| 28 | IBCONTROL_DO_STOP = -2, |
| 29 | IBCONTROL_DO_READ = -3, |
| 30 | IBCONTROL_COMPLETE = -4 |
| 31 | }; |
| 32 | |
| 33 | /* control intra-bit and byte states */ |
| 34 | |
| 35 | enum i2c_bitbang_states { |
| 36 | IBS_INIT, |
| 37 | |
| 38 | IBS_START1, |
| 39 | IBS_START2, |
| 40 | |
| 41 | IBS_ADS_TX_S, |
| 42 | IBS_ADS_TX_H, |
| 43 | IBS_ADS_TX_L, |
| 44 | IBS_ADS_TX_ACK_H, |
| 45 | IBS_ADS_TX_ACK_L, |
| 46 | |
| 47 | IBS_DATA_RX_S, |
| 48 | IBS_DATA_RX_H, |
| 49 | IBS_DATA_RX_L, |
| 50 | |
| 51 | IBS_DATA_RX_ACK_H, |
| 52 | IBS_DATA_RX_ACK_L, |
| 53 | |
| 54 | IBS_STOP1, |
| 55 | IBS_STOP2, |
| 56 | IBS_STOP3, |
| 57 | IBS_STOP4 |
| 58 | }; |
| 59 | |
| 60 | /* context for bitbang GPIO pins and transaction */ |
| 61 | |
| 62 | struct i2c_bitbang { |
| 63 | |
| 64 | enum i2c_bitbang_states state; |
| 65 | int count; |
| 66 | unsigned int data[8]; /* read result found here */ |
| 67 | int index; |
| 68 | int index_read; |
| 69 | |
| 70 | char (*read_sda)(void); |
| 71 | /* data = 0 = op low, 1 == inp */ |
| 72 | void (*set)(char clock, char data); |
| 73 | /* delay > 1 half-bit time, used by i2c_complete_synchronously() */ |
| 74 | void (*spin)(void); |
| 75 | void (*close)(void); |
| 76 | }; |
| 77 | |
| 78 | /* synchronous read and write functions spin until completed or failed |
| 79 | * i2c_read_sync returns -1 for fail or byte result from device |
| 80 | */ |
| 81 | |
| 82 | extern int i2c_read_sync(struct i2c_bitbang * bb, unsigned char ads7, |
| 83 | unsigned char reg); |
| 84 | extern void i2c_write_sync(struct i2c_bitbang * bb, unsigned char ads7, |
| 85 | unsigned char reg, unsigned char data); |
| 86 | |
| 87 | |
| 88 | /* |
| 89 | * set up an asynchronous read or write transaction |
| 90 | */ |
| 91 | extern void i2c_read(struct i2c_bitbang * bb, unsigned char ads7, |
| 92 | unsigned char reg); |
| 93 | extern void i2c_write(struct i2c_bitbang * bb, unsigned char ads7, |
| 94 | unsigned char reg, unsigned char data); |
| 95 | |
| 96 | /* |
| 97 | * after setting up a read or write transaction above, you loop calling this |
| 98 | * with >= 1.25us (400kHz) or >= 5us (100kHz) delay between calls. You don't |
| 99 | * have to spin but can do something useful if you know it will take more than |
| 100 | * an i2c bit-time, hiding the time for the i2c transaction completely. |
| 101 | */ |
| 102 | extern int i2c_next_state(struct i2c_bitbang * bb); /* return !=0 = completed */ |
| 103 | |
