| 1 | /* |
| 2 | * Header for MultiMediaCard (MMC) |
| 3 | * |
| 4 | * Copyright 2002 Hewlett-Packard Company |
| 5 | * |
| 6 | * Use consistent with the GNU GPL is permitted, |
| 7 | * provided that this copyright notice is |
| 8 | * preserved in its entirety in all copies and derived works. |
| 9 | * |
| 10 | * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, |
| 11 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS |
| 12 | * FITNESS FOR ANY PARTICULAR PURPOSE. |
| 13 | * |
| 14 | * Many thanks to Alessandro Rubini and Jonathan Corbet! |
| 15 | * |
| 16 | * Based strongly on code by: |
| 17 | * |
| 18 | * Author: Yong-iL Joh <tolkien@mizi.com> |
| 19 | * Date : $Date: 2006/12/06 02:50:52 $ |
| 20 | * |
| 21 | * Author: Andrew Christian |
| 22 | * 15 May 2002 |
| 23 | */ |
| 24 | |
| 25 | #ifndef MMC_MMC_PROTOCOL_H |
| 26 | #define MMC_MMC_PROTOCOL_H |
| 27 | |
| 28 | #ifdef CONFIG_SUPPORT_MMC_PLUS |
| 29 | /* Standard MMC commands (4.2) type argument response */ |
| 30 | #else |
| 31 | /* Standard MMC commands (3.1) type argument response */ |
| 32 | #endif |
| 33 | /* class 1 */ |
| 34 | #define MMC_GO_IDLE_STATE 0 /* bc */ |
| 35 | #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ |
| 36 | #define MMC_ALL_SEND_CID 2 /* bcr R2 */ |
| 37 | #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ |
| 38 | #define MMC_SET_DSR 4 /* bc [31:16] RCA */ |
| 39 | #define MMC_SWITCH 6 /* ac R1b */ |
| 40 | #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ |
| 41 | #define MMC_SEND_EXT_CSD 8 /* adtc R1 */ |
| 42 | #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ |
| 43 | #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ |
| 44 | #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ |
| 45 | #define MMC_STOP_TRANSMISSION 12 /* ac R1b */ |
| 46 | #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ |
| 47 | #define MMC_BUSTEST_R 14 /* adtc R1 */ |
| 48 | #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ |
| 49 | #define MMC_BUSTEST_W 19 /* adtc R1 */ |
| 50 | |
| 51 | /* class 2 */ |
| 52 | #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ |
| 53 | #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ |
| 54 | #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ |
| 55 | |
| 56 | /* class 3 */ |
| 57 | #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ |
| 58 | |
| 59 | /* class 4 */ |
| 60 | #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ |
| 61 | #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ |
| 62 | #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ |
| 63 | #define MMC_PROGRAM_CID 26 /* adtc R1 */ |
| 64 | #define MMC_PROGRAM_CSD 27 /* adtc R1 */ |
| 65 | |
| 66 | /* class 6 */ |
| 67 | #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ |
| 68 | #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ |
| 69 | #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ |
| 70 | |
| 71 | /* class 5 */ |
| 72 | #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ |
| 73 | #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ |
| 74 | #define MMC_ERASE 38 /* ac R1b */ |
| 75 | |
| 76 | /* class 9 */ |
| 77 | #define MMC_FAST_IO 39 /* ac <Complex> R4 */ |
| 78 | #define MMC_GO_IRQ_STATE 40 /* bcr R5 */ |
| 79 | |
| 80 | /* class 7 */ |
| 81 | #define MMC_LOCK_UNLOCK 42 /* adtc R1b */ |
| 82 | |
| 83 | /* class 8 */ |
| 84 | #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ |
| 85 | #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ |
| 86 | |
| 87 | /* SD commands type argument response */ |
| 88 | /* class 8 */ |
| 89 | /* This is basically the same command as for MMC with some quirks. */ |
| 90 | #define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */ |
| 91 | |
| 92 | /* Application commands */ |
| 93 | #define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ |
| 94 | #define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ |
| 95 | #define SD_APP_SEND_SCR 51 /* adtc R1 */ |
| 96 | |
| 97 | /* |
| 98 | MMC status in R1 |
| 99 | Type |
| 100 | e : error bit |
| 101 | s : status bit |
| 102 | r : detected and set for the actual command response |
| 103 | x : detected and set during command execution. the host must poll |
| 104 | the card by sending status command in order to read these bits. |
| 105 | Clear condition |
| 106 | a : according to the card state |
| 107 | b : always related to the previous command. Reception of |
| 108 | a valid command will clear it (with a delay of one command) |
| 109 | c : clear by read |
| 110 | */ |
| 111 | |
| 112 | #define R1_OUT_OF_RANGE (1 << 31) /* er, c */ |
| 113 | #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ |
| 114 | #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ |
| 115 | #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ |
| 116 | #define R1_ERASE_PARAM (1 << 27) /* ex, c */ |
| 117 | #define R1_WP_VIOLATION (1 << 26) /* erx, c */ |
| 118 | #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ |
| 119 | #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ |
| 120 | #define R1_COM_CRC_ERROR (1 << 23) /* er, b */ |
| 121 | #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ |
| 122 | #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ |
| 123 | #define R1_CC_ERROR (1 << 20) /* erx, c */ |
| 124 | #define R1_ERROR (1 << 19) /* erx, c */ |
| 125 | #define R1_UNDERRUN (1 << 18) /* ex, c */ |
| 126 | #define R1_OVERRUN (1 << 17) /* ex, c */ |
| 127 | #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ |
| 128 | #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ |
| 129 | #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ |
| 130 | #define R1_ERASE_RESET (1 << 13) /* sr, c */ |
| 131 | #define R1_STATUS(x) (x & 0xFFFFE000) |
| 132 | #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ |
| 133 | #define R1_READY_FOR_DATA (1 << 8) /* sx, a */ |
| 134 | #define R1_APP_CMD (1 << 5) /* sr, c */ |
| 135 | |
| 136 | /* |
| 137 | MMC CURRENT_STATE in R1 [12:9] |
| 138 | */ |
| 139 | #define STATE_IDLE (0x0 << 9) /* 0 */ |
| 140 | #define STATE_READY (0x1 << 9) /* 1 */ |
| 141 | #define STATE_IDENT (0x2 << 9) /* 2 */ |
| 142 | #define STATE_STBY (0x3 << 9) /* 3 */ |
| 143 | #define STATE_TRAN (0x4 << 9) /* 4 */ |
| 144 | #define STATE_DATA (0x5 << 9) /* 5 */ |
| 145 | #define STATE_RCV (0x6 << 9) /* 6 */ |
| 146 | #define STATE_PRG (0x7 << 9) /* 7 */ |
| 147 | #define STATE_DIS (0x8 << 9) /* 8 */ |
| 148 | #define STATE_BTST (0x9 << 9) /* 9 */ |
| 149 | |
| 150 | /* These are unpacked versions of the actual responses */ |
| 151 | |
| 152 | struct _mmc_csd { |
| 153 | u8 csd_structure; |
| 154 | u8 spec_vers; |
| 155 | u8 taac; |
| 156 | u8 nsac; |
| 157 | u8 tran_speed; |
| 158 | u16 ccc; |
| 159 | u8 read_bl_len; |
| 160 | u8 read_bl_partial; |
| 161 | u8 write_blk_misalign; |
| 162 | u8 read_blk_misalign; |
| 163 | u8 dsr_imp; |
| 164 | u16 c_size; |
| 165 | u8 vdd_r_curr_min; |
| 166 | u8 vdd_r_curr_max; |
| 167 | u8 vdd_w_curr_min; |
| 168 | u8 vdd_w_curr_max; |
| 169 | u8 c_size_mult; |
| 170 | union { |
| 171 | struct { /* MMC system specification version 3.1 */ |
| 172 | u8 erase_grp_size; |
| 173 | u8 erase_grp_mult; |
| 174 | } v31; |
| 175 | struct { /* MMC system specification version 2.2 */ |
| 176 | u8 sector_size; |
| 177 | u8 erase_grp_size; |
| 178 | } v22; |
| 179 | } erase; |
| 180 | u8 wp_grp_size; |
| 181 | u8 wp_grp_enable; |
| 182 | u8 default_ecc; |
| 183 | u8 r2w_factor; |
| 184 | u8 write_bl_len; |
| 185 | u8 write_bl_partial; |
| 186 | u8 file_format_grp; |
| 187 | u8 copy; |
| 188 | u8 perm_write_protect; |
| 189 | u8 tmp_write_protect; |
| 190 | u8 file_format; |
| 191 | u8 ecc; |
| 192 | }; |
| 193 | |
| 194 | struct _mmc_ext_csd { |
| 195 | u8 s_cmd_set; |
| 196 | u32 sec_count; |
| 197 | u8 MIN_PERF_W_8_52; |
| 198 | u8 MIN_PERF_R_8_52; |
| 199 | u8 MIN_PERF_W_8_26_4_52; |
| 200 | u8 MIN_PERF_R_8_26_4_52; |
| 201 | u8 MIN_PERF_W_4_26; |
| 202 | u8 MIN_PERF_R_4_26; |
| 203 | u8 PWR_CL_26_360; |
| 204 | u8 PWR_CL_52_360; |
| 205 | u8 PWR_CL_26_195; |
| 206 | u8 PWR_CL_52_195; |
| 207 | u8 card_type; |
| 208 | u8 csd_structure; |
| 209 | u8 ext_csd_rev; |
| 210 | u8 cmd_set; |
| 211 | u8 cmd_set_rev; |
| 212 | u8 power_class; |
| 213 | u8 hs_timing; |
| 214 | u8 bus_width; |
| 215 | }; |
| 216 | |
| 217 | #define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */ |
| 218 | #define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */ |
| 219 | #define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */ |
| 220 | #define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */ |
| 221 | #define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */ |
| 222 | #define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */ |
| 223 | #define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */ |
| 224 | #define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */ |
| 225 | #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ |
| 226 | #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ |
| 227 | #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ |
| 228 | #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ |
| 229 | #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ |
| 230 | #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ |
| 231 | #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ |
| 232 | #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ |
| 233 | #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ |
| 234 | #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ |
| 235 | #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ |
| 236 | #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ |
| 237 | #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ |
| 238 | #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ |
| 239 | #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ |
| 240 | #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ |
| 241 | #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ |
| 242 | |
| 243 | /* |
| 244 | * Card Command Classes (CCC) |
| 245 | */ |
| 246 | #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ |
| 247 | /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ |
| 248 | #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ |
| 249 | /* (CMD11) */ |
| 250 | #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ |
| 251 | /* (CMD16,17,18) */ |
| 252 | #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ |
| 253 | /* (CMD20) */ |
| 254 | #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ |
| 255 | /* (CMD16,24,25,26,27) */ |
| 256 | #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ |
| 257 | /* (CMD32,33,34,35,36,37,38,39) */ |
| 258 | #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ |
| 259 | /* (CMD28,29,30) */ |
| 260 | #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ |
| 261 | /* (CMD16,CMD42) */ |
| 262 | #define CCC_APP_SPEC (1<<8) /* (8) Application specific */ |
| 263 | /* (CMD55,56,57,ACMD*) */ |
| 264 | #define CCC_IO_MODE (1<<9) /* (9) I/O mode */ |
| 265 | /* (CMD5,39,40,52,53) */ |
| 266 | #define CCC_SWITCH (1<<10) /* (10) High speed switch */ |
| 267 | /* (CMD6,34,35,36,37,50) */ |
| 268 | /* (11) Reserved */ |
| 269 | /* (CMD?) */ |
| 270 | |
| 271 | /* |
| 272 | * CSD field definitions |
| 273 | */ |
| 274 | |
| 275 | #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ |
| 276 | #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ |
| 277 | #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */ |
| 278 | |
| 279 | #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ |
| 280 | #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ |
| 281 | #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ |
| 282 | #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */ |
| 283 | #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 ~ 4.2 */ |
| 284 | |
| 285 | /* |
| 286 | * SD bus widths |
| 287 | */ |
| 288 | #define SD_BUS_WIDTH_1 0 |
| 289 | #define SD_BUS_WIDTH_4 2 |
| 290 | |
| 291 | /* |
| 292 | * EXT_CSD field definitions |
| 293 | */ |
| 294 | |
| 295 | /* |
| 296 | * S_CMD_SET |
| 297 | */ |
| 298 | |
| 299 | #define STANDARD_MMC 0 /* Standard MMC */ |
| 300 | #define SECURE_MMC 1 /* Secure MMC */ |
| 301 | #define CPS_MMC 2 /* Content Protection Secure MMC */ |
| 302 | #define SECURE_MMC_2 3 /* Secure MMC 2.0 */ |
| 303 | #define ATA_MMC 4 /* ATA on MMC */ |
| 304 | |
| 305 | /* |
| 306 | * MIN_PERF_a_b_ff |
| 307 | */ |
| 308 | #define NO_CLASS 0x0 /* For cards not reaching the 2.4MB/s minimum value */ |
| 309 | #define CLASS_A 0x08 /* Class A */ |
| 310 | #define CLASS_B 0x0A /* Class B */ |
| 311 | #define CLASS_C 0x0F /* Class C */ |
| 312 | #define CLASS_D 0x14 /* Class D */ |
| 313 | #define CLASS_E 0x1E /* Class E */ |
| 314 | #define CLASS_F 0x28 /* Class F */ |
| 315 | #define CLASS_G 0x32 /* Class G */ |
| 316 | #define CLASS_H 0x3c /* Class H */ |
| 317 | #define CLASS_J 0x46 /* Class J */ |
| 318 | #define CLASS_K 0x50 /* Class E */ |
| 319 | #define CLASS_M 0x64 /* Class M */ |
| 320 | #define CLASS_O 0x78 /* Class O */ |
| 321 | #define CLASS_R 0x8c /* Class R */ |
| 322 | #define CLASS_T 0xa0 /* Class T */ |
| 323 | |
| 324 | /* |
| 325 | * CARD_TYPE |
| 326 | */ |
| 327 | |
| 328 | #define MMCPLUS_26MHZ (1<<0) |
| 329 | #define MMCPLUS_52MHZ (1<<1) |
| 330 | |
| 331 | /* |
| 332 | * EXT_CSD_REV |
| 333 | */ |
| 334 | |
| 335 | #define EXT_CSD_REV_1_0 0 |
| 336 | #define EXT_CSD_REV_1_1 1 |
| 337 | #define EXT_CSD_REV_1_2 2 |
| 338 | |
| 339 | /* |
| 340 | * HS_TIMING |
| 341 | */ |
| 342 | #define HS_TIMING_LOW 0 |
| 343 | #define HS_TIMING_HIGH 1 |
| 344 | |
| 345 | /* |
| 346 | * BUS_WIDTH |
| 347 | */ |
| 348 | #define MMCPLUS_BUS_WIDTH_1 0 |
| 349 | #define MMCPLUS_BUS_WIDTH_4 1 |
| 350 | #define MMCPLUS_BUS_WIDTH_8 2 |
| 351 | |
| 352 | |
| 353 | /* |
| 354 | * ERASED_MEM_CONT |
| 355 | */ |
| 356 | |
| 357 | #define ERASED_MEM_CONT_0 0 |
| 358 | #define ERASED_MEM_CONT_1 1 |
| 359 | |
| 360 | /* |
| 361 | * Argument for CMD6 |
| 362 | */ |
| 363 | |
| 364 | /* |
| 365 | * EXT_CSD Access Modes |
| 366 | */ |
| 367 | |
| 368 | #define EXT_CSD_COMMAND_SET 0 |
| 369 | #define EXT_CSD_SET_BITS 1 |
| 370 | #define EXT_CSD_CLEAR_BITS 2 |
| 371 | #define EXT_CSD_WRITE_BYTE 3 |
| 372 | |
| 373 | /* |
| 374 | * EXT_CSD Argument Byte |
| 375 | */ |
| 376 | |
| 377 | #define EXT_CSD_POWER_CLASS 187 |
| 378 | #define EXT_CSD_BUS_WIDTH 183 |
| 379 | #define EXT_CSD_HS_TIMING 185 |
| 380 | |
| 381 | #endif /* MMC_MMC_PROTOCOL_H */ |
| 382 | |
| 383 | |
