| 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. |
| 4 | * - only support for S3C6400 |
| 5 | * $Id: s3c6410.h,v 1.6 2008/07/02 11:01:48 jsgood Exp $ |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /************************************************ |
| 24 | * NAME : s3c6400.h |
| 25 | * |
| 26 | * Based on S3C6400 User's manual Rev 0.0 |
| 27 | ************************************************/ |
| 28 | |
| 29 | #ifndef __S3C6410_H__ |
| 30 | #define __S3C6410_H__ |
| 31 | |
| 32 | #ifndef CONFIG_S3C6410 |
| 33 | #define CONFIG_S3C6410 1 |
| 34 | #endif |
| 35 | |
| 36 | #define S3C64XX_UART_CHANNELS 4 |
| 37 | #define S3C64XX_SPI_CHANNELS 2 |
| 38 | |
| 39 | #define HSMMC_CHANNEL 0 |
| 40 | #define MOVI_INIT_REQUIRED 0 |
| 41 | #define TCM_BASE 0x0C004000 |
| 42 | #define BL2_BASE 0x57E00000 |
| 43 | #define CopyMovitoMem(a,b,c,d,e) (((int(*)(int, uint, ushort, uint *, int))(*((uint *)(TCM_BASE + 0x8))))(a,b,c,d,e)) |
| 44 | #define SS_SIZE (8 * 1024) |
| 45 | #define eFUSE_SIZE (1 * 1024) // 0.5k eFuse, 0.5k reserved` |
| 46 | #define PART_UBOOT_OFFSET 0x0 |
| 47 | #define PART_ZIMAGE_OFFSET 0x40000 |
| 48 | #define PART_ROOTFS_OFFSET 0x200000 |
| 49 | #define PART_EXTRA_OFFSET 0x3200000 |
| 50 | |
| 51 | /* movinand definitions */ |
| 52 | #define MOVI_BLKSIZE 512 |
| 53 | |
| 54 | #define MOVI_TOTAL_BLKCNT 7864320 // 7864320 // 3995648 // 1003520 /* static movinand total block count: for writing to movinand when nand boot */ |
| 55 | #define MOVI_HIGH_CAPACITY 0 |
| 56 | |
| 57 | #define MOVI_LAST_BLKPOS (MOVI_TOTAL_BLKCNT - (eFUSE_SIZE / MOVI_BLKSIZE)) |
| 58 | #define MOVI_BL1_BLKCNT (SS_SIZE / MOVI_BLKSIZE) |
| 59 | #define MOVI_ENV_BLKCNT (CFG_ENV_SIZE / MOVI_BLKSIZE) |
| 60 | #define MOVI_BL2_BLKCNT (((PART_ZIMAGE_OFFSET - PART_UBOOT_OFFSET) / MOVI_BLKSIZE) - MOVI_ENV_BLKCNT) |
| 61 | #define MOVI_ZIMAGE_BLKCNT ((PART_ROOTFS_OFFSET - PART_ZIMAGE_OFFSET) / MOVI_BLKSIZE) |
| 62 | #define MOVI_BL2_POS (MOVI_LAST_BLKPOS - MOVI_BL1_BLKCNT - MOVI_BL2_BLKCNT - MOVI_ENV_BLKCNT) |
| 63 | #ifndef __ASSEMBLY__ |
| 64 | |
| 65 | struct movi_offset_t { |
| 66 | uint last; |
| 67 | uint bl1; |
| 68 | uint env; |
| 69 | uint bl2; |
| 70 | uint zimage; |
| 71 | }; |
| 72 | |
| 73 | /* external functions */ |
| 74 | extern void hsmmc_set_gpio(void); |
| 75 | extern void hsmmc_reset (void); |
| 76 | extern int hsmmc_init (void); |
| 77 | |
| 78 | extern void test_hsmmc (uint width, uint test, uint start_blk, uint blknum); |
| 79 | |
| 80 | |
| 81 | typedef enum { |
| 82 | S3C64XX_UART0, |
| 83 | S3C64XX_UART1, |
| 84 | S3C64XX_UART2, |
| 85 | S3C64XX_UART3, |
| 86 | } S3C64XX_UARTS_NR; |
| 87 | |
| 88 | #define __REG(x) (*((volatile unsigned int *)(x))) |
| 89 | |
| 90 | //#include <s3c64x0.h> |
| 91 | #endif |
| 92 | |
| 93 | #define BIT0 0x00000001 |
| 94 | #define BIT1 0x00000002 |
| 95 | #define BIT2 0x00000004 |
| 96 | #define BIT3 0x00000008 |
| 97 | #define BIT4 0x00000010 |
| 98 | #define BIT5 0x00000020 |
| 99 | #define BIT6 0x00000040 |
| 100 | #define BIT7 0x00000080 |
| 101 | #define BIT8 0x00000100 |
| 102 | #define BIT9 0x00000200 |
| 103 | #define BIT10 0x00000400 |
| 104 | #define BIT11 0x00000800 |
| 105 | #define BIT12 0x00001000 |
| 106 | #define BIT13 0x00002000 |
| 107 | #define BIT14 0x00004000 |
| 108 | #define BIT15 0x00008000 |
| 109 | #define BIT16 0x00010000 |
| 110 | #define BIT17 0x00020000 |
| 111 | #define BIT18 0x00040000 |
| 112 | #define BIT19 0x00080000 |
| 113 | #define BIT20 0x00100000 |
| 114 | #define BIT21 0x00200000 |
| 115 | #define BIT22 0x00400000 |
| 116 | #define BIT23 0x00800000 |
| 117 | #define BIT24 0x01000000 |
| 118 | #define BIT25 0x02000000 |
| 119 | #define BIT26 0x04000000 |
| 120 | #define BIT27 0x08000000 |
| 121 | #define BIT28 0x10000000 |
| 122 | #define BIT29 0x20000000 |
| 123 | #define BIT30 0x40000000 |
| 124 | #define BIT31 0x80000000 |
| 125 | |
| 126 | #define ROM_BASE0 0x00000000 /* base address of rom bank 0 */ |
| 127 | #define ROM_BASE1 0x04000000 /* base address of rom bank 1 */ |
| 128 | #define DRAM_BASE0 0x40000000 /* base address of dram bank 0 */ |
| 129 | #define DRAM_BASE1 0x50000000 /* base address of dram bank 1 */ |
| 130 | |
| 131 | |
| 132 | /* S3C6400 device base addresses */ |
| 133 | #define ELFIN_DMA_BASE 0x75000000 |
| 134 | #define ELFIN_LCD_BASE 0x77100000 |
| 135 | #define ELFIN_USB_HOST_BASE 0x74300000 |
| 136 | #define ELFIN_I2C_BASE 0x7f004000 |
| 137 | #define ELFIN_I2S_BASE 0x7f002000 |
| 138 | #define ELFIN_ADC_BASE 0x7e00b000 |
| 139 | #define ELFIN_SPI_BASE 0x7f00b000 |
| 140 | #define ELFIN_HSMMC_0_BASE 0x7c200000 |
| 141 | #define ELFIN_HSMMC_1_BASE 0x7c300000 |
| 142 | #define ELFIN_HSMMC_2_BASE 0x7c400000 |
| 143 | |
| 144 | #define ELFIN_CLOCK_POWER_BASE 0x7e00f000 |
| 145 | |
| 146 | /* Clock & Power Controller for mDirac3*/ |
| 147 | #define APLL_LOCK_OFFSET 0x00 |
| 148 | #define MPLL_LOCK_OFFSET 0x04 |
| 149 | #define EPLL_LOCK_OFFSET 0x08 |
| 150 | #define APLL_CON_OFFSET 0x0C |
| 151 | #define MPLL_CON_OFFSET 0x10 |
| 152 | #define EPLL_CON0_OFFSET 0x14 |
| 153 | #define EPLL_CON1_OFFSET 0x18 |
| 154 | #define CLK_SRC_OFFSET 0x1C |
| 155 | #define CLK_DIV0_OFFSET 0x20 |
| 156 | #define CLK_DIV1_OFFSET 0x24 |
| 157 | #define CLK_DIV2_OFFSET 0x28 |
| 158 | #define CLK_OUT_OFFSET 0x2C |
| 159 | #define HCLK_GATE_OFFSET 0x30 |
| 160 | #define PCLK_GATE_OFFSET 0x34 |
| 161 | #define SCLK_GATE_OFFSET 0x38 |
| 162 | #define AHB_CON0_OFFSET 0x100 |
| 163 | #define AHB_CON1_OFFSET 0x104 |
| 164 | #define AHB_CON2_OFFSET 0x108 |
| 165 | #define SELECT_DMA_OFFSET 0x110 |
| 166 | #define SW_RST_OFFSET 0x114 |
| 167 | #define SYS_ID_OFFSET 0x118 |
| 168 | #define MEM_SYS_CFG_OFFSET 0x120 |
| 169 | #define QOS_OVERRIDE0_OFFSET 0x124 |
| 170 | #define QOS_OVERRIDE1_OFFSET 0x128 |
| 171 | #define MEM_CFG_STAT_OFFSET 0x12C |
| 172 | #define PWR_CFG_OFFSET 0x804 |
| 173 | #define EINT_MASK_OFFSET 0x808 |
| 174 | #define NOR_CFG_OFFSET 0x810 |
| 175 | #define STOP_CFG_OFFSET 0x814 |
| 176 | #define SLEEP_CFG_OFFSET 0x818 |
| 177 | #define STOP_MEM_CFG_OFFSET 0x81c |
| 178 | #define OSC_FREQ_OFFSET 0x820 |
| 179 | #define OSC_STABLE_OFFSET 0x824 |
| 180 | #define PWR_STABLE_OFFSET 0x828 |
| 181 | #define FPC_STABLE_OFFSET 0x82C |
| 182 | #define MTC_STABLE_OFFSET 0x830 |
| 183 | #define OTHERS_OFFSET 0x900 |
| 184 | #define RST_STAT_OFFSET 0x904 |
| 185 | #define WAKEUP_STAT_OFFSET 0x908 |
| 186 | #define BLK_PWR_STAT_OFFSET 0x90C |
| 187 | #define INF_REG0_OFFSET 0xA00 |
| 188 | #define INF_REG1_OFFSET 0xA04 |
| 189 | #define INF_REG2_OFFSET 0xA08 |
| 190 | #define INF_REG3_OFFSET 0xA0C |
| 191 | #define INF_REG4_OFFSET 0xA10 |
| 192 | #define INF_REG5_OFFSET 0xA14 |
| 193 | #define INF_REG6_OFFSET 0xA18 |
| 194 | #define INF_REG7_OFFSET 0xA1C |
| 195 | |
| 196 | #define OSC_CNT_VAL_OFFSET 0x824 |
| 197 | #define PWR_CNT_VAL_OFFSET 0x828 |
| 198 | #define FPC_CNT_VAL_OFFSET 0x82C |
| 199 | #define MTC_CNT_VAL_OFFSET 0x830 |
| 200 | |
| 201 | |
| 202 | #define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET) |
| 203 | #define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET) |
| 204 | #define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET) |
| 205 | #define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET) |
| 206 | #define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET) |
| 207 | #define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET) |
| 208 | #define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET) |
| 209 | #define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET) |
| 210 | #define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET) |
| 211 | #define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET) |
| 212 | #define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET) |
| 213 | #define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET) |
| 214 | #define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET) |
| 215 | #define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET) |
| 216 | #define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET) |
| 217 | #define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET) |
| 218 | #define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET) |
| 219 | #define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET) |
| 220 | #define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET) |
| 221 | #define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET) |
| 222 | #define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET) |
| 223 | #define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET) |
| 224 | #define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET) |
| 225 | #define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET) |
| 226 | #define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET) |
| 227 | #define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET) |
| 228 | #define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET) |
| 229 | #define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET) |
| 230 | #define STOP_MEM_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+STOP_MEM_CFG_OFFSET) |
| 231 | #define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET) |
| 232 | #define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET) |
| 233 | #define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET) |
| 234 | #define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET) |
| 235 | #define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET) |
| 236 | #define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET) |
| 237 | #define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET) |
| 238 | #define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) |
| 239 | #define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET) |
| 240 | #define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET) |
| 241 | #define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET) |
| 242 | #define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET) |
| 243 | #define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET) |
| 244 | #define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET) |
| 245 | #define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET) |
| 246 | #define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET) |
| 247 | #define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET) |
| 248 | #define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET) |
| 249 | |
| 250 | #define APLL_LOCK (ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET) |
| 251 | #define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET) |
| 252 | #define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET) |
| 253 | #define APLL_CON (ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET) |
| 254 | #define MPLL_CON (ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET) |
| 255 | #define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET) |
| 256 | #define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET) |
| 257 | #define CLK_SRC (ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET) |
| 258 | #define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET) |
| 259 | #define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET) |
| 260 | #define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET) |
| 261 | #define CLK_OUT (ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET) |
| 262 | #define HCLK_GATE (ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET) |
| 263 | #define PCLK_GATE (ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET) |
| 264 | #define SCLK_GATE (ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET) |
| 265 | #define AHB_CON0 (ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET) |
| 266 | #define AHB_CON1 (ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET) |
| 267 | #define AHB_CON2 (ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET) |
| 268 | #define SELECT_DMA (ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET) |
| 269 | #define SW_RST (ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET) |
| 270 | #define SYS_ID (ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET) |
| 271 | #define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET) |
| 272 | #define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET) |
| 273 | #define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET) |
| 274 | #define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET) |
| 275 | #define PWR_CFG (ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET) |
| 276 | #define EINT_MASK (ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET) |
| 277 | #define NOR_CFG (ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET) |
| 278 | #define STOP_CFG (ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET) |
| 279 | #define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET) |
| 280 | #define STOP_MEM_CFG (ELFIN_CLOCK_POWER_BASE+STOP_MEM_CFG_OFFSET) |
| 281 | #define OSC_FREQ (ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET) |
| 282 | #define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET) |
| 283 | #define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET) |
| 284 | #define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET) |
| 285 | #define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET) |
| 286 | #define OTHERS (ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET) |
| 287 | #define RST_STAT (ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) |
| 288 | #define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET) |
| 289 | #define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET) |
| 290 | #define INF_REG0 (ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET) |
| 291 | #define INF_REG1 (ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET) |
| 292 | #define INF_REG2 (ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET) |
| 293 | #define INF_REG3 (ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET) |
| 294 | #define INF_REG4 (ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET) |
| 295 | #define INF_REG5 (ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET) |
| 296 | #define INF_REG6 (ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET) |
| 297 | #define INF_REG7 (ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET) |
| 298 | |
| 299 | |
| 300 | /* |
| 301 | * GPIO |
| 302 | */ |
| 303 | #define ELFIN_GPIO_BASE 0x7f008000 |
| 304 | |
| 305 | #define GPACON_OFFSET 0x00 |
| 306 | #define GPADAT_OFFSET 0x04 |
| 307 | #define GPAPUD_OFFSET 0x08 |
| 308 | #define GPACONSLP_OFFSET 0x0C |
| 309 | #define GPAPUDSLP_OFFSET 0x10 |
| 310 | #define GPBCON_OFFSET 0x20 |
| 311 | #define GPBDAT_OFFSET 0x24 |
| 312 | #define GPBPUD_OFFSET 0x28 |
| 313 | #define GPBCONSLP_OFFSET 0x2C |
| 314 | #define GPBPUDSLP_OFFSET 0x30 |
| 315 | #define GPCCON_OFFSET 0x40 |
| 316 | #define GPCDAT_OFFSET 0x44 |
| 317 | #define GPCPUD_OFFSET 0x48 |
| 318 | #define GPCCONSLP_OFFSET 0x4C |
| 319 | #define GPCPUDSLP_OFFSET 0x50 |
| 320 | #define GPDCON_OFFSET 0x60 |
| 321 | #define GPDDAT_OFFSET 0x64 |
| 322 | #define GPDPUD_OFFSET 0x68 |
| 323 | #define GPDCONSLP_OFFSET 0x6C |
| 324 | #define GPDPUDSLP_OFFSET 0x70 |
| 325 | #define GPECON_OFFSET 0x80 |
| 326 | #define GPEDAT_OFFSET 0x84 |
| 327 | #define GPEPUD_OFFSET 0x88 |
| 328 | #define GPECONSLP_OFFSET 0x8C |
| 329 | #define GPEPUDSLP_OFFSET 0x90 |
| 330 | #define GPFCON_OFFSET 0xA0 |
| 331 | #define GPFDAT_OFFSET 0xA4 |
| 332 | #define GPFPUD_OFFSET 0xA8 |
| 333 | #define GPFCONSLP_OFFSET 0xAC |
| 334 | #define GPFPUDSLP_OFFSET 0xB0 |
| 335 | #define GPGCON_OFFSET 0xC0 |
| 336 | #define GPGDAT_OFFSET 0xC4 |
| 337 | #define GPGPUD_OFFSET 0xC8 |
| 338 | #define GPGCONSLP_OFFSET 0xCC |
| 339 | #define GPGPUDSLP_OFFSET 0xD0 |
| 340 | #define GPHCON0_OFFSET 0xE0 |
| 341 | #define GPHCON1_OFFSET 0xE4 |
| 342 | #define GPHDAT_OFFSET 0xE8 |
| 343 | #define GPHPUD_OFFSET 0xEC |
| 344 | #define GPHCONSLP_OFFSET 0xF0 |
| 345 | #define GPHPUDSLP_OFFSET 0xF4 |
| 346 | #define GPICON_OFFSET 0x100 |
| 347 | #define GPIDAT_OFFSET 0x104 |
| 348 | #define GPIPUD_OFFSET 0x108 |
| 349 | #define GPICONSLP_OFFSET 0x10C |
| 350 | #define GPIPUDSLP_OFFSET 0x110 |
| 351 | #define GPJCON_OFFSET 0x120 |
| 352 | #define GPJDAT_OFFSET 0x124 |
| 353 | #define GPJPUD_OFFSET 0x128 |
| 354 | #define GPJCONSLP_OFFSET 0x12C |
| 355 | #define GPJPUDSLP_OFFSET 0x130 |
| 356 | #define SPCON_OFFSET 0x1A0 |
| 357 | #define MEM0DRVCON_OFFSET 0x1D0 |
| 358 | #define MEM1DRVCON_OFFSET 0x1D4 |
| 359 | #define GPKCON0_OFFSET 0x800 |
| 360 | #define GPKCON1_OFFSET 0x804 |
| 361 | #define GPKDAT_OFFSET 0x808 |
| 362 | #define GPKPUD_OFFSET 0x80C |
| 363 | #define GPLCON0_OFFSET 0x810 |
| 364 | #define GPLCON1_OFFSET 0x814 |
| 365 | #define GPLDAT_OFFSET 0x818 |
| 366 | #define GPLPUD_OFFSET 0x81C |
| 367 | #define GPMCON_OFFSET 0x820 |
| 368 | #define GPMDAT_OFFSET 0x824 |
| 369 | #define GPMPUD_OFFSET 0x828 |
| 370 | #define GPNCON_OFFSET 0x830 |
| 371 | #define GPNDAT_OFFSET 0x834 |
| 372 | #define GPNPUD_OFFSET 0x838 |
| 373 | #define GPOCON_OFFSET 0x140 |
| 374 | #define GPODAT_OFFSET 0x144 |
| 375 | #define GPOPUD_OFFSET 0x148 |
| 376 | #define GPOCONSLP_OFFSET 0x14C |
| 377 | #define GPOPUDSLP_OFFSET 0x150 |
| 378 | #define GPPCON_OFFSET 0x160 |
| 379 | #define GPPDAT_OFFSET 0x164 |
| 380 | #define GPPPUD_OFFSET 0x168 |
| 381 | #define GPPCONSLP_OFFSET 0x16C |
| 382 | #define GPPPUDSLP_OFFSET 0x170 |
| 383 | #define GPQCON_OFFSET 0x180 |
| 384 | #define GPQDAT_OFFSET 0x184 |
| 385 | #define GPQPUD_OFFSET 0x188 |
| 386 | #define GPQCONSLP_OFFSET 0x18C |
| 387 | #define GPQPUDSLP_OFFSET 0x190 |
| 388 | |
| 389 | #define EINTPEND_OFFSET 0x924 |
| 390 | |
| 391 | #define GPACON_REG __REG(ELFIN_GPIO_BASE+GPACON_OFFSET) |
| 392 | #define GPADAT_REG __REG(ELFIN_GPIO_BASE+GPADAT_OFFSET) |
| 393 | #define GPAPUD_REG __REG(ELFIN_GPIO_BASE+GPAPUD_OFFSET) |
| 394 | #define GPACONSLP_REG __REG(ELFIN_GPIO_BASE+GPACONSLP_OFFSET) |
| 395 | #define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPAPUDSLP_OFFSET) |
| 396 | #define GPBCON_REG __REG(ELFIN_GPIO_BASE+GPBCON_OFFSET) |
| 397 | #define GPBDAT_REG __REG(ELFIN_GPIO_BASE+GPBDAT_OFFSET) |
| 398 | #define GPBPUD_REG __REG(ELFIN_GPIO_BASE+GPBPUD_OFFSET) |
| 399 | #define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE+GPBCONSLP_OFFSET) |
| 400 | #define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPBPUDSLP_OFFSET) |
| 401 | #define GPCCON_REG __REG(ELFIN_GPIO_BASE+GPCCON_OFFSET) |
| 402 | #define GPCDAT_REG __REG(ELFIN_GPIO_BASE+GPCDAT_OFFSET) |
| 403 | #define GPCPUD_REG __REG(ELFIN_GPIO_BASE+GPCPUD_OFFSET) |
| 404 | #define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE+GPCCONSLP_OFFSET) |
| 405 | #define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPCPUDSLP_OFFSET) |
| 406 | #define GPDCON_REG __REG(ELFIN_GPIO_BASE+GPDCON_OFFSET) |
| 407 | #define GPDDAT_REG __REG(ELFIN_GPIO_BASE+GPDDAT_OFFSET) |
| 408 | #define GPDPUD_REG __REG(ELFIN_GPIO_BASE+GPDPUD_OFFSET) |
| 409 | #define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE+GPDCONSLP_OFFSET) |
| 410 | #define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPDPUDSLP_OFFSET) |
| 411 | #define GPECON_REG __REG(ELFIN_GPIO_BASE+GPECON_OFFSET) |
| 412 | #define GPEDAT_REG __REG(ELFIN_GPIO_BASE+GPEDAT_OFFSET) |
| 413 | #define GPEPUD_REG __REG(ELFIN_GPIO_BASE+GPEPUD_OFFSET) |
| 414 | #define GPECONSLP_REG __REG(ELFIN_GPIO_BASE+GPECONSLP_OFFSET) |
| 415 | #define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPEPUDSLP_OFFSET) |
| 416 | #define GPFCON_REG __REG(ELFIN_GPIO_BASE+GPFCON_OFFSET) |
| 417 | #define GPFDAT_REG __REG(ELFIN_GPIO_BASE+GPFDAT_OFFSET) |
| 418 | #define GPFPUD_REG __REG(ELFIN_GPIO_BASE+GPFPUD_OFFSET) |
| 419 | #define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE+GPFCONSLP_OFFSET) |
| 420 | #define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPFPUDSLP_OFFSET) |
| 421 | #define GPGCON_REG __REG(ELFIN_GPIO_BASE+GPGCON_OFFSET) |
| 422 | #define GPGDAT_REG __REG(ELFIN_GPIO_BASE+GPGDAT_OFFSET) |
| 423 | #define GPGPUD_REG __REG(ELFIN_GPIO_BASE+GPGPUD_OFFSET) |
| 424 | #define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE+GPGCONSLP_OFFSET) |
| 425 | #define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPGPUDSLP_OFFSET) |
| 426 | #define GPHCON0_REG __REG(ELFIN_GPIO_BASE+GPHCON0_OFFSET) |
| 427 | #define GPHCON1_REG __REG(ELFIN_GPIO_BASE+GPHCON1_OFFSET) |
| 428 | #define GPHDAT_REG __REG(ELFIN_GPIO_BASE+GPHDAT_OFFSET) |
| 429 | #define GPHPUD_REG __REG(ELFIN_GPIO_BASE+GPHPUD_OFFSET) |
| 430 | #define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE+GPHCONSLP_OFFSET) |
| 431 | #define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPHPUDSLP_OFFSET) |
| 432 | #define GPICON_REG __REG(ELFIN_GPIO_BASE+GPICON_OFFSET) |
| 433 | #define GPIDAT_REG __REG(ELFIN_GPIO_BASE+GPIDAT_OFFSET) |
| 434 | #define GPIPUD_REG __REG(ELFIN_GPIO_BASE+GPIPUD_OFFSET) |
| 435 | #define GPICONSLP_REG __REG(ELFIN_GPIO_BASE+GPICONSLP_OFFSET) |
| 436 | #define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPIPUDSLP_OFFSET) |
| 437 | #define GPJCON_REG __REG(ELFIN_GPIO_BASE+GPJCON_OFFSET) |
| 438 | #define GPJDAT_REG __REG(ELFIN_GPIO_BASE+GPJDAT_OFFSET) |
| 439 | #define GPJPUD_REG __REG(ELFIN_GPIO_BASE+GPJPUD_OFFSET) |
| 440 | #define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE+GPJCONSLP_OFFSET) |
| 441 | #define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPJPUDSLP_OFFSET) |
| 442 | #define GPKCON0_REG __REG(ELFIN_GPIO_BASE+GPKCON0_OFFSET) |
| 443 | #define GPKCON1_REG __REG(ELFIN_GPIO_BASE+GPKCON1_OFFSET) |
| 444 | #define GPKDAT_REG __REG(ELFIN_GPIO_BASE+GPKDAT_OFFSET) |
| 445 | #define GPKPUD_REG __REG(ELFIN_GPIO_BASE+GPKPUD_OFFSET) |
| 446 | #define GPLCON0_REG __REG(ELFIN_GPIO_BASE+GPLCON0_OFFSET) |
| 447 | #define GPLCON1_REG __REG(ELFIN_GPIO_BASE+GPLCON1_OFFSET) |
| 448 | #define GPLDAT_REG __REG(ELFIN_GPIO_BASE+GPLDAT_OFFSET) |
| 449 | #define GPLPUD_REG __REG(ELFIN_GPIO_BASE+GPLPUD_OFFSET) |
| 450 | #define GPMCON_REG __REG(ELFIN_GPIO_BASE+GPMCON_OFFSET) |
| 451 | #define GPMDAT_REG __REG(ELFIN_GPIO_BASE+GPMDAT_OFFSET) |
| 452 | #define GPMPUD_REG __REG(ELFIN_GPIO_BASE+GPMPUD_OFFSET) |
| 453 | #define GPNCON_REG __REG(ELFIN_GPIO_BASE+GPNCON_OFFSET) |
| 454 | #define GPNDAT_REG __REG(ELFIN_GPIO_BASE+GPNDAT_OFFSET) |
| 455 | #define GPNPUD_REG __REG(ELFIN_GPIO_BASE+GPNPUD_OFFSET) |
| 456 | #define GPOCON_REG __REG(ELFIN_GPIO_BASE+GPOCON_OFFSET) |
| 457 | #define GPODAT_REG __REG(ELFIN_GPIO_BASE+GPODAT_OFFSET) |
| 458 | #define GPOPUD_REG __REG(ELFIN_GPIO_BASE+GPOPUD_OFFSET) |
| 459 | #define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE+GPOCONSLP_OFFSET) |
| 460 | #define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPOPUDSLP_OFFSET) |
| 461 | #define GPPCON_REG __REG(ELFIN_GPIO_BASE+GPPCON_OFFSET) |
| 462 | #define GPPDAT_REG __REG(ELFIN_GPIO_BASE+GPPDAT_OFFSET) |
| 463 | #define GPPPUD_REG __REG(ELFIN_GPIO_BASE+GPPPUD_OFFSET) |
| 464 | #define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE+GPPCONSLP_OFFSET) |
| 465 | #define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPPPUDSLP_OFFSET) |
| 466 | #define GPQCON_REG __REG(ELFIN_GPIO_BASE+GPQCON_OFFSET) |
| 467 | #define GPQDAT_REG __REG(ELFIN_GPIO_BASE+GPQDAT_OFFSET) |
| 468 | #define GPQPUD_REG __REG(ELFIN_GPIO_BASE+GPQPUD_OFFSET) |
| 469 | #define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE+GPQCONSLP_OFFSET) |
| 470 | #define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPQPUDSLP_OFFSET) |
| 471 | |
| 472 | #define GPACON (ELFIN_GPIO_BASE+GPACON_OFFSET) |
| 473 | #define GPADAT (ELFIN_GPIO_BASE+GPADAT_OFFSET) |
| 474 | #define GPAPUD (ELFIN_GPIO_BASE+GPAPUD_OFFSET) |
| 475 | #define GPACONSLP (ELFIN_GPIO_BASE+GPACONSLP_OFFSET) |
| 476 | #define GPAPUDSLP (ELFIN_GPIO_BASE+GPAPUDSLP_OFFSET) |
| 477 | #define GPBCON (ELFIN_GPIO_BASE+GPBCON_OFFSET) |
| 478 | #define GPBDAT (ELFIN_GPIO_BASE+GPBDAT_OFFSET) |
| 479 | #define GPBPUD (ELFIN_GPIO_BASE+GPBPUD_OFFSET) |
| 480 | #define GPBCONSLP (ELFIN_GPIO_BASE+GPBCONSLP_OFFSET) |
| 481 | #define GPBPUDSLP (ELFIN_GPIO_BASE+GPBPUDSLP_OFFSET) |
| 482 | #define GPCCON (ELFIN_GPIO_BASE+GPCCON_OFFSET) |
| 483 | #define GPCDAT (ELFIN_GPIO_BASE+GPCDAT_OFFSET) |
| 484 | #define GPCPUD (ELFIN_GPIO_BASE+GPCPUD_OFFSET) |
| 485 | #define GPCCONSLP (ELFIN_GPIO_BASE+GPCCONSLP_OFFSET) |
| 486 | #define GPCPUDSLP (ELFIN_GPIO_BASE+GPCPUDSLP_OFFSET) |
| 487 | #define GPDCON (ELFIN_GPIO_BASE+GPDCON_OFFSET) |
| 488 | #define GPDDAT (ELFIN_GPIO_BASE+GPDDAT_OFFSET) |
| 489 | #define GPDPUD (ELFIN_GPIO_BASE+GPDPUD_OFFSET) |
| 490 | #define GPDCONSLP (ELFIN_GPIO_BASE+GPDCONSLP_OFFSET) |
| 491 | #define GPDPUDSLP (ELFIN_GPIO_BASE+GPDPUDSLP_OFFSET) |
| 492 | #define GPECON (ELFIN_GPIO_BASE+GPECON_OFFSET) |
| 493 | #define GPEDAT (ELFIN_GPIO_BASE+GPEDAT_OFFSET) |
| 494 | #define GPEPUD (ELFIN_GPIO_BASE+GPEPUD_OFFSET) |
| 495 | #define GPECONSLP (ELFIN_GPIO_BASE+GPECONSLP_OFFSET) |
| 496 | #define GPEPUDSLP (ELFIN_GPIO_BASE+GPEPUDSLP_OFFSET) |
| 497 | #define GPFCON (ELFIN_GPIO_BASE+GPFCON_OFFSET) |
| 498 | #define GPFDAT (ELFIN_GPIO_BASE+GPFDAT_OFFSET) |
| 499 | #define GPFPUD (ELFIN_GPIO_BASE+GPFPUD_OFFSET) |
| 500 | #define GPFCONSLP (ELFIN_GPIO_BASE+GPFCONSLP_OFFSET) |
| 501 | #define GPFPUDSLP (ELFIN_GPIO_BASE+GPFPUDSLP_OFFSET) |
| 502 | #define GPGCON (ELFIN_GPIO_BASE+GPGCON_OFFSET) |
| 503 | #define GPGDAT (ELFIN_GPIO_BASE+GPGDAT_OFFSET) |
| 504 | #define GPGPUD (ELFIN_GPIO_BASE+GPGPUD_OFFSET) |
| 505 | #define GPGCONSLP (ELFIN_GPIO_BASE+GPGCONSLP_OFFSET) |
| 506 | #define GPGPUDSLP (ELFIN_GPIO_BASE+GPGPUDSLP_OFFSET) |
| 507 | #define GPHCON0 (ELFIN_GPIO_BASE+GPHCON0_OFFSET) |
| 508 | #define GPHCON1 (ELFIN_GPIO_BASE+GPHCON1_OFFSET) |
| 509 | #define GPHDAT (ELFIN_GPIO_BASE+GPHDAT_OFFSET) |
| 510 | #define GPHPUD (ELFIN_GPIO_BASE+GPHPUD_OFFSET) |
| 511 | #define GPHCONSLP (ELFIN_GPIO_BASE+GPHCONSLP_OFFSET) |
| 512 | #define GPHPUDSLP (ELFIN_GPIO_BASE+GPHPUDSLP_OFFSET) |
| 513 | #define GPICON (ELFIN_GPIO_BASE+GPICON_OFFSET) |
| 514 | #define GPIDAT (ELFIN_GPIO_BASE+GPIDAT_OFFSET) |
| 515 | #define GPIPUD (ELFIN_GPIO_BASE+GPIPUD_OFFSET) |
| 516 | #define GPICONSLP (ELFIN_GPIO_BASE+GPICONSLP_OFFSET) |
| 517 | #define GPIPUDSLP (ELFIN_GPIO_BASE+GPIPUDSLP_OFFSET) |
| 518 | #define GPJCON (ELFIN_GPIO_BASE+GPJCON_OFFSET) |
| 519 | #define GPJDAT (ELFIN_GPIO_BASE+GPJDAT_OFFSET) |
| 520 | #define GPJPUD (ELFIN_GPIO_BASE+GPJPUD_OFFSET) |
| 521 | #define GPJCONSLP (ELFIN_GPIO_BASE+GPJCONSLP_OFFSET) |
| 522 | #define GPJPUDSLP (ELFIN_GPIO_BASE+GPJPUDSLP_OFFSET) |
| 523 | #define GPKCON0 (ELFIN_GPIO_BASE+GPKCON0_OFFSET) |
| 524 | #define GPKCON1 (ELFIN_GPIO_BASE+GPKCON1_OFFSET) |
| 525 | #define GPKDAT (ELFIN_GPIO_BASE+GPKDAT_OFFSET) |
| 526 | #define GPKPUD (ELFIN_GPIO_BASE+GPKPUD_OFFSET) |
| 527 | #define GPLCON0 (ELFIN_GPIO_BASE+GPLCON0_OFFSET) |
| 528 | #define GPLCON1 (ELFIN_GPIO_BASE+GPLCON1_OFFSET) |
| 529 | #define GPLDAT (ELFIN_GPIO_BASE+GPLDAT_OFFSET) |
| 530 | #define GPLPUD (ELFIN_GPIO_BASE+GPLPUD_OFFSET) |
| 531 | #define GPMCON (ELFIN_GPIO_BASE+GPMCON_OFFSET) |
| 532 | #define GPMDAT (ELFIN_GPIO_BASE+GPMDAT_OFFSET) |
| 533 | #define GPMPUD (ELFIN_GPIO_BASE+GPMPUD_OFFSET) |
| 534 | #define GPNCON (ELFIN_GPIO_BASE+GPNCON_OFFSET) |
| 535 | #define GPNDAT (ELFIN_GPIO_BASE+GPNDAT_OFFSET) |
| 536 | #define GPNPUD (ELFIN_GPIO_BASE+GPNPUD_OFFSET) |
| 537 | #define GPOCON (ELFIN_GPIO_BASE+GPOCON_OFFSET) |
| 538 | #define GPODAT (ELFIN_GPIO_BASE+GPODAT_OFFSET) |
| 539 | #define GPOPUD (ELFIN_GPIO_BASE+GPOPUD_OFFSET) |
| 540 | #define GPOCONSLP (ELFIN_GPIO_BASE+GPOCONSLP_OFFSET) |
| 541 | #define GPOPUDSLP (ELFIN_GPIO_BASE+GPOPUDSLP_OFFSET) |
| 542 | #define GPPCON (ELFIN_GPIO_BASE+GPPCON_OFFSET) |
| 543 | #define GPPDAT (ELFIN_GPIO_BASE+GPPDAT_OFFSET) |
| 544 | #define GPPPUD (ELFIN_GPIO_BASE+GPPPUD_OFFSET) |
| 545 | #define GPPCONSLP (ELFIN_GPIO_BASE+GPPCONSLP_OFFSET) |
| 546 | #define GPPPUDSLP (ELFIN_GPIO_BASE+GPPPUDSLP_OFFSET) |
| 547 | #define GPQCON (ELFIN_GPIO_BASE+GPQCON_OFFSET) |
| 548 | #define GPQDAT (ELFIN_GPIO_BASE+GPQDAT_OFFSET) |
| 549 | #define GPQPUD (ELFIN_GPIO_BASE+GPQPUD_OFFSET) |
| 550 | #define GPQCONSLP (ELFIN_GPIO_BASE+GPQCONSLP_OFFSET) |
| 551 | #define GPQPUDSLP (ELFIN_GPIO_BASE+GPQPUDSLP_OFFSET) |
| 552 | |
| 553 | /* |
| 554 | * Bus Matrix |
| 555 | */ |
| 556 | #define ELFIN_MEM_SYS_CFG 0x7e00f120 |
| 557 | |
| 558 | |
| 559 | |
| 560 | /* |
| 561 | * Memory controller |
| 562 | */ |
| 563 | #define ELFIN_SROM_BASE 0x70000000 |
| 564 | |
| 565 | #define SROM_BW_REG __REG(ELFIN_SROM_BASE+0x0) |
| 566 | #define SROM_BC0_REG __REG(ELFIN_SROM_BASE+0x4) |
| 567 | #define SROM_BC1_REG __REG(ELFIN_SROM_BASE+0x8) |
| 568 | #define SROM_BC2_REG __REG(ELFIN_SROM_BASE+0xC) |
| 569 | #define SROM_BC3_REG __REG(ELFIN_SROM_BASE+0x10) |
| 570 | #define SROM_BC4_REG __REG(ELFIN_SROM_BASE+0x14) |
| 571 | #define SROM_BC5_REG __REG(ELFIN_SROM_BASE+0x18) |
| 572 | |
| 573 | |
| 574 | |
| 575 | /* |
| 576 | * SDRAM Controller |
| 577 | */ |
| 578 | #define ELFIN_DMC0_BASE 0x7e000000 |
| 579 | #define ELFIN_DMC1_BASE 0x7e001000 |
| 580 | |
| 581 | #define INDEX_DMC_MEMC_STATUS (0x00) |
| 582 | #define INDEX_DMC_MEMC_CMD (0x04) |
| 583 | #define INDEX_DMC_DIRECT_CMD (0x08) |
| 584 | #define INDEX_DMC_MEMORY_CFG (0x0C) |
| 585 | #define INDEX_DMC_REFRESH_PRD (0x10) |
| 586 | #define INDEX_DMC_CAS_LATENCY (0x14) |
| 587 | #define INDEX_DMC_T_DQSS (0x18) |
| 588 | #define INDEX_DMC_T_MRD (0x1C) |
| 589 | #define INDEX_DMC_T_RAS (0x20) |
| 590 | #define INDEX_DMC_T_RC (0x24) |
| 591 | #define INDEX_DMC_T_RCD (0x28) |
| 592 | #define INDEX_DMC_T_RFC (0x2C) |
| 593 | #define INDEX_DMC_T_RP (0x30) |
| 594 | #define INDEX_DMC_T_RRD (0x34) |
| 595 | #define INDEX_DMC_T_WR (0x38) |
| 596 | #define INDEX_DMC_T_WTR (0x3C) |
| 597 | #define INDEX_DMC_T_XP (0x40) |
| 598 | #define INDEX_DMC_T_XSR (0x44) |
| 599 | #define INDEX_DMC_T_ESR (0x48) |
| 600 | #define INDEX_DMC_MEMORY_CFG2 (0x4C) |
| 601 | #define INDEX_DMC_CHIP_0_CFG (0x200) |
| 602 | #define INDEX_DMC_CHIP_1_CFG (0x204) |
| 603 | #define INDEX_DMC_CHIP_2_CFG (0x208) |
| 604 | #define INDEX_DMC_CHIP_3_CFG (0x20C) |
| 605 | #define INDEX_DMC_USER_STATUS (0x300) |
| 606 | #define INDEX_DMC_USER_CONFIG (0x304) |
| 607 | |
| 608 | /* |
| 609 | * Memory Chip direct command |
| 610 | */ |
| 611 | #define DMC_NOP0 0x0c0000 |
| 612 | #define DMC_NOP1 0x1c0000 |
| 613 | #define DMC_PA0 0x000000 //Precharge all |
| 614 | #define DMC_PA1 0x100000 |
| 615 | #define DMC_AR0 0x040000 //Autorefresh |
| 616 | #define DMC_AR1 0x140000 |
| 617 | #define DMC_SDR_MR0 0x080032 //MRS, CAS 3, Burst Length 4 |
| 618 | #define DMC_SDR_MR1 0x180032 |
| 619 | #define DMC_DDR_MR0 0x080162 |
| 620 | #define DMC_DDR_MR1 0x180162 |
| 621 | #define DMC_mDDR_MR0 0x080032 //CAS 3, Burst Length 4 |
| 622 | #define DMC_mDDR_MR1 0x180032 |
| 623 | #define DMC_mSDR_EMR0 0x0a0000 //EMRS, DS:Full, PASR:Full Array |
| 624 | #define DMC_mSDR_EMR1 0x1a0000 |
| 625 | #define DMC_DDR_EMR0 0x090000 |
| 626 | #define DMC_DDR_EMR1 0x190000 |
| 627 | #define DMC_mDDR_EMR0 0x0a0000 // DS:Full, PASR:Full Array |
| 628 | #define DMC_mDDR_EMR1 0x1a0000 |
| 629 | |
| 630 | |
| 631 | /**************************************************************** |
| 632 | Definitions for memory configuration |
| 633 | Set memory configuration |
| 634 | active_chips = 1'b0 (1 chip) |
| 635 | qos_master_chip = 3'b000(ARID[3:0]) |
| 636 | memory burst = 3'b010(burst 4) |
| 637 | stop_mem_clock = 1'b0(disable dynamical stop) |
| 638 | auto_power_down = 1'b0(disable auto power-down mode) |
| 639 | power_down_prd = 6'b00_0000(0 cycle for auto power-down) |
| 640 | ap_bit = 1'b0 (bit position of auto-precharge is 10) |
| 641 | row_bits = 3'b010(# row address 13) |
| 642 | column_bits = 3'b010(# column address 10 ) |
| 643 | |
| 644 | Set user configuration |
| 645 | 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR |
| 646 | |
| 647 | Set chip select for chip [n] |
| 648 | row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff |
| 649 | CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] |
| 650 | ******************************************************************/ |
| 651 | |
| 652 | /* |
| 653 | * HS MMC Interface |
| 654 | */ |
| 655 | #define ELFIN_HSMMC_BASE 0x7C200000 |
| 656 | |
| 657 | #define HM_SYSAD (0x00) |
| 658 | #define HM_BLKSIZE (0x04) |
| 659 | #define HM_BLKCNT (0x06) |
| 660 | #define HM_ARGUMENT (0x08) |
| 661 | #define HM_TRNMOD (0x0c) |
| 662 | #define HM_CMDREG (0x0e) |
| 663 | #define HM_RSPREG0 (0x10) |
| 664 | #define HM_RSPREG1 (0x14) |
| 665 | #define HM_RSPREG2 (0x18) |
| 666 | #define HM_RSPREG3 (0x1c) |
| 667 | #define HM_BDATA (0x20) |
| 668 | #define HM_PRNSTS (0x24) |
| 669 | #define HM_HOSTCTL (0x28) |
| 670 | #define HM_PWRCON (0x29) |
| 671 | #define HM_BLKGAP (0x2a) |
| 672 | #define HM_WAKCON (0x2b) |
| 673 | #define HM_CLKCON (0x2c) |
| 674 | #define HM_TIMEOUTCON (0x2e) |
| 675 | #define HM_SWRST (0x2f) |
| 676 | #define HM_NORINTSTS (0x30) |
| 677 | #define HM_ERRINTSTS (0x32) |
| 678 | #define HM_NORINTSTSEN (0x34) |
| 679 | #define HM_ERRINTSTSEN (0x36) |
| 680 | #define HM_NORINTSIGEN (0x38) |
| 681 | #define HM_ERRINTSIGEN (0x3a) |
| 682 | #define HM_ACMD12ERRSTS (0x3c) |
| 683 | #define HM_CAPAREG (0x40) |
| 684 | #define HM_MAXCURR (0x48) |
| 685 | #define HM_CONTROL2 (0x80) |
| 686 | #define HM_CONTROL3 (0x84) |
| 687 | #define HM_CONTROL4 (0x8c) |
| 688 | #define HM_HCVER (0xfe) |
| 689 | |
| 690 | /* |
| 691 | * Nand flash controller |
| 692 | */ |
| 693 | #define ELFIN_NAND_BASE 0x70200000 |
| 694 | |
| 695 | #define NFCONF_OFFSET 0x00 |
| 696 | #define NFCONT_OFFSET 0x04 |
| 697 | #define NFCMMD_OFFSET 0x08 |
| 698 | #define NFADDR_OFFSET 0x0c |
| 699 | #define NFDATA_OFFSET 0x10 |
| 700 | #define NFMECCDATA0_OFFSET 0x14 |
| 701 | #define NFMECCDATA1_OFFSET 0x18 |
| 702 | #define NFSECCDATA0_OFFSET 0x1c |
| 703 | #define NFSBLK_OFFSET 0x20 |
| 704 | #define NFEBLK_OFFSET 0x24 |
| 705 | #define NFSTAT_OFFSET 0x28 |
| 706 | #define NFESTAT0_OFFSET 0x2c |
| 707 | #define NFESTAT1_OFFSET 0x30 |
| 708 | #define NFMECC0_OFFSET 0x34 |
| 709 | #define NFMECC1_OFFSET 0x38 |
| 710 | #define NFSECC_OFFSET 0x3c |
| 711 | #define NFMLCBITPT_OFFSET 0x40 |
| 712 | #define NF8ECCERR0_OFFSET 0x44 |
| 713 | #define NF8ECCERR1_OFFSET 0x48 |
| 714 | #define NF8ECCERR2_OFFSET 0x4c |
| 715 | #define NFM8ECC0_OFFSET 0x50 |
| 716 | #define NFM8ECC1_OFFSET 0x54 |
| 717 | #define NFM8ECC2_OFFSET 0x58 |
| 718 | #define NFM8ECC3_OFFSET 0x5c |
| 719 | #define NFMLC8BITPT0_OFFSET 0x60 |
| 720 | #define NFMLC8BITPT1_OFFSET 0x64 |
| 721 | |
| 722 | #define NFCONF (ELFIN_NAND_BASE+NFCONF_OFFSET) |
| 723 | #define NFCONT (ELFIN_NAND_BASE+NFCONT_OFFSET) |
| 724 | #define NFCMMD (ELFIN_NAND_BASE+NFCMMD_OFFSET) |
| 725 | #define NFADDR (ELFIN_NAND_BASE+NFADDR_OFFSET) |
| 726 | #define NFDATA (ELFIN_NAND_BASE+NFDATA_OFFSET) |
| 727 | #define NFMECCDATA0 (ELFIN_NAND_BASE+NFMECCDATA0_OFFSET) |
| 728 | #define NFMECCDATA1 (ELFIN_NAND_BASE+NFMECCDATA1_OFFSET) |
| 729 | #define NFSECCDATA0 (ELFIN_NAND_BASE+NFSECCDATA0_OFFSET) |
| 730 | #define NFSBLK (ELFIN_NAND_BASE+NFSBLK_OFFSET) |
| 731 | #define NFEBLK (ELFIN_NAND_BASE+NFEBLK_OFFSET) |
| 732 | #define NFSTAT (ELFIN_NAND_BASE+NFSTAT_OFFSET) |
| 733 | #define NFESTAT0 (ELFIN_NAND_BASE+NFESTAT0_OFFSET) |
| 734 | #define NFESTAT1 (ELFIN_NAND_BASE+NFESTAT1_OFFSET) |
| 735 | #define NFMECC0 (ELFIN_NAND_BASE+NFMECC0_OFFSET) |
| 736 | #define NFMECC1 (ELFIN_NAND_BASE+NFMECC1_OFFSET) |
| 737 | #define NFSECC (ELFIN_NAND_BASE+NFSECC_OFFSET) |
| 738 | #define NFMLCBITPT (ELFIN_NAND_BASE+NFMLCBITPT_OFFSET) |
| 739 | #define NF8ECCERR0 (ELFIN_NAND_BASE+NF8ECCERR0_OFFSET) |
| 740 | #define NF8ECCERR1 (ELFIN_NAND_BASE+NF8ECCERR1_OFFSET) |
| 741 | #define NF8ECCERR2 (ELFIN_NAND_BASE+NF8ECCERR2_OFFSET) |
| 742 | #define NFM8ECC0 (ELFIN_NAND_BASE+NFM8ECC0_OFFSET) |
| 743 | #define NFM8ECC1 (ELFIN_NAND_BASE+NFM8ECC1_OFFSET) |
| 744 | #define NFM8ECC2 (ELFIN_NAND_BASE+NFM8ECC2_OFFSET) |
| 745 | #define NFM8ECC3 (ELFIN_NAND_BASE+NFM8ECC3_OFFSET) |
| 746 | #define NFMLC8BITPT0 (ELFIN_NAND_BASE+NFMLC8BITPT0_OFFSET) |
| 747 | #define NFMLC8BITPT1 (ELFIN_NAND_BASE+NFMLC8BITPT1_OFFSET) |
| 748 | |
| 749 | #define NFCONF_REG __REG(ELFIN_NAND_BASE+NFCONF_OFFSET) |
| 750 | #define NFCONT_REG __REG(ELFIN_NAND_BASE+NFCONT_OFFSET) |
| 751 | #define NFCMD_REG __REG(ELFIN_NAND_BASE+NFCMMD_OFFSET) |
| 752 | #define NFADDR_REG __REG(ELFIN_NAND_BASE+NFADDR_OFFSET) |
| 753 | #define NFDATA_REG __REG(ELFIN_NAND_BASE+NFDATA_OFFSET) |
| 754 | #define NFDATA8_REG __REGb(ELFIN_NAND_BASE+NFDATA_OFFSET) |
| 755 | #define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE+NFMECCDATA0_OFFSET) |
| 756 | #define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE+NFMECCDATA1_OFFSET) |
| 757 | #define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE+NFSECCDATA0_OFFSET) |
| 758 | #define NFSBLK_REG __REG(ELFIN_NAND_BASE+NFSBLK_OFFSET) |
| 759 | #define NFEBLK_REG __REG(ELFIN_NAND_BASE+NFEBLK_OFFSET) |
| 760 | #define NFSTAT_REG __REG(ELFIN_NAND_BASE+NFSTAT_OFFSET) |
| 761 | #define NFESTAT0_REG __REG(ELFIN_NAND_BASE+NFESTAT0_OFFSET) |
| 762 | #define NFESTAT1_REG __REG(ELFIN_NAND_BASE+NFESTAT1_OFFSET) |
| 763 | #define NFMECC0_REG __REG(ELFIN_NAND_BASE+NFMECC0_OFFSET) |
| 764 | #define NFMECC1_REG __REG(ELFIN_NAND_BASE+NFMECC1_OFFSET) |
| 765 | #define NFSECC_REG __REG(ELFIN_NAND_BASE+NFSECC_OFFSET) |
| 766 | #define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE+NFMLCBITPT_OFFSET) |
| 767 | |
| 768 | #define NFCONF_ECC_MLC (1<<24) |
| 769 | #define NFCONT_ECC_ENC (1<<18) |
| 770 | #define NFCONT_WP (1<<16) |
| 771 | #define NFCONT_MECCLOCK (1<<7) |
| 772 | #define NFCONT_SECCLOCK (1<<6) |
| 773 | #define NFCONT_INITMECC (1<<5) |
| 774 | #define NFCONT_INITSECC (1<<4) |
| 775 | #define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) |
| 776 | #define NFCONT_CS_ALT (1<<1) |
| 777 | #define NFCONT_CS (1<<1) |
| 778 | #define NFSTAT_ECCENCDONE (1<<7) |
| 779 | #define NFSTAT_ECCDECDONE (1<<6) |
| 780 | #define NFSTAT_RnB (1<<0) |
| 781 | #define NFESTAT0_ECCBUSY (1<<31) |
| 782 | |
| 783 | |
| 784 | |
| 785 | /************************************************************* |
| 786 | * OneNAND Controller |
| 787 | *************************************************************/ |
| 788 | |
| 789 | /* |
| 790 | * S3C6400 SFRs |
| 791 | */ |
| 792 | #define ONENAND_REG_MEM_CFG (0x000) |
| 793 | #define ONENAND_REG_BURST_LEN (0x010) |
| 794 | #define ONENAND_REG_MEM_RESET (0x020) |
| 795 | #define ONENAND_REG_INT_ERR_STAT (0x030) |
| 796 | #define ONENAND_REG_INT_ERR_MASK (0x040) |
| 797 | #define ONENAND_REG_INT_ERR_ACK (0x050) |
| 798 | #define ONENAND_REG_ECC_ERR_STAT (0x060) |
| 799 | #define ONENAND_REG_MANUFACT_ID (0x070) |
| 800 | #define ONENAND_REG_DEVICE_ID (0x080) |
| 801 | #define ONENAND_REG_DATA_BUF_SIZE (0x090) |
| 802 | #define ONENAND_REG_BOOT_BUF_SIZE (0x0A0) |
| 803 | #define ONENAND_REG_BUF_AMOUNT (0x0B0) |
| 804 | #define ONENAND_REG_TECH (0x0C0) |
| 805 | #define ONENAND_REG_FBA_WIDTH (0x0D0) |
| 806 | #define ONENAND_REG_FPA_WIDTH (0x0E0) |
| 807 | #define ONENAND_REG_FSA_WIDTH (0x0F0) |
| 808 | #define ONENAND_REG_REVISION (0x100) |
| 809 | #define ONENAND_REG_DATARAM0 (0x110) |
| 810 | #define ONENAND_REG_DATARAM1 (0x120) |
| 811 | #define ONENAND_REG_SYNC_MODE (0x130) |
| 812 | #define ONENAND_REG_TRANS_SPARE (0x140) |
| 813 | #define ONENAND_REG_LOCK_BIT (0x150) |
| 814 | #define ONENAND_REG_DBS_DFS_WIDTH (0x160) |
| 815 | #define ONENAND_REG_PAGE_CNT (0x170) |
| 816 | #define ONENAND_REG_ERR_PAGE_ADDR (0x180) |
| 817 | #define ONENAND_REG_BURST_RD_LAT (0x190) |
| 818 | #define ONENAND_REG_INT_PIN_ENABLE (0x1A0) |
| 819 | #define ONENAND_REG_INT_MON_CYC (0x1B0) |
| 820 | #define ONENAND_REG_ACC_CLOCK (0x1C0) |
| 821 | #define ONENAND_REG_SLOW_RD_PATH (0x1D0) |
| 822 | #define ONENAND_REG_ERR_BLK_ADDR (0x1E0) |
| 823 | #define ONENAND_REG_FLASH_VER_ID (0x1F0) |
| 824 | #define ONENAND_REG_FLASH_AUX_CNTRL (0x300) |
| 825 | |
| 826 | /* |
| 827 | * S3C6400 SFR values |
| 828 | */ |
| 829 | #define ONENAND_MEM_CFG_SYNC_READ (1 << 15) |
| 830 | #define ONENAND_MEM_CFG_BRL_7 (7 << 12) |
| 831 | #define ONENAND_MEM_CFG_BRL_6 (6 << 12) |
| 832 | #define ONENAND_MEM_CFG_BRL_5 (5 << 12) |
| 833 | #define ONENAND_MEM_CFG_BRL_4 (4 << 12) |
| 834 | #define ONENAND_MEM_CFG_BRL_3 (3 << 12) |
| 835 | #define ONENAND_MEM_CFG_BRL_10 (2 << 12) |
| 836 | #define ONENAND_MEM_CFG_BRL_9 (1 << 12) |
| 837 | #define ONENAND_MEM_CFG_BRL_8 (0 << 12) |
| 838 | #define ONENAND_MEM_CFG_BRL_SHIFT (12) |
| 839 | #define ONENAND_MEM_CFG_BL_1K (5 << 9) |
| 840 | #define ONENAND_MEM_CFG_BL_32 (4 << 9) |
| 841 | #define ONENAND_MEM_CFG_BL_16 (3 << 9) |
| 842 | #define ONENAND_MEM_CFG_BL_8 (2 << 9) |
| 843 | #define ONENAND_MEM_CFG_BL_4 (1 << 9) |
| 844 | #define ONENAND_MEM_CFG_BL_CONT (0 << 9) |
| 845 | #define ONENAND_MEM_CFG_BL_SHIFT (9) |
| 846 | #define ONENAND_MEM_CFG_NO_ECC (1 << 8) |
| 847 | #define ONENAND_MEM_CFG_RDY_HIGH (1 << 7) |
| 848 | #define ONENAND_MEM_CFG_INT_HIGH (1 << 6) |
| 849 | #define ONENAND_MEM_CFG_IOBE (1 << 5) |
| 850 | #define ONENAND_MEM_CFG_RDY_CONF (1 << 4) |
| 851 | #define ONENAND_MEM_CFG_HF (1 << 2) |
| 852 | #define ONENAND_MEM_CFG_WM_SYNC (1 << 1) |
| 853 | #define ONENAND_MEM_CFG_BWPS_UNLOCK (1 << 0) |
| 854 | |
| 855 | #define ONENAND_BURST_LEN_CONT (0) |
| 856 | #define ONENAND_BURST_LEN_4 (4) |
| 857 | #define ONENAND_BURST_LEN_8 (8) |
| 858 | #define ONENAND_BURST_LEN_16 (16) |
| 859 | |
| 860 | #define ONENAND_MEM_RESET_WARM (0x1) |
| 861 | #define ONENAND_MEM_RESET_COLD (0x2) |
| 862 | #define ONENAND_MEM_RESET_HOT (0x3) |
| 863 | |
| 864 | #define ONENAND_INT_ERR_CACHE_OP_ERR (1 << 13) |
| 865 | #define ONENAND_INT_ERR_RST_CMP (1 << 12) |
| 866 | #define ONENAND_INT_ERR_RDY_ACT (1 << 11) |
| 867 | #define ONENAND_INT_ERR_INT_ACT (1 << 10) |
| 868 | #define ONENAND_INT_ERR_UNSUP_CMD (1 << 9) |
| 869 | #define ONENAND_INT_ERR_LOCKED_BLK (1 << 8) |
| 870 | #define ONENAND_INT_ERR_BLK_RW_CMP (1 << 7) |
| 871 | #define ONENAND_INT_ERR_ERS_CMP (1 << 6) |
| 872 | #define ONENAND_INT_ERR_PGM_CMP (1 << 5) |
| 873 | #define ONENAND_INT_ERR_LOAD_CMP (1 << 4) |
| 874 | #define ONENAND_INT_ERR_ERS_FAIL (1 << 3) |
| 875 | #define ONENAND_INT_ERR_PGM_FAIL (1 << 2) |
| 876 | #define ONENAND_INT_ERR_INT_TO (1 << 1) |
| 877 | #define ONENAND_INT_ERR_LD_FAIL_ECC_ERR (1 << 0) |
| 878 | |
| 879 | #define ONENAND_DEVICE_DENSITY_SHIFT (4) |
| 880 | #define ONENAND_DEVICE_IS_DDP (1 << 3) |
| 881 | #define ONENAND_DEVICE_IS_DEMUX (1 << 2) |
| 882 | #define ONENAND_DEVICE_VCC_MASK (0x3) |
| 883 | #define ONENAND_DEVICE_DENSITY_128Mb (0x000) |
| 884 | #define ONENAND_DEVICE_DENSITY_256Mb (0x001) |
| 885 | #define ONENAND_DEVICE_DENSITY_512Mb (0x002) |
| 886 | #define ONENAND_DEVICE_DENSITY_1Gb (0x003) |
| 887 | #define ONENAND_DEVICE_DENSITY_2Gb (0x004) |
| 888 | #define ONENAND_DEVICE_DENSITY_4Gb (0x005) |
| 889 | |
| 890 | #define ONENAND_SYNC_MODE_RM_SYNC (1 << 1) |
| 891 | #define ONENAND_SYNC_MODE_WM_SYNC (1 << 0) |
| 892 | |
| 893 | #define ONENAND_TRANS_SPARE_TSRF_INC (1 << 0) |
| 894 | |
| 895 | #define ONENAND_INT_PIN_ENABLE (1 << 0) |
| 896 | |
| 897 | #define ONENAND_ACC_CLOCK_266_133 (0x5) |
| 898 | #define ONENAND_ACC_CLOCK_166_83 (0x3) |
| 899 | #define ONENAND_ACC_CLOCK_134_67 (0x3) |
| 900 | #define ONENAND_ACC_CLOCK_100_50 (0x2) |
| 901 | #define ONENAND_ACC_CLOCK_60_30 (0x2) |
| 902 | |
| 903 | #define ONENAND_FLASH_AUX_WD_DISABLE (1 << 0) |
| 904 | |
| 905 | /* |
| 906 | * Datain values for mapped commands |
| 907 | */ |
| 908 | #define ONENAND_DATAIN_ERASE_STATUS (0x00) |
| 909 | #define ONENAND_DATAIN_ERASE_MULTI (0x01) |
| 910 | #define ONENAND_DATAIN_ERASE_SINGLE (0x03) |
| 911 | #define ONENAND_DATAIN_ERASE_VERIFY (0x15) |
| 912 | #define ONENAND_DATAIN_UNLOCK_START (0x08) |
| 913 | #define ONENAND_DATAIN_UNLOCK_END (0x09) |
| 914 | #define ONENAND_DATAIN_LOCK_START (0x0A) |
| 915 | #define ONENAND_DATAIN_LOCK_END (0x0B) |
| 916 | #define ONENAND_DATAIN_LOCKTIGHT_START (0x0C) |
| 917 | #define ONENAND_DATAIN_LOCKTIGHT_END (0x0D) |
| 918 | #define ONENAND_DATAIN_UNLOCK_ALL (0x0E) |
| 919 | #define ONENAND_DATAIN_COPYBACK_SRC (0x1000) |
| 920 | #define ONENAND_DATAIN_COPYBACK_DST (0x2000) |
| 921 | #define ONENAND_DATAIN_ACCESS_OTP (0x12) |
| 922 | #define ONENAND_DATAIN_ACCESS_MAIN (0x14) |
| 923 | #define ONENAND_DATAIN_PIPELINE_READ (0x4000) |
| 924 | #define ONENAND_DATAIN_PIPELINE_WRITE (0x4100) |
| 925 | #define ONENAND_DATAIN_RMW_LOAD (0x10) |
| 926 | #define ONENAND_DATAIN_RMW_MODIFY (0x11) |
| 927 | |
| 928 | /* |
| 929 | * Device ID Register F001h (R) |
| 930 | */ |
| 931 | #define ONENAND_DEVICE_DENSITY_SHIFT (4) |
| 932 | #define ONENAND_DEVICE_IS_DDP (1 << 3) |
| 933 | #define ONENAND_DEVICE_IS_DEMUX (1 << 2) |
| 934 | #define ONENAND_DEVICE_VCC_MASK (0x3) |
| 935 | |
| 936 | /* |
| 937 | * Version ID Register F002h (R) |
| 938 | */ |
| 939 | #define ONENAND_VERSION_PROCESS_SHIFT (8) |
| 940 | |
| 941 | /* |
| 942 | * Start Address 1 F100h (R/W) |
| 943 | */ |
| 944 | #define ONENAND_DDP_SHIFT (15) |
| 945 | #define ONENAND_DDP_CHIP0 (0) |
| 946 | #define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT) |
| 947 | |
| 948 | /* |
| 949 | * Start Buffer Register F200h (R/W) |
| 950 | */ |
| 951 | #define ONENAND_BSA_MASK (0x03) |
| 952 | #define ONENAND_BSA_SHIFT (8) |
| 953 | #define ONENAND_BSA_BOOTRAM (0 << 2) |
| 954 | #define ONENAND_BSA_DATARAM0 (2 << 2) |
| 955 | #define ONENAND_BSA_DATARAM1 (3 << 2) |
| 956 | #define ONENAND_BSC_MASK (0x03) |
| 957 | |
| 958 | /* |
| 959 | * Command Register F220h (R/W) |
| 960 | */ |
| 961 | #define ONENAND_CMD_READ (0x00) |
| 962 | #define ONENAND_CMD_READOOB (0x13) |
| 963 | #define ONENAND_CMD_PROG (0x80) |
| 964 | #define ONENAND_CMD_PROGOOB (0x1A) |
| 965 | #define ONENAND_CMD_UNLOCK (0x23) |
| 966 | #define ONENAND_CMD_LOCK (0x2A) |
| 967 | #define ONENAND_CMD_LOCK_TIGHT (0x2C) |
| 968 | #define ONENAND_CMD_UNLOCK_ALL (0x27) |
| 969 | #define ONENAND_CMD_ERASE (0x94) |
| 970 | #define ONENAND_CMD_RESET (0xF0) |
| 971 | #define ONENAND_CMD_OTP_ACCESS (0x65) |
| 972 | #define ONENAND_CMD_READID (0x90) |
| 973 | #define ONENAND_CMD_STARTADDR1 (0xE0) |
| 974 | #define ONENAND_CMD_WP_STATUS (0xE1) |
| 975 | #define ONENAND_CMD_PIPELINE_READ (0x01) |
| 976 | #define ONENAND_CMD_PIPELINE_WRITE (0x81) |
| 977 | |
| 978 | /* |
| 979 | * Command Mapping for S3C6400 OneNAND Controller |
| 980 | */ |
| 981 | #define ONENAND_AHB_ADDR (0x20000000) |
| 982 | #define ONENAND_DUMMY_ADDR (0x20400000) |
| 983 | #define ONENAND_CMD_SHIFT (24) |
| 984 | #define ONENAND_CMD_MAP_00 (0x0) |
| 985 | #define ONENAND_CMD_MAP_01 (0x1) |
| 986 | #define ONENAND_CMD_MAP_10 (0x2) |
| 987 | #define ONENAND_CMD_MAP_11 (0x3) |
| 988 | #define ONENAND_CMD_MAP_FF (0xF) |
| 989 | |
| 990 | /* |
| 991 | * Mask for Mapping table |
| 992 | */ |
| 993 | #define ONENAND_MEM_ADDR_MASK (0xffffff) |
| 994 | #define ONENAND_DDP_SHIFT_1Gb (21) |
| 995 | #define ONENAND_DDP_SHIFT_2Gb (22) |
| 996 | #define ONENAND_DDP_SHIFT_4Gb (23) |
| 997 | #define ONENAND_FBA_SHIFT (12) |
| 998 | #define ONENAND_FPA_SHIFT (6) |
| 999 | #define ONENAND_FSA_SHIFT (4) |
| 1000 | #define ONENAND_FBA_MASK_128Mb (0xff) |
| 1001 | #define ONENAND_FBA_MASK_256Mb (0x1ff) |
| 1002 | #define ONENAND_FBA_MASK_512Mb (0x1ff) |
| 1003 | #define ONENAND_FBA_MASK_1Gb_DDP (0x1ff) |
| 1004 | #define ONENAND_FBA_MASK_1Gb (0x3ff) |
| 1005 | #define ONENAND_FBA_MASK_2Gb_DDP (0x3ff) |
| 1006 | #define ONENAND_FBA_MASK_2Gb (0x7ff) |
| 1007 | #define ONENAND_FBA_MASK_4Gb_DDP (0x7ff) |
| 1008 | #define ONENAND_FBA_MASK_4Gb (0xfff) |
| 1009 | #define ONENAND_FPA_MASK (0x3f) |
| 1010 | #define ONENAND_FSA_MASK (0x3) |
| 1011 | |
| 1012 | /* |
| 1013 | * System Configuration 1 Register F221h (R, R/W) |
| 1014 | */ |
| 1015 | #define ONENAND_SYS_CFG1_SYNC_READ (1 << 15) |
| 1016 | #define ONENAND_SYS_CFG1_BRL_7 (7 << 12) |
| 1017 | #define ONENAND_SYS_CFG1_BRL_6 (6 << 12) |
| 1018 | #define ONENAND_SYS_CFG1_BRL_5 (5 << 12) |
| 1019 | #define ONENAND_SYS_CFG1_BRL_4 (4 << 12) |
| 1020 | #define ONENAND_SYS_CFG1_BRL_3 (3 << 12) |
| 1021 | #define ONENAND_SYS_CFG1_BRL_10 (2 << 12) |
| 1022 | #define ONENAND_SYS_CFG1_BRL_9 (1 << 12) |
| 1023 | #define ONENAND_SYS_CFG1_BRL_8 (0 << 12) |
| 1024 | #define ONENAND_SYS_CFG1_BRL_SHIFT (12) |
| 1025 | #define ONENAND_SYS_CFG1_BL_32 (4 << 9) |
| 1026 | #define ONENAND_SYS_CFG1_BL_16 (3 << 9) |
| 1027 | #define ONENAND_SYS_CFG1_BL_8 (2 << 9) |
| 1028 | #define ONENAND_SYS_CFG1_BL_4 (1 << 9) |
| 1029 | #define ONENAND_SYS_CFG1_BL_CONT (0 << 9) |
| 1030 | #define ONENAND_SYS_CFG1_BL_SHIFT (9) |
| 1031 | #define ONENAND_SYS_CFG1_NO_ECC (1 << 8) |
| 1032 | #define ONENAND_SYS_CFG1_RDY (1 << 7) |
| 1033 | #define ONENAND_SYS_CFG1_INT (1 << 6) |
| 1034 | #define ONENAND_SYS_CFG1_IOBE (1 << 5) |
| 1035 | #define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) |
| 1036 | |
| 1037 | /* |
| 1038 | * Controller Status Register F240h (R) |
| 1039 | */ |
| 1040 | #define ONENAND_CTRL_ONGO (1 << 15) |
| 1041 | #define ONENAND_CTRL_LOCK (1 << 14) |
| 1042 | #define ONENAND_CTRL_LOAD (1 << 13) |
| 1043 | #define ONENAND_CTRL_PROGRAM (1 << 12) |
| 1044 | #define ONENAND_CTRL_ERASE (1 << 11) |
| 1045 | #define ONENAND_CTRL_ERROR (1 << 10) |
| 1046 | #define ONENAND_CTRL_RSTB (1 << 7) |
| 1047 | #define ONENAND_CTRL_OTP_L (1 << 6) |
| 1048 | #define ONENAND_CTRL_OTP_BL (1 << 5) |
| 1049 | |
| 1050 | /* |
| 1051 | * Interrupt Status Register F241h (R) |
| 1052 | */ |
| 1053 | #define ONENAND_INT_MASTER (1 << 15) |
| 1054 | #define ONENAND_INT_READ (1 << 7) |
| 1055 | #define ONENAND_INT_WRITE (1 << 6) |
| 1056 | #define ONENAND_INT_ERASE (1 << 5) |
| 1057 | #define ONENAND_INT_RESET (1 << 4) |
| 1058 | #define ONENAND_INT_CLEAR (0 << 0) |
| 1059 | |
| 1060 | /* |
| 1061 | * NAND Flash Write Protection Status Register F24Eh (R) |
| 1062 | */ |
| 1063 | #define ONENAND_WP_US (1 << 2) |
| 1064 | #define ONENAND_WP_LS (1 << 1) |
| 1065 | #define ONENAND_WP_LTS (1 << 0) |
| 1066 | |
| 1067 | /* |
| 1068 | * ECC Status Register FF00h (R) |
| 1069 | */ |
| 1070 | #define ONENAND_ECC_1BIT (1 << 0) |
| 1071 | #define ONENAND_ECC_1BIT_ALL (0x5555) |
| 1072 | #define ONENAND_ECC_2BIT (1 << 1) |
| 1073 | #define ONENAND_ECC_2BIT_ALL (0xAAAA) |
| 1074 | |
| 1075 | /* |
| 1076 | * One-Time Programmable (OTP) |
| 1077 | */ |
| 1078 | #define ONENAND_OTP_LOCK_OFFSET (14) |
| 1079 | |
| 1080 | /************************************************************* |
| 1081 | * End of OneNAND Controller |
| 1082 | *************************************************************/ |
| 1083 | |
| 1084 | |
| 1085 | /* |
| 1086 | * Interrupt |
| 1087 | */ |
| 1088 | #define ELFIN_VIC0_BASE_ADDR (0x71200000) |
| 1089 | #define ELFIN_VIC1_BASE_ADDR (0x71300000) |
| 1090 | #define oINTMOD (0x0C) // VIC INT SELECT (IRQ or FIQ) |
| 1091 | #define oINTUNMSK (0x10) // VIC INT EN (Unmask by writing 1) |
| 1092 | #define oINTMSK (0x14) // VIC INT EN CLEAR (Mask by writing 1) |
| 1093 | #define oINTSUBMSK (0x1C) // VIC SOFT INT CLEAR |
| 1094 | #define oVECTADDR (0xF00) // VIC ADDRESS |
| 1095 | |
| 1096 | |
| 1097 | |
| 1098 | /* |
| 1099 | * Watchdog timer |
| 1100 | */ |
| 1101 | #define ELFIN_WATCHDOG_BASE 0x7E004000 |
| 1102 | |
| 1103 | #define WTCON_REG __REG(0x7E004004) |
| 1104 | #define WTDAT_REG __REG(0x7E004008) |
| 1105 | #define WTCNT_REG __REG(0x7E00400C) |
| 1106 | |
| 1107 | |
| 1108 | |
| 1109 | /* |
| 1110 | * UART |
| 1111 | */ |
| 1112 | #define ELFIN_UART_BASE 0x7F005000 |
| 1113 | |
| 1114 | #define ELFIN_UART0_OFFSET 0x0000 |
| 1115 | #define ELFIN_UART1_OFFSET 0x0400 |
| 1116 | #define ELFIN_UART2_OFFSET 0x0800 |
| 1117 | #define ELFIN_UART3_OFFSET 0x0c00 |
| 1118 | |
| 1119 | #define ULCON_OFFSET 0x00 |
| 1120 | #define UCON_OFFSET 0x04 |
| 1121 | #define UFCON_OFFSET 0x08 |
| 1122 | #define UMCON_OFFSET 0x0C |
| 1123 | #define UTRSTAT_OFFSET 0x10 |
| 1124 | #define UERSTAT_OFFSET 0x14 |
| 1125 | #define UFSTAT_OFFSET 0x18 |
| 1126 | #define UMSTAT_OFFSET 0x1C |
| 1127 | #define UTXH_OFFSET 0x20 |
| 1128 | #define URXH_OFFSET 0x24 |
| 1129 | #define UBRDIV_OFFSET 0x28 |
| 1130 | #define UDIVSLOT_OFFSET 0x2C |
| 1131 | #define UINTP_OFFSET 0x30 |
| 1132 | #define UINTSP_OFFSET 0x34 |
| 1133 | #define UINTM_OFFSET 0x38 |
| 1134 | |
| 1135 | #define ULCON0_REG __REG(0x7F005000) |
| 1136 | #define UCON0_REG __REG(0x7F005004) |
| 1137 | #define UFCON0_REG __REG(0x7F005008) |
| 1138 | #define UMCON0_REG __REG(0x7F00500C) |
| 1139 | #define UTRSTAT0_REG __REG(0x7F005010) |
| 1140 | #define UERSTAT0_REG __REG(0x7F005014) |
| 1141 | #define UFSTAT0_REG __REG(0x7F005018) |
| 1142 | #define UMSTAT0_REG __REG(0x7F00501c) |
| 1143 | #define UTXH0_REG __REG(0x7F005020) |
| 1144 | #define URXH0_REG __REG(0x7F005024) |
| 1145 | #define UBRDIV0_REG __REG(0x7F005028) |
| 1146 | #define UDIVSLOT0_REG __REG(0x7F00502c) |
| 1147 | #define UINTP0_REG __REG(0x7F005030) |
| 1148 | #define UINTSP0_REG __REG(0x7F005034) |
| 1149 | #define UINTM0_REG __REG(0x7F005038) |
| 1150 | |
| 1151 | #define ULCON1_REG __REG(0x7F005400) |
| 1152 | #define UCON1_REG __REG(0x7F005404) |
| 1153 | #define UFCON1_REG __REG(0x7F005408) |
| 1154 | #define UMCON1_REG __REG(0x7F00540C) |
| 1155 | #define UTRSTAT1_REG __REG(0x7F005410) |
| 1156 | #define UERSTAT1_REG __REG(0x7F005414) |
| 1157 | #define UFSTAT1_REG __REG(0x7F005418) |
| 1158 | #define UMSTAT1_REG __REG(0x7F00541c) |
| 1159 | #define UTXH1_REG __REG(0x7F005420) |
| 1160 | #define URXH1_REG __REG(0x7F005424) |
| 1161 | #define UBRDIV1_REG __REG(0x7F005428) |
| 1162 | #define UDIVSLOT1_REG __REG(0x7F00542c) |
| 1163 | #define UINTP1_REG __REG(0x7F005430) |
| 1164 | #define UINTSP1_REG __REG(0x7F005434) |
| 1165 | #define UINTM1_REG __REG(0x7F005438) |
| 1166 | |
| 1167 | #define UTRSTAT_TX_EMPTY BIT2 |
| 1168 | #define UTRSTAT_RX_READY BIT0 |
| 1169 | #define UART_ERR_MASK 0xF |
| 1170 | |
| 1171 | |
| 1172 | /* |
| 1173 | * PWM timer |
| 1174 | */ |
| 1175 | #define ELFIN_TIMER_BASE 0x7F006000 |
| 1176 | |
| 1177 | #define TCFG0_REG __REG(0x7F006000) |
| 1178 | #define TCFG1_REG __REG(0x7F006004) |
| 1179 | #define TCON_REG __REG(0x7F006008) |
| 1180 | #define TCNTB0_REG __REG(0x7F00600c) |
| 1181 | #define TCMPB0_REG __REG(0x7F006010) |
| 1182 | #define TCNTO0_REG __REG(0x7F006014) |
| 1183 | #define TCNTB1_REG __REG(0x7F006018) |
| 1184 | #define TCMPB1_REG __REG(0x7F00601c) |
| 1185 | #define TCNTO1_REG __REG(0x7F006020) |
| 1186 | #define TCNTB2_REG __REG(0x7F006024) |
| 1187 | #define TCMPB2_REG __REG(0x7F006028) |
| 1188 | #define TCNTO2_REG __REG(0x7F00602c) |
| 1189 | #define TCNTB3_REG __REG(0x7F006030) |
| 1190 | #define TCMPB3_REG __REG(0x7F006034) |
| 1191 | #define TCNTO3_REG __REG(0x7F006038) |
| 1192 | #define TCNTB4_REG __REG(0x7F00603c) |
| 1193 | #define TCNTO4_REG __REG(0x7F006040) |
| 1194 | |
| 1195 | /* Fields */ |
| 1196 | #define fTCFG0_DZONE Fld(8,16) /* the dead zone length (= timer 0) */ |
| 1197 | #define fTCFG0_PRE1 Fld(8,8) /* prescaler value for time 2,3,4 */ |
| 1198 | #define fTCFG0_PRE0 Fld(8,0) /* prescaler value for time 0,1 */ |
| 1199 | #define fTCFG1_MUX4 Fld(4,16) |
| 1200 | /* bits */ |
| 1201 | #define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) |
| 1202 | #define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) |
| 1203 | #define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) |
| 1204 | #define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ |
| 1205 | #define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ |
| 1206 | #define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ |
| 1207 | #define COUNT_4_ON (TCON_4_ONOFF*1) |
| 1208 | #define COUNT_4_OFF (TCON_4_ONOFF*0) |
| 1209 | #define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ |
| 1210 | #define TIMER3_ATLOAD_ON (TCON_3_AUTO*1) |
| 1211 | #define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) |
| 1212 | #define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ |
| 1213 | #define TIMER3_IVT_ON (TCON_3_INVERT*1) |
| 1214 | #define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) |
| 1215 | #define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ |
| 1216 | #define TIMER3_MANUP (TCON_3_MAN*1) |
| 1217 | #define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) |
| 1218 | #define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ |
| 1219 | #define TIMER3_ON (TCON_3_ONOFF*1) |
| 1220 | #define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) |
| 1221 | /* macros */ |
| 1222 | #define GET_PRESCALE_TIMER4(x) FExtr((x), fTCFG0_PRE1) |
| 1223 | #define GET_DIVIDER_TIMER4(x) FExtr((x), fTCFG1_MUX4) |
| 1224 | |
| 1225 | /* |
| 1226 | * RTC Controller |
| 1227 | */ |
| 1228 | #define ELFIN_RTC_BASE 0x7e005000 |
| 1229 | |
| 1230 | #define RTCCON_REG __REG(0x7e005040) |
| 1231 | #define TICNT_REG __REG(0x7e005044) |
| 1232 | #define RTCALM_REG __REG(0x7e005050) |
| 1233 | #define ALMSEC_REG __REG(0x7e005054) |
| 1234 | #define ALMMIN_REG __REG(0x7e005058) |
| 1235 | #define ALMHOUR_REG __REG(0x7e00505c) |
| 1236 | #define ALMDATE_REG __REG(0x7e005060) |
| 1237 | #define ALMMON_REG __REG(0x7e005064) |
| 1238 | #define ALMYEAR_REG __REG(0x7e005068) |
| 1239 | #define BCDSEC_REG __REG(0x7e005070) |
| 1240 | #define BCDMIN_REG __REG(0x7e005074) |
| 1241 | #define BCDHOUR_REG __REG(0x7e005078) |
| 1242 | #define BCDDATE_REG __REG(0x7e00507c) |
| 1243 | #define BCDDAY_REG __REG(0x7e005080) |
| 1244 | #define BCDMON_REG __REG(0x7e005084) |
| 1245 | #define BCDYEAR_REG __REG(0x7e005088) |
| 1246 | |
| 1247 | /* |
| 1248 | * USB2.0 HS OTG (Chapter 26) |
| 1249 | */ |
| 1250 | #define USBOTG_LINK_BASE (0x7C000000) |
| 1251 | #define USBOTG_PHY_BASE (0x7C100000) |
| 1252 | |
| 1253 | /* Core Global Registers */ |
| 1254 | #define S3C_OTG_GOTGCTL (USBOTG_LINK_BASE + 0x000) /* OTG Control & Status */ |
| 1255 | #define S3C_OTG_GOTGINT (USBOTG_LINK_BASE + 0x004) /* OTG Interrupt */ |
| 1256 | #define S3C_OTG_GAHBCFG (USBOTG_LINK_BASE + 0x008) /* Core AHB Configuration */ |
| 1257 | #define S3C_OTG_GUSBCFG (USBOTG_LINK_BASE + 0x00C) /* Core USB Configuration */ |
| 1258 | #define S3C_OTG_GRSTCTL (USBOTG_LINK_BASE + 0x010) /* Core Reset */ |
| 1259 | #define S3C_OTG_GINTSTS (USBOTG_LINK_BASE + 0x014) /* Core Interrupt */ |
| 1260 | #define S3C_OTG_GINTMSK (USBOTG_LINK_BASE + 0x018) /* Core Interrupt Mask */ |
| 1261 | #define S3C_OTG_GRXSTSR (USBOTG_LINK_BASE + 0x01C) /* Receive Status Debug Read/Status Read */ |
| 1262 | #define S3C_OTG_GRXSTSP (USBOTG_LINK_BASE + 0x020) /* Receive Status Debug Pop/Status Pop */ |
| 1263 | #define S3C_OTG_GRXFSIZ (USBOTG_LINK_BASE + 0x024) /* Receive FIFO Size */ |
| 1264 | #define S3C_OTG_GNPTXFSIZ (USBOTG_LINK_BASE + 0x028) /* Non-Periodic Transmit FIFO Size */ |
| 1265 | #define S3C_OTG_GNPTXSTS (USBOTG_LINK_BASE + 0x02C) /* Non-Periodic Transmit FIFO/Queue Status */ |
| 1266 | |
| 1267 | #define S3C_OTG_HPTXFSIZ (USBOTG_LINK_BASE + 0x100) /* Host Periodic Transmit FIFO Size */ |
| 1268 | #define S3C_OTG_DPTXFSIZ1 (USBOTG_LINK_BASE + 0x104) /* Device Periodic Transmit FIFO-1 Size */ |
| 1269 | #define S3C_OTG_DPTXFSIZ2 (USBOTG_LINK_BASE + 0x108) /* Device Periodic Transmit FIFO-2 Size */ |
| 1270 | #define S3C_OTG_DPTXFSIZ3 (USBOTG_LINK_BASE + 0x10C) /* Device Periodic Transmit FIFO-3 Size */ |
| 1271 | #define S3C_OTG_DPTXFSIZ4 (USBOTG_LINK_BASE + 0x110) /* Device Periodic Transmit FIFO-4 Size */ |
| 1272 | #define S3C_OTG_DPTXFSIZ5 (USBOTG_LINK_BASE + 0x114) /* Device Periodic Transmit FIFO-5 Size */ |
| 1273 | #define S3C_OTG_DPTXFSIZ6 (USBOTG_LINK_BASE + 0x118) /* Device Periodic Transmit FIFO-6 Size */ |
| 1274 | #define S3C_OTG_DPTXFSIZ7 (USBOTG_LINK_BASE + 0x11C) /* Device Periodic Transmit FIFO-7 Size */ |
| 1275 | #define S3C_OTG_DPTXFSIZ8 (USBOTG_LINK_BASE + 0x120) /* Device Periodic Transmit FIFO-8 Size */ |
| 1276 | #define S3C_OTG_DPTXFSIZ9 (USBOTG_LINK_BASE + 0x124) /* Device Periodic Transmit FIFO-9 Size */ |
| 1277 | #define S3C_OTG_DPTXFSIZ10 (USBOTG_LINK_BASE + 0x128) /* Device Periodic Transmit FIFO-10 Size */ |
| 1278 | #define S3C_OTG_DPTXFSIZ11 (USBOTG_LINK_BASE + 0x12C) /* Device Periodic Transmit FIFO-11 Size */ |
| 1279 | #define S3C_OTG_DPTXFSIZ12 (USBOTG_LINK_BASE + 0x130) /* Device Periodic Transmit FIFO-12 Size */ |
| 1280 | #define S3C_OTG_DPTXFSIZ13 (USBOTG_LINK_BASE + 0x134) /* Device Periodic Transmit FIFO-13 Size */ |
| 1281 | #define S3C_OTG_DPTXFSIZ14 (USBOTG_LINK_BASE + 0x138) /* Device Periodic Transmit FIFO-14 Size */ |
| 1282 | #define S3C_OTG_DPTXFSIZ15 (USBOTG_LINK_BASE + 0x13C) /* Device Periodic Transmit FIFO-15 Size */ |
| 1283 | |
| 1284 | /* Host Global Registers */ |
| 1285 | #define S3C_OTG_HCFG (USBOTG_LINK_BASE + 0x400) /* Host Configuration */ |
| 1286 | #define S3C_OTG_HFIR (USBOTG_LINK_BASE + 0x404) /* Host Frame Interval */ |
| 1287 | #define S3C_OTG_HFNUM (USBOTG_LINK_BASE + 0x408) /* Host Frame Number/Frame Time Remaining */ |
| 1288 | #define S3C_OTG_HPTXSTS (USBOTG_LINK_BASE + 0x410) /* Host Periodic Transmit FIFO/Queue Status */ |
| 1289 | #define S3C_OTG_HAINT (USBOTG_LINK_BASE + 0x414) /* Host All Channels Interrupt */ |
| 1290 | #define S3C_OTG_HAINTMSK (USBOTG_LINK_BASE + 0x418) /* Host All Channels Interrupt Mask */ |
| 1291 | |
| 1292 | /* Host Port Control & Status Registers */ |
| 1293 | #define S3C_OTG_HPRT (USBOTG_LINK_BASE + 0x440) /* Host Port Control & Status */ |
| 1294 | |
| 1295 | /* Host Channel-Specific Registers */ |
| 1296 | #define S3C_OTG_HCCHAR0 (USBOTG_LINK_BASE + 0x500) /* Host Channel-0 Characteristics */ |
| 1297 | #define S3C_OTG_HCSPLT0 (USBOTG_LINK_BASE + 0x504) /* Host Channel-0 Split Control */ |
| 1298 | #define S3C_OTG_HCINT0 (USBOTG_LINK_BASE + 0x508) /* Host Channel-0 Interrupt */ |
| 1299 | #define S3C_OTG_HCINTMSK0 (USBOTG_LINK_BASE + 0x50C) /* Host Channel-0 Interrupt Mask */ |
| 1300 | #define S3C_OTG_HCTSIZ0 (USBOTG_LINK_BASE + 0x510) /* Host Channel-0 Transfer Size */ |
| 1301 | #define S3C_OTG_HCDMA0 (USBOTG_LINK_BASE + 0x514) /* Host Channel-0 DMA Address */ |
| 1302 | |
| 1303 | |
| 1304 | /* Device Global Registers */ |
| 1305 | #define S3C_OTG_DCFG (USBOTG_LINK_BASE + 0x800) /* Device Configuration */ |
| 1306 | #define S3C_OTG_DCTL (USBOTG_LINK_BASE + 0x804) /* Device Control */ |
| 1307 | #define S3C_OTG_DSTS (USBOTG_LINK_BASE + 0x808) /* Device Status */ |
| 1308 | #define S3C_OTG_DIEPMSK (USBOTG_LINK_BASE + 0x810) /* Device IN Endpoint Common Interrupt Mask */ |
| 1309 | #define S3C_OTG_DOEPMSK (USBOTG_LINK_BASE + 0x814) /* Device OUT Endpoint Common Interrupt Mask */ |
| 1310 | #define S3C_OTG_DAINT (USBOTG_LINK_BASE + 0x818) /* Device All Endpoints Interrupt */ |
| 1311 | #define S3C_OTG_DAINTMSK (USBOTG_LINK_BASE + 0x81C) /* Device All Endpoints Interrupt Mask */ |
| 1312 | #define S3C_OTG_DTKNQR1 (USBOTG_LINK_BASE + 0x820) /* Device IN Token Sequence Learning Queue Read 1 */ |
| 1313 | #define S3C_OTG_DTKNQR2 (USBOTG_LINK_BASE + 0x824) /* Device IN Token Sequence Learning Queue Read 2 */ |
| 1314 | #define S3C_OTG_DVBUSDIS (USBOTG_LINK_BASE + 0x828) /* Device VBUS Discharge Time */ |
| 1315 | #define S3C_OTG_DVBUSPULSE (USBOTG_LINK_BASE + 0x82C) /* Device VBUS Pulsing Time */ |
| 1316 | #define S3C_OTG_DTKNQR3 (USBOTG_LINK_BASE + 0x830) /* Device IN Token Sequence Learning Queue Read 3 */ |
| 1317 | #define S3C_OTG_DTKNQR4 (USBOTG_LINK_BASE + 0x834) /* Device IN Token Sequence Learning Queue Read 4 */ |
| 1318 | |
| 1319 | /* Device Logical IN Endpoint-Specific Registers */ |
| 1320 | #define S3C_OTG_DIEPCTL0 (USBOTG_LINK_BASE + 0x900) /* Device IN Endpoint 0 Control */ |
| 1321 | #define S3C_OTG_DIEPINT0 (USBOTG_LINK_BASE + 0x908) /* Device IN Endpoint 0 Interrupt */ |
| 1322 | #define S3C_OTG_DIEPTSIZ0 (USBOTG_LINK_BASE + 0x910) /* Device IN Endpoint 0 Transfer Size */ |
| 1323 | #define S3C_OTG_DIEPDMA0 (USBOTG_LINK_BASE + 0x914) /* Device IN Endpoint 0 DMA Address */ |
| 1324 | |
| 1325 | /* Device Logical OUT Endpoint-Specific Registers */ |
| 1326 | #define S3C_OTG_DOEPCTL0 (USBOTG_LINK_BASE + 0xB00) /* Device OUT Endpoint 0 Control */ |
| 1327 | #define S3C_OTG_DOEPINT0 (USBOTG_LINK_BASE + 0xB08) /* Device OUT Endpoint 0 Interrupt */ |
| 1328 | #define S3C_OTG_DOEPTSIZ0 (USBOTG_LINK_BASE + 0xB10) /* Device OUT Endpoint 0 Transfer Size */ |
| 1329 | #define S3C_OTG_DOEPDMA0 (USBOTG_LINK_BASE + 0xB14) /* Device OUT Endpoint 0 DMA Address */ |
| 1330 | |
| 1331 | /* Power & clock gating registers */ |
| 1332 | #define S3C_OTG_PCGCCTRL (USBOTG_LINK_BASE + 0xE00) |
| 1333 | |
| 1334 | /* Endpoint FIFO address */ |
| 1335 | #define S3C_OTG_EP0_FIFO (USBOTG_LINK_BASE + 0x1000) |
| 1336 | |
| 1337 | |
| 1338 | |
| 1339 | /* OTG PHY CORE REGISTERS */ |
| 1340 | #define S3C_OTG_PHYPWR (USBOTG_PHY_BASE+0x00) |
| 1341 | #define S3C_OTG_PHYCTRL (USBOTG_PHY_BASE+0x04) |
| 1342 | #define S3C_OTG_RSTCON (USBOTG_PHY_BASE+0x08) |
| 1343 | |
| 1344 | /* include common stuff */ |
| 1345 | #ifndef __ASSEMBLY__ |
| 1346 | #if 0 |
| 1347 | static inline S3C2410_SDI * S3C2410_GetBase_SDI(void) |
| 1348 | { |
| 1349 | return (S3C2410_SDI *)ELFIN_SDI_BASE; |
| 1350 | } |
| 1351 | #endif |
| 1352 | #else /* #ifndef __ASSEMBLY__ */ |
| 1353 | |
| 1354 | /* watchdog */ |
| 1355 | #define WTCON_OFFSET 0x00 |
| 1356 | |
| 1357 | /* LCD controller */ |
| 1358 | #define LCDBGCON_OFFSET 0x5c |
| 1359 | |
| 1360 | #endif /* #ifndef __ASSEMBLY__ */ |
| 1361 | |
| 1362 | /* PENDING BIT */ |
| 1363 | #define BIT_EINT0 (0x1) |
| 1364 | #define BIT_EINT1 (0x1<<1) |
| 1365 | #define BIT_EINT2 (0x1<<2) |
| 1366 | #define BIT_EINT3 (0x1<<3) |
| 1367 | #define BIT_EINT4_7 (0x1<<4) |
| 1368 | #define BIT_EINT8_23 (0x1<<5) |
| 1369 | #define BIT_BAT_FLT (0x1<<7) |
| 1370 | #define BIT_TICK (0x1<<8) |
| 1371 | #define BIT_WDT (0x1<<9) |
| 1372 | #define BIT_TIMER0 (0x1<<10) |
| 1373 | #define BIT_TIMER1 (0x1<<11) |
| 1374 | #define BIT_TIMER2 (0x1<<12) |
| 1375 | #define BIT_TIMER3 (0x1<<13) |
| 1376 | #define BIT_TIMER4 (0x1<<14) |
| 1377 | #define BIT_UART2 (0x1<<15) |
| 1378 | #define BIT_LCD (0x1<<16) |
| 1379 | #define BIT_DMA0 (0x1<<17) |
| 1380 | #define BIT_DMA1 (0x1<<18) |
| 1381 | #define BIT_DMA2 (0x1<<19) |
| 1382 | #define BIT_DMA3 (0x1<<20) |
| 1383 | #define BIT_SDI (0x1<<21) |
| 1384 | #define BIT_SPI0 (0x1<<22) |
| 1385 | #define BIT_UART1 (0x1<<23) |
| 1386 | #define BIT_USBH (0x1<<26) |
| 1387 | #define BIT_IIC (0x1<<27) |
| 1388 | #define BIT_UART0 (0x1<<28) |
| 1389 | #define BIT_SPI1 (0x1<<29) |
| 1390 | #define BIT_RTC (0x1<<30) |
| 1391 | #define BIT_ADC (0x1<<31) |
| 1392 | #define BIT_ALLMSK (0xFFFFFFFF) |
| 1393 | |
| 1394 | #endif /*__S3C6410_H__*/ |
| 1395 | |
