| 1 | /* |
| 2 | * Memory Setup stuff - taken from blob memsetup.S |
| 3 | * |
| 4 | * Modified for the FIC Neo1973 GTA01 by Harald Welte <laforge@openmoko.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | /* NOTE this stuff runs in steppingstone context! */ |
| 23 | |
| 24 | |
| 25 | /* |
| 26 | * #include <config.h> |
| 27 | * #include <version.h> |
| 28 | */ |
| 29 | #define __ASM_MODE__ |
| 30 | #include <neo_gta01.h> |
| 31 | |
| 32 | /* |
| 33 | * |
| 34 | * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S |
| 35 | * |
| 36 | * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com> |
| 37 | * |
| 38 | */ |
| 39 | |
| 40 | #define BWSCON 0x48000000 |
| 41 | |
| 42 | /* BWSCON */ |
| 43 | #define DW8 (0x0) |
| 44 | #define DW16 (0x1) |
| 45 | #define DW32 (0x2) |
| 46 | #define WAIT (0x1<<2) |
| 47 | #define UBLB (0x1<<3) |
| 48 | |
| 49 | #define B1_BWSCON (DW16 + WAIT + UBLB) |
| 50 | #define B2_BWSCON (DW16) |
| 51 | #define B3_BWSCON (DW16 + WAIT + UBLB) |
| 52 | #define B4_BWSCON (DW16) |
| 53 | #define B5_BWSCON (DW16) |
| 54 | #define B6_BWSCON (DW32) |
| 55 | #define B7_BWSCON (DW32) |
| 56 | |
| 57 | /* BANK0CON */ |
| 58 | #define B0_Tacs 0x0 /* 0clk */ |
| 59 | #define B0_Tcos 0x0 /* 0clk */ |
| 60 | #define B0_Tacc 0x7 /* 14clk */ |
| 61 | #define B0_Tcoh 0x0 /* 0clk */ |
| 62 | #define B0_Tah 0x0 /* 0clk */ |
| 63 | #define B0_Tacp 0x0 |
| 64 | #define B0_PMC 0x0 /* normal */ |
| 65 | |
| 66 | /* BANK1CON: Smedia Glamo 3362 (on GTA02) */ |
| 67 | #define B1_Tacs 0x0 /* 0clk */ |
| 68 | #define B1_Tcos 0x3 /* 4clk */ |
| 69 | #define B1_Tacc 0x3 /* 4clk */ |
| 70 | #define B1_Tcoh 0x3 /* 4clk */ |
| 71 | #define B1_Tah 0x0 /* 0clk */ |
| 72 | #define B1_Tacp 0x0 |
| 73 | #define B1_PMC 0x0 |
| 74 | |
| 75 | #define B2_Tacs 0x0 |
| 76 | #define B2_Tcos 0x0 |
| 77 | #define B2_Tacc 0x7 |
| 78 | #define B2_Tcoh 0x0 |
| 79 | #define B2_Tah 0x0 |
| 80 | #define B2_Tacp 0x0 |
| 81 | #define B2_PMC 0x0 |
| 82 | |
| 83 | #define B3_Tacs 0x0 /* 0clk */ |
| 84 | #define B3_Tcos 0x3 /* 4clk */ |
| 85 | #define B3_Tacc 0x7 /* 14clk */ |
| 86 | #define B3_Tcoh 0x1 /* 1clk */ |
| 87 | #define B3_Tah 0x0 /* 0clk */ |
| 88 | #define B3_Tacp 0x3 /* 6clk */ |
| 89 | #define B3_PMC 0x0 /* normal */ |
| 90 | |
| 91 | #define B4_Tacs 0x0 /* 0clk */ |
| 92 | #define B4_Tcos 0x0 /* 0clk */ |
| 93 | #define B4_Tacc 0x7 /* 14clk */ |
| 94 | #define B4_Tcoh 0x0 /* 0clk */ |
| 95 | #define B4_Tah 0x0 /* 0clk */ |
| 96 | #define B4_Tacp 0x0 |
| 97 | #define B4_PMC 0x0 /* normal */ |
| 98 | |
| 99 | #define B5_Tacs 0x0 /* 0clk */ |
| 100 | #define B5_Tcos 0x0 /* 0clk */ |
| 101 | #define B5_Tacc 0x7 /* 14clk */ |
| 102 | #define B5_Tcoh 0x0 /* 0clk */ |
| 103 | #define B5_Tah 0x0 /* 0clk */ |
| 104 | #define B5_Tacp 0x0 |
| 105 | #define B5_PMC 0x0 /* normal */ |
| 106 | |
| 107 | #define B6_MT 0x3 /* SDRAM */ |
| 108 | #define B6_Trcd 0x1 /* 3clk */ |
| 109 | |
| 110 | #define B6_SCAN 0x2 /* 10bit */ |
| 111 | #define B7_SCAN 0x2 /* 10bit */ |
| 112 | |
| 113 | |
| 114 | #define B7_MT 0x3 /* SDRAM */ |
| 115 | #define B7_Trcd 0x1 /* 3clk */ |
| 116 | |
| 117 | /* REFRESH parameter */ |
| 118 | #define REFEN 0x1 /* Refresh enable */ |
| 119 | #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ |
| 120 | #define Trp 0x1 /* 3clk */ |
| 121 | #define Trc 0x3 /* 7clk */ |
| 122 | #define Tchr 0x2 /* 3clk */ |
| 123 | //#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ |
| 124 | #define REFCNT 997 /* period=17.5us, HCLK=60Mhz, (2048+1-15.6*60) */ |
| 125 | /**************************************/ |
| 126 | |
| 127 | .globl lowlevel_init |
| 128 | lowlevel_init: |
| 129 | |
| 130 | ldr r0, =SMRDATA |
| 131 | ldr r1, =BWSCON /* Bus Width Status Controller */ |
| 132 | add r2, r0, #13*4 |
| 133 | 0: |
| 134 | ldr r3, [r0], #4 |
| 135 | str r3, [r1], #4 |
| 136 | cmp r2, r0 |
| 137 | bne 0b |
| 138 | |
| 139 | /* setup asynchronous bus mode */ |
| 140 | mrc p15, 0, r1 ,c1 ,c0, 0 |
| 141 | orr r1, r1, #0xc0000000 |
| 142 | mcr p15, 0, r1, c1, c0, 0 |
| 143 | |
| 144 | /* everything is fine now */ |
| 145 | mov pc, lr |
| 146 | |
| 147 | .ltorg |
| 148 | /* the literal pools origin */ |
| 149 | SMRDATA: |
| 150 | .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) |
| 151 | .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) |
| 152 | .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) |
| 153 | .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) |
| 154 | .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) |
| 155 | .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) |
| 156 | .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) |
| 157 | .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) |
| 158 | .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) |
| 159 | .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) |
| 160 | .word 0xb2 |
| 161 | .word 0x30 |
| 162 | .word 0x30 |
| 163 | |
