| 1 | /* |
| 2 | * (C) Copyright 2007 OpenMoko, Inc. |
| 3 | * |
| 4 | * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #define __ASM_MODE__ |
| 23 | #define __ASSEMBLY__ |
| 24 | |
| 25 | #include <neo_gta01.h> |
| 26 | |
| 27 | #define S3C2410_MISCCR_nEN_SCLK0 (1 << 17) |
| 28 | #define S3C2410_MISCCR_nEN_SCLK1 (1 << 18) |
| 29 | #define S3C2410_MISCCR_nEN_SCLKE (1 << 19) |
| 30 | |
| 31 | |
| 32 | .globl _start, processor_id, is_jtag |
| 33 | |
| 34 | _start: b start_code |
| 35 | /* if we are injected by JTAG, the script sets _istag content to nonzero */ |
| 36 | is_jtag: |
| 37 | .word 0 |
| 38 | |
| 39 | /* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script |
| 40 | * we need to go through this hassle because before this moment, SDRAM is not |
| 41 | * working so we can't prep it from JTAG |
| 42 | */ |
| 43 | |
| 44 | _steppingstone_done: |
| 45 | ldr pc, _start_armboot |
| 46 | |
| 47 | _start_armboot: |
| 48 | .word start_qi |
| 49 | |
| 50 | _TEXT_BASE: |
| 51 | .word TEXT_BASE |
| 52 | |
| 53 | /* |
| 54 | * These are defined in the board-specific linker script. |
| 55 | */ |
| 56 | .globl _bss_start |
| 57 | _bss_start: |
| 58 | .word __bss_start |
| 59 | |
| 60 | .globl _bss_end |
| 61 | _bss_end: |
| 62 | .word _end |
| 63 | /* |
| 64 | * we have a stack in steppingstone because we can want to run full memory |
| 65 | * memory tests |
| 66 | */ |
| 67 | |
| 68 | .fill 128 |
| 69 | .globl _ss_stack |
| 70 | _ss_stack: |
| 71 | |
| 72 | |
| 73 | start_code: |
| 74 | /* |
| 75 | * set the cpu to SVC32 mode |
| 76 | */ |
| 77 | mrs r0,cpsr |
| 78 | bic r0,r0,#0x1f |
| 79 | orr r0,r0,#0xd3 |
| 80 | msr cpsr,r0 |
| 81 | |
| 82 | # define pWTCON 0x53000000 |
| 83 | |
| 84 | ldr r0, =pWTCON |
| 85 | mov r1, #0x0 |
| 86 | str r1, [r0] |
| 87 | |
| 88 | /* |
| 89 | * mask all IRQs by setting all bits in the INTMR - default |
| 90 | */ |
| 91 | # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ |
| 92 | # define INTSUBMSK 0x4A00001C |
| 93 | # define INTSUBMSK_val 0x000007ff |
| 94 | |
| 95 | mov r1, #0xffffffff |
| 96 | ldr r0, =INTMSK |
| 97 | str r1, [r0] |
| 98 | |
| 99 | ldr r1, =INTSUBMSK_val |
| 100 | ldr r0, =INTSUBMSK |
| 101 | str r1, [r0] |
| 102 | |
| 103 | /* Clock asynchronous mode */ |
| 104 | mrc p15, 0, r1, c1, c0, 0 |
| 105 | orr r1, r1, #0xc0000000 |
| 106 | mcr p15, 0, r1, c1, c0, 0 |
| 107 | |
| 108 | #define LOCKTIME 0x4c000000 |
| 109 | |
| 110 | ldr r0, =LOCKTIME |
| 111 | mov r1, #0xffffff |
| 112 | str r1, [r0] |
| 113 | |
| 114 | # define UPLLCON 0x4c000008 |
| 115 | # define MPLLCON_val ((0x90 << 12) + (0x7 << 4) + 0x0) /* 202 MHz */ |
| 116 | # define UPLLCON_val ((0x78 << 12) + (0x2 << 4) + 0x3) |
| 117 | |
| 118 | ldr r0, =UPLLCON |
| 119 | ldr r1, =UPLLCON_val |
| 120 | str r1, [r0] |
| 121 | |
| 122 | /* Page 7-19, seven nops between UPLL and MPLL */ |
| 123 | nop |
| 124 | nop |
| 125 | nop |
| 126 | nop |
| 127 | nop |
| 128 | nop |
| 129 | nop |
| 130 | |
| 131 | ldr r1, =MPLLCON_val |
| 132 | str r1, [r0, #-4] /* MPLLCON */ |
| 133 | |
| 134 | # define CLKDIVN 0x4C000014 /* clock divisor register */ |
| 135 | # define CLKDIVN_val 3 /* FCLK:HCLK:PCLK = 1:2:4 */ |
| 136 | |
| 137 | /* FCLK:HCLK:PCLK = 1:3:6 */ |
| 138 | ldr r0, =CLKDIVN |
| 139 | mov r1, #CLKDIVN_val |
| 140 | str r1, [r0] |
| 141 | |
| 142 | /* enable only CPU peripheral block clocks we actually use */ |
| 143 | ldr r0, =0x4c00000c /* clkcon */ |
| 144 | ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */ |
| 145 | str r1, [r0] |
| 146 | |
| 147 | /* gpio UART0 init */ |
| 148 | ldr r0, =0x56000070 |
| 149 | ldr r1, =0x000000AA |
| 150 | str r1, [r0] |
| 151 | |
| 152 | /* init uart0 */ |
| 153 | ldr r0, =0x50000000 |
| 154 | mov r1, #0x03 |
| 155 | str r1, [r0] |
| 156 | ldr r1, =0x245 |
| 157 | str r1, [r0, #0x04] |
| 158 | mov r1, #0x01 |
| 159 | str r1, [r0, #0x08] |
| 160 | mov r1, #0x00 |
| 161 | str r1, [r0, #0x0c] |
| 162 | mov r1, #0x1a |
| 163 | str r1, [r0, #0x28] |
| 164 | |
| 165 | /* reset nand controller, or it is dead to us */ |
| 166 | |
| 167 | #define oNFCONF 0x00 |
| 168 | #define oNFCMD 0x04 |
| 169 | #define oNFSTAT 0x10 |
| 170 | |
| 171 | mov r1, #0x4E000000 |
| 172 | ldr r2, =0xf842 @ initial value enable tacls=3,rph0=6,rph1=0 |
| 173 | str r2, [r1, #oNFCONF] |
| 174 | ldr r2, [r1, #oNFCONF] |
| 175 | bic r2, r2, #0x800 @ enable chip |
| 176 | str r2, [r1, #oNFCONF] |
| 177 | mov r2, #0xff @ RESET command |
| 178 | strb r2, [r1, #oNFCMD] |
| 179 | mov r3, #0 @ wait |
| 180 | 1: add r3, r3, #0x1 |
| 181 | cmp r3, #0xa |
| 182 | blt 1b |
| 183 | 2: ldr r2, [r1, #oNFSTAT] @ wait ready |
| 184 | tst r2, #0x1 |
| 185 | beq 2b |
| 186 | ldr r2, [r1, #oNFCONF] |
| 187 | orr r2, r2, #0x800 @ disable chip |
| 188 | str r2, [r1, #oNFCONF] |
| 189 | |
| 190 | /* take sdram out of power down */ |
| 191 | ldr r0, =0x56000080 /* misccr */ |
| 192 | ldr r1, [ r0 ] |
| 193 | bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE) |
| 194 | str r1, [ r0 ] |
| 195 | |
| 196 | /* ensure signals stabalise */ |
| 197 | mov r1, #128 |
| 198 | 3: subs r1, r1, #1 |
| 199 | bpl 3b |
| 200 | |
| 201 | bl cpu_init_crit |
| 202 | |
| 203 | /* ensure some refresh has happened */ |
| 204 | ldr r1, =0xfffff |
| 205 | 4: subs r1, r1, #1 |
| 206 | bpl 4b |
| 207 | |
| 208 | /* capture full EINT situation into gstatus 4 */ |
| 209 | |
| 210 | ldr r0, =0x4A000000 /* SRCPND */ |
| 211 | ldr r1, [ r0 ] |
| 212 | and r1, r1, #0xf |
| 213 | |
| 214 | ldr r0, =0x560000BC /* gstatus4 */ |
| 215 | str r1, [ r0 ] |
| 216 | |
| 217 | ldr r0, =0x560000A8 /* EINTPEND */ |
| 218 | ldr r1, [ r0 ] |
| 219 | ldr r0, =0xfff0 |
| 220 | and r1, r1, r0 |
| 221 | ldr r0, =0x560000BC /* gstatus4 */ |
| 222 | ldr r0, [ r0 ] |
| 223 | orr r1, r1, r0 |
| 224 | ldr r0, =0x560000BC /* gstatus4 */ |
| 225 | str r1, [ r0 ] |
| 226 | |
| 227 | /* test for resume */ |
| 228 | |
| 229 | ldr r1, =0x560000B4 /* gstatus2 */ |
| 230 | ldr r0, [ r1 ] |
| 231 | tst r0, #0x02 /* is this resume from power down */ |
| 232 | /* well, if it was, we are going to jump to |
| 233 | * whatever address we stashed in gstatus3, |
| 234 | * and gstatus4 will hold the wake interrupt |
| 235 | * source for the OS to look at |
| 236 | */ |
| 237 | ldrne pc, [r1, #4] |
| 238 | |
| 239 | |
| 240 | /* >> CFG_VIDEO_LOGO_MAX_SIZE */ |
| 241 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 242 | |
| 243 | stack_setup: |
| 244 | ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ |
| 245 | sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ |
| 246 | sub sp, r0, #12 /* leave 3 words for abort-stack */ |
| 247 | |
| 248 | clear_bss: |
| 249 | ldr r0, _bss_start /* find start of bss segment */ |
| 250 | ldr r1, _bss_end /* stop here */ |
| 251 | mov r2, #0x00000000 /* clear */ |
| 252 | |
| 253 | clbss_l: |
| 254 | str r2, [r0] /* clear loop... */ |
| 255 | add r0, r0, #4 |
| 256 | cmp r0, r1 |
| 257 | ble clbss_l |
| 258 | |
| 259 | /* we are going to jump into the C part of the init now */ |
| 260 | spin: |
| 261 | b _steppingstone_done |
| 262 | |
| 263 | /* |
| 264 | ************************************************************************* |
| 265 | * |
| 266 | * CPU_init_critical registers |
| 267 | * |
| 268 | * setup important registers |
| 269 | * setup memory timing |
| 270 | * |
| 271 | ************************************************************************* |
| 272 | */ |
| 273 | |
| 274 | cpu_init_crit: |
| 275 | |
| 276 | /* |
| 277 | * flush v4 I/D caches |
| 278 | */ |
| 279 | mov r0, #0 |
| 280 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
| 281 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
| 282 | |
| 283 | /* |
| 284 | * disable MMU stuff and caches |
| 285 | */ |
| 286 | mrc p15, 0, r0, c1, c0, 0 |
| 287 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) |
| 288 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) |
| 289 | orr r0, r0, #0x00000002 @ set bit 2 (A) Align |
| 290 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache |
| 291 | mcr p15, 0, r0, c1, c0, 0 |
| 292 | |
| 293 | /* |
| 294 | * before relocating, we have to setup RAM timing |
| 295 | * because memory timing is board-dependend, you will |
| 296 | * find a lowlevel_init.S in your board directory. |
| 297 | */ |
| 298 | mov ip, lr |
| 299 | |
| 300 | bl lowlevel_init |
| 301 | |
| 302 | mov lr, ip |
| 303 | mov pc, lr |
| 304 | |
| 305 | |
