Root/qiboot/src/cpu/s3c6410/start.S

1/*
2 * (C) Copyright 2007 OpenMoko, Inc.
3 *
4 * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#define __ASM_MODE__
23#define __ASSEMBLY__
24
25#include <s3c6410.h>
26
27#define TEXT_BASE 0x53000000
28
29
30#define S3C6410_POP_A 1
31
32#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
33
34/* fixed MPLL 533MHz */
35#define MPLL_MDIV 266
36#define MPLL_PDIV 3
37#define MPLL_SDIV 1
38
39#define Startup_APLLdiv 0
40#define APLL_MDIV 266
41#define APLL_PDIV 3
42#define APLL_SDIV 1
43#define Startup_PCLKdiv 3
44#define Startup_HCLKdiv 1
45#define Startup_MPLLdiv 1
46#define Startup_HCLKx2div 1
47#define Startup_APLL (12000000/(APLL_PDIV<<APLL_SDIV)*APLL_MDIV)
48#define Startup_HCLK (Startup_APLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))
49
50#define CLK_DIV_VAL ((Startup_PCLKdiv<<12)|(Startup_HCLKx2div<<9)|(Startup_HCLKdiv<<8)|(Startup_MPLLdiv<<4)|Startup_APLLdiv)
51#define APLL_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
52#define MPLL_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
53#if S3C6410_POP_A
54
55#define DMC1_MEM_CFG 0x00210011 /* Supports one CKE control, Chip1, Burst4, Row/Column bit */
56#define DMC1_MEM_CFG2 0xB41
57#define DMC1_CHIP0_CFG 0x150FC
58#define DMC1_CHIP1_CFG 0x154FC
59#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
60
61/* Memory Parameters */
62/* DDR Parameters */
63#define DDR_tREFRESH 5865 /* ns */
64#define DDR_tRAS 50 /* ns (min: 45ns)*/
65#define DDR_tRC 68 /* ns (min: 67.5ns)*/
66#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
67#define DDR_tRFC 133 /* ns (min: 80ns)*/
68#define DDR_tRP 23 /* ns (min: 22.5ns)*/
69#define DDR_tRRD 20 /* ns (min: 15ns)*/
70#define DDR_tWR 20 /* ns (min: 15ns)*/
71#define DDR_tXSR 125 /* ns (min: 120ns)*/
72#define DDR_CASL 3 /* CAS Latency 3 */
73
74#else
75
76#define DMC1_MEM_CFG 0x00010012 /* Supports one CKE control, Chip1, Burst4, Row/Column bit */
77#define DMC1_MEM_CFG2 0xB45
78#define DMC1_CHIP0_CFG 0x150F8
79#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
80
81/* Memory Parameters */
82/* DDR Parameters */
83#define DDR_tREFRESH 7800 /* ns */
84#define DDR_tRAS 45 /* ns (min: 45ns)*/
85#define DDR_tRC 68 /* ns (min: 67.5ns)*/
86#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
87#define DDR_tRFC 80 /* ns (min: 80ns)*/
88#define DDR_tRP 23 /* ns (min: 22.5ns)*/
89#define DDR_tRRD 15 /* ns (min: 15ns)*/
90#define DDR_tWR 15 /* ns (min: 15ns)*/
91#define DDR_tXSR 120 /* ns (min: 120ns)*/
92#define DDR_CASL 3 /* CAS Latency 3 */
93
94#endif
95
96
97/*
98 * mDDR memory configuration
99 */
100#define DMC_DDR_BA_EMRS 2
101#define DMC_DDR_MEM_CASLAT 3
102#define DMC_DDR_CAS_LATENCY (DDR_CASL<<1) //6 Set Cas Latency to 3
103#define DMC_DDR_t_DQSS 1 // Min 0.75 ~ 1.25
104#define DMC_DDR_t_MRD 2 //Min 2 tck
105#define DMC_DDR_t_RAS (((Startup_HCLK / 1000 * DDR_tRAS) - 1) / 1000000 + 1) //7, Min 45ns
106#define DMC_DDR_t_RC (((Startup_HCLK / 1000 * DDR_tRC) - 1) / 1000000 + 1) //10, Min 67.5ns
107#define DMC_DDR_t_RCD (((Startup_HCLK / 1000 * DDR_tRCD) - 1) / 1000000 + 1) //4,5(TRM), Min 22.5ns
108#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
109#define DMC_DDR_t_RFC (((Startup_HCLK / 1000 * DDR_tRFC) - 1) / 1000000 + 1) //11,18(TRM) Min 80ns
110#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
111#define DMC_DDR_t_RP (((Startup_HCLK / 1000 * DDR_tRP) - 1) / 1000000 + 1) //4, 5(TRM) Min 22.5ns
112#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
113#define DMC_DDR_t_RRD (((Startup_HCLK / 1000 * DDR_tRRD) - 1) / 1000000 + 1) //3, Min 15ns
114#define DMC_DDR_t_WR (((Startup_HCLK / 1000 * DDR_tWR) - 1) / 1000000 + 1) //Min 15ns
115#define DMC_DDR_t_WTR 2
116#define DMC_DDR_t_XP 2 //1tck + tIS(1.5ns)
117#define DMC_DDR_t_XSR (((Startup_HCLK / 1000 * DDR_tXSR) - 1) / 1000000 + 1) //17, Min 120ns
118#define DMC_DDR_t_ESR DMC_DDR_t_XSR
119#define DMC_DDR_REFRESH_PRD (((Startup_HCLK / 1000 * DDR_tREFRESH) - 1) / 1000000) // TRM 2656
120#define DMC_DDR_USER_CONFIG 1 // 2b01 : mDDR
121
122
123.globl _start, processor_id, is_jtag
124
125_start: b start_code
126/* if we are injected by JTAG, the script sets _istag content to nonzero */
127is_jtag:
128    .word 0
129
130/* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script
131 * we need to go through this hassle because before this moment, SDRAM is not
132 * working so we can't prep it from JTAG
133 */
134
135_steppingstone_done:
136    ldr pc, _start_armboot
137
138_start_armboot:
139    .word start_qi
140
141_TEXT_BASE:
142    .word TEXT_BASE
143
144/*
145 * These are defined in the board-specific linker script.
146 */
147.globl _bss_start
148_bss_start:
149    .word __bss_start
150
151.globl _bss_end
152_bss_end:
153    .word _end
154
155/*
156 * we have a stack in steppingstone because we can want to run full memory
157 * memory tests
158 */
159
160    .fill 128
161.globl _ss_stack
162_ss_stack:
163
164start_code:
165    /*
166     * set the cpu to SVC32 mode
167     */
168    mrs r0,cpsr
169    bic r0,r0,#0x1f
170    orr r0,r0,#0xd3
171    msr cpsr,r0
172
173    /*
174     * flush v4 I/D caches
175     */
176    mov r0, #0
177    mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
178    mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
179
180    /*
181     * disable MMU stuff and caches
182     */
183    mrc p15, 0, r0, c1, c0, 0
184    bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
185    bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
186    orr r0, r0, #0x00000002 @ set bit 2 (A) Align
187    orr r0, r0, #0x00005000 @ Enable I and D-Cache
188    mcr p15, 0, r0, c1, c0, 0
189
190    /* Peri port setup */
191    ldr r0, =0x70000000
192    orr r0, r0, #0x13
193        mcr p15,0,r0,c15,c2,4 @ 256M(0x70000000-0x7fffffff)
194
195    /* SDRAM */
196
197    ldr r0, =ELFIN_MEM_SYS_CFG @Memory sussystem address 0x7e00f120
198    mov r1, #0xd @ Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1
199    str r1, [r0]
200
201    ldr r0, =ELFIN_DMC1_BASE @DMC1 base address 0x7e001000
202
203    ldr r1, =0x04
204    str r1, [r0, #INDEX_DMC_MEMC_CMD]
205
206    ldr r1, =DMC_DDR_REFRESH_PRD
207    str r1, [r0, #INDEX_DMC_REFRESH_PRD]
208
209    ldr r1, =DMC_DDR_CAS_LATENCY
210    str r1, [r0, #INDEX_DMC_CAS_LATENCY]
211
212    ldr r1, =DMC_DDR_t_DQSS
213    str r1, [r0, #INDEX_DMC_T_DQSS]
214
215    ldr r1, =DMC_DDR_t_MRD
216    str r1, [r0, #INDEX_DMC_T_MRD]
217
218    ldr r1, =DMC_DDR_t_RAS
219    str r1, [r0, #INDEX_DMC_T_RAS]
220
221    ldr r1, =DMC_DDR_t_RC
222    str r1, [r0, #INDEX_DMC_T_RC]
223
224    ldr r1, =DMC_DDR_t_RCD
225    ldr r2, =DMC_DDR_schedule_RCD
226    orr r1, r1, r2
227    str r1, [r0, #INDEX_DMC_T_RCD]
228
229    ldr r1, =DMC_DDR_t_RFC
230    ldr r2, =DMC_DDR_schedule_RFC
231    orr r1, r1, r2
232    str r1, [r0, #INDEX_DMC_T_RFC]
233
234    ldr r1, =DMC_DDR_t_RP
235    ldr r2, =DMC_DDR_schedule_RP
236    orr r1, r1, r2
237    str r1, [r0, #INDEX_DMC_T_RP]
238
239    ldr r1, =DMC_DDR_t_RRD
240    str r1, [r0, #INDEX_DMC_T_RRD]
241
242    ldr r1, =DMC_DDR_t_WR
243    str r1, [r0, #INDEX_DMC_T_WR]
244
245    ldr r1, =DMC_DDR_t_WTR
246    str r1, [r0, #INDEX_DMC_T_WTR]
247
248    ldr r1, =DMC_DDR_t_XP
249    str r1, [r0, #INDEX_DMC_T_XP]
250
251    ldr r1, =DMC_DDR_t_XSR
252    str r1, [r0, #INDEX_DMC_T_XSR]
253
254    ldr r1, =DMC_DDR_t_ESR
255    str r1, [r0, #INDEX_DMC_T_ESR]
256
257    ldr r1, =DMC1_MEM_CFG
258    str r1, [r0, #INDEX_DMC_MEMORY_CFG]
259
260    ldr r1, =DMC1_MEM_CFG2
261    str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
262
263    ldr r1, =DMC1_CHIP0_CFG
264    str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
265
266    ldr r1, =DMC_DDR_32_CFG
267    str r1, [r0, #INDEX_DMC_USER_CONFIG]
268
269    @DMC0 DDR Chip 0 configuration direct command reg
270    ldr r1, =DMC_NOP0
271    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
272
273    @Precharge All
274    ldr r1, =DMC_PA0
275    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
276
277    @Auto Refresh 2 time
278    ldr r1, =DMC_AR0
279    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
280    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
281
282    @MRS
283    ldr r1, =DMC_mDDR_EMR0
284    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
285
286    @Mode Reg
287    ldr r1, =DMC_mDDR_MR0
288    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
289
290#if S3C6410_POP_A
291    ldr r1, =DMC1_CHIP1_CFG
292    str r1, [r0, #INDEX_DMC_CHIP_1_CFG]
293
294    @DMC0 DDR Chip 0 configuration direct command reg
295    ldr r1, =DMC_NOP1
296    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
297
298    @Precharge All
299    ldr r1, =DMC_PA1
300    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
301
302    @Auto Refresh 2 time
303    ldr r1, =DMC_AR1
304    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
305    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
306
307    @MRS
308    ldr r1, =DMC_mDDR_EMR1
309    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
310
311    @Mode Reg
312    ldr r1, =DMC_mDDR_MR1
313    str r1, [r0, #INDEX_DMC_DIRECT_CMD]
314#endif
315
316    @Enable DMC1
317    mov r1, #0x0
318    str r1, [r0, #INDEX_DMC_MEMC_CMD]
319
3201:
321    ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
322    mov r2, #0x3
323    and r1, r1, r2
324    cmp r1, #0x1
325    bne 1b
326    nop
327
328    ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000
329
330    ldr r1, [r0, #OTHERS_OFFSET]
331    mov r2, #0x40
332    orr r1, r1, r2
333    str r1, [r0, #OTHERS_OFFSET]
334
335    nop
336    nop
337    nop
338    nop
339    nop
340
341    ldr r2, =0x80
342    orr r1, r1, r2
343    str r1, [r0, #OTHERS_OFFSET]
344
3452:
346    ldr r1, [r0, #OTHERS_OFFSET]
347    ldr r2, =0xf00
348    and r1, r1, r2
349    cmp r1, #0xf00
350    bne 2b
351
352    mov r1, #0xff00
353    orr r1, r1, #0xff
354    str r1, [r0, #APLL_LOCK_OFFSET]
355    str r1, [r0, #MPLL_LOCK_OFFSET]
356    str r1, [r0, #EPLL_LOCK_OFFSET]
357/* CLKUART(=66.5Mhz) = CLKUART_input(532/2=266Mhz) / (UART_RATIO(3)+1) */
358/* CLKUART(=50Mhz) = CLKUART_input(400/2=200Mhz) / (UART_RATIO(3)+1) */
359/* Now, When you use UART CLK SRC by EXT_UCLK1, We support 532MHz & 400MHz value */
360
361    ldr r1, [r0, #CLK_DIV2_OFFSET]
362    bic r1, r1, #0x70000
363    orr r1, r1, #0x30000
364    str r1, [r0, #CLK_DIV2_OFFSET]
365
366
367    ldr r1, [r0, #CLK_DIV0_OFFSET] /*Set Clock Divider*/
368    bic r1, r1, #0x30000
369    bic r1, r1, #0xff00
370    bic r1, r1, #0xff
371    ldr r2, =CLK_DIV_VAL
372    orr r1, r1, r2
373    str r1, [r0, #CLK_DIV0_OFFSET]
374
375    ldr r1, =APLL_VAL
376    str r1, [r0, #APLL_CON_OFFSET]
377    ldr r1, =MPLL_VAL
378    str r1, [r0, #MPLL_CON_OFFSET]
379
380    ldr r1, =0x80200203 /* FOUT of EPLL is 96MHz */
381    str r1, [r0, #EPLL_CON0_OFFSET]
382    ldr r1, =0x0
383    str r1, [r0, #EPLL_CON1_OFFSET]
384
385    ldr r1, [r0, #CLK_SRC_OFFSET] /* APLL, MPLL, EPLL select to Fout */
386
387    ldr r2, =0x2007
388    orr r1, r1, r2
389
390    str r1, [r0, #CLK_SRC_OFFSET]
391
392    /* wait at least 200us to stablize all clock */
393    mov r1, #0x10000
3943: subs r1, r1, #1
395    bne 3b
396
397    ldr r1, [r0, #OTHERS_OFFSET]
398    orr r1, r1, #0x20
399    str r1, [r0, #OTHERS_OFFSET]
400
401
402    /* set GPIO to enable UART */
403    @ GPIO setting for UART
404    ldr r0, =ELFIN_GPIO_BASE
405    ldr r1, =0x2222
406    str r1, [r0, #GPBCON_OFFSET]
407
408    ldr r0, =ELFIN_UART_BASE + ELFIN_UART3_OFFSET @0x7F005c00 uart 3
409    mov r1, #0x0
410    str r1, [r0, #UFCON_OFFSET]
411    str r1, [r0, #UMCON_OFFSET]
412
413    mov r1, #0x3 @was 0.
414    str r1, [r0, #ULCON_OFFSET]
415
416    ldr r1, =0xe45 /* UARTCLK SRC = 11 => EXT_UCLK1*/
417
418    str r1, [r0, #UCON_OFFSET]
419
420    ldr r1, =0x22
421    str r1, [r0, #UBRDIV_OFFSET]
422
423    ldr r1, =0x1FFF
424    str r1, [r0, #UDIVSLOT_OFFSET]
425
426    /* resuming? */
427
428        ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)
429        ldr r1, [r0]
430        bic r1, r1, #0xfffffff7
431        cmp r1, #0x8
432        beq wakeup_reset
433
434    /* no, cold boot */
435
436    ldr r0, =ELFIN_UART_BASE + ELFIN_UART3_OFFSET
437    ldr r1, =0x55
438    str r1, [r0, #UTXH_OFFSET] @'U'
439                                /* >> CFG_VIDEO_LOGO_MAX_SIZE */
440#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
441
442
443    ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
444    sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
445    sub sp, r0, #12 /* leave 3 words for abort-stack */
446clear_bss:
447    ldr r0, _bss_start /* find start of bss segment */
448    ldr r1, _bss_end /* stop here */
449    mov r2, #0x00000000 /* clear */
450
451clbss_l:
452    str r2, [r0] /* clear loop... */
453    add r0, r0, #4
454    cmp r0, r1
455    ble clbss_l
456
457    b _steppingstone_done
458
459    /* resume */
460
461wakeup_reset:
462
463    ldr r0, =ELFIN_UART_BASE + ELFIN_UART3_OFFSET
464    ldr r1, =0x4b4b4b4b
465    str r1, [r0, #UTXH_OFFSET]
466
467    /*Clear wakeup status register*/
468    ldr r0, =(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET)
469    ldr r1, [r0]
470    str r1, [r0]
471
472#if 0
473        /*LED test*/
474        ldr r0, =ELFIN_GPIO_BASE
475        ldr r1, =0x3000
476        str r1, [r0, #GPNDAT_OFFSET]
477#endif
478
479    /*Load return address and jump to kernel*/
480    ldr r0, =(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET)
481    ldr r1, [r0] /* r1 = physical address of s3c6400_cpu_resume function*/
482    mov pc, r1 /*Jump to kernel (sleep-s3c6400.S)*/
483    nop
484    nop
485
4864:
487    b 4b
488

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