| 1 | /* |
| 2 | * (C) Copyright 2007 OpenMoko, Inc. |
| 3 | * |
| 4 | * Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #define __ASM_MODE__ |
| 23 | #include <neo_gta02.h> |
| 24 | |
| 25 | #define S3C2410_MISCCR_nEN_SCLK0 (1 << 17) |
| 26 | #define S3C2410_MISCCR_nEN_SCLK1 (1 << 18) |
| 27 | #define S3C2410_MISCCR_nEN_SCLKE (1 << 19) |
| 28 | |
| 29 | |
| 30 | |
| 31 | .globl _start, processor_id, is_jtag |
| 32 | |
| 33 | _start: b start_code |
| 34 | /* if we are injected by JTAG, the script sets _istag content to nonzero */ |
| 35 | is_jtag: |
| 36 | .word 0 |
| 37 | |
| 38 | /* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script |
| 39 | * we need to go through this hassle because before this moment, SDRAM is not |
| 40 | * working so we can't prep it from JTAG |
| 41 | */ |
| 42 | |
| 43 | _steppingstone_done: |
| 44 | ldr pc, _start_armboot |
| 45 | |
| 46 | _start_armboot: |
| 47 | .word start_qi |
| 48 | |
| 49 | _TEXT_BASE: |
| 50 | .word TEXT_BASE |
| 51 | |
| 52 | processor_id: |
| 53 | .word 0 |
| 54 | .word 0x41129200 /* s3c2442 ID */ |
| 55 | .word 0x410fb760 /* s3c6410 ID */ |
| 56 | |
| 57 | /* |
| 58 | * These are defined in the board-specific linker script. |
| 59 | */ |
| 60 | .globl _bss_start |
| 61 | _bss_start: |
| 62 | .word __bss_start |
| 63 | |
| 64 | .globl _bss_end |
| 65 | _bss_end: |
| 66 | .word _end |
| 67 | |
| 68 | start_code: |
| 69 | /* |
| 70 | * set the cpu to SVC32 mode |
| 71 | */ |
| 72 | mrs r0,cpsr |
| 73 | bic r0,r0,#0x1f |
| 74 | orr r0,r0,#0xd3 |
| 75 | msr cpsr,r0 |
| 76 | |
| 77 | /* |
| 78 | * detect processor we are running on |
| 79 | * s3c2442: 0x4112920x |
| 80 | * s3c6410: 0x410fb76x |
| 81 | */ |
| 82 | MRC p15, 0 ,r0, c0, c0, 0 |
| 83 | ldr r1, =processor_id |
| 84 | str r0, [r1] |
| 85 | ldr r2, [r1, #4] |
| 86 | |
| 87 | and r0, #0xfffffff0 |
| 88 | cmp r0, r2 |
| 89 | beq startup_2442 |
| 90 | |
| 91 | /* 6410 startup */ |
| 92 | startup_6410: |
| 93 | |
| 94 | mov r0, #0 |
| 95 | str r0, [r1] |
| 96 | |
| 97 | /* 2442 startup */ |
| 98 | startup_2442: |
| 99 | # define pWTCON 0x53000000 |
| 100 | |
| 101 | ldr r0, =pWTCON |
| 102 | mov r1, #0x0 |
| 103 | str r1, [r0] |
| 104 | |
| 105 | /* |
| 106 | * mask all IRQs by setting all bits in the INTMR - default |
| 107 | */ |
| 108 | # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ |
| 109 | # define INTSUBMSK 0x4A00001C |
| 110 | # define INTSUBMSK_val 0x0000ffff |
| 111 | |
| 112 | mov r1, #0xffffffff |
| 113 | ldr r0, =INTMSK |
| 114 | str r1, [r0] |
| 115 | |
| 116 | ldr r1, =INTSUBMSK_val |
| 117 | ldr r0, =INTSUBMSK |
| 118 | str r1, [r0] |
| 119 | |
| 120 | |
| 121 | /* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */ |
| 122 | # define CAMDIVN 0x4C000018 |
| 123 | |
| 124 | ldr r0, =CAMDIVN |
| 125 | mov r1, #0 |
| 126 | str r1, [r0] |
| 127 | |
| 128 | /* Clock asynchronous mode */ |
| 129 | mrc p15, 0, r1, c1, c0, 0 |
| 130 | orr r1, r1, #0xc0000000 |
| 131 | mcr p15, 0, r1, c1, c0, 0 |
| 132 | |
| 133 | #define LOCKTIME 0x4c000000 |
| 134 | |
| 135 | ldr r0, =LOCKTIME |
| 136 | mov r1, #0xffffff |
| 137 | str r1, [r0] |
| 138 | |
| 139 | # define UPLLCON 0x4c000008 |
| 140 | # define MPLLCON_val ((142 << 12) + (7 << 4) + 1) |
| 141 | # define UPLLCON_val (( 88 << 12) + (8 << 4) + 2) |
| 142 | |
| 143 | ldr r0, =UPLLCON |
| 144 | ldr r1, =UPLLCON_val |
| 145 | str r1, [r0] |
| 146 | |
| 147 | /* Page 7-19, seven nops between UPLL and MPLL */ |
| 148 | nop |
| 149 | nop |
| 150 | nop |
| 151 | nop |
| 152 | nop |
| 153 | nop |
| 154 | nop |
| 155 | |
| 156 | ldr r1, =MPLLCON_val |
| 157 | str r1, [r0, #-4] /* MPLLCON */ |
| 158 | |
| 159 | # define CLKDIVN 0x4C000014 /* clock divisor register */ |
| 160 | # define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */ |
| 161 | |
| 162 | /* FCLK:HCLK:PCLK = 1:3:6 */ |
| 163 | ldr r0, =CLKDIVN |
| 164 | mov r1, #CLKDIVN_val |
| 165 | str r1, [r0] |
| 166 | |
| 167 | /* enable only CPU peripheral block clocks we actually use */ |
| 168 | ldr r0, =0x4c00000c /* clkcon */ |
| 169 | ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */ |
| 170 | str r1, [r0] |
| 171 | |
| 172 | /* gpio UART2 init, H port */ |
| 173 | ldr r0, =0x56000070 |
| 174 | ldr r1, =0x001AAAAA |
| 175 | str r1, [r0] |
| 176 | |
| 177 | /* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */ |
| 178 | ldr r0, =0x56000000 /* GPJ base */ |
| 179 | ldr r1, [r0, #0xd0] /* GPJCON */ |
| 180 | orr r1, r1, #(1 << 16) |
| 181 | str r1, [r0, #0xd0] |
| 182 | |
| 183 | ldr r1, [r0, #0xd4] /* GPJDAT */ |
| 184 | orr r1, r1, #(1 << 8) |
| 185 | str r1, [r0, #0xd4] |
| 186 | |
| 187 | |
| 188 | /* init uart2 */ |
| 189 | ldr r0, =0x50008000 |
| 190 | mov r1, #0x03 |
| 191 | str r1, [r0] |
| 192 | ldr r1, =0x245 |
| 193 | str r1, [r0, #0x04] |
| 194 | mov r1, #0x00 |
| 195 | str r1, [r0, #0x08] |
| 196 | mov r1, #0x00 |
| 197 | str r1, [r0, #0x0c] |
| 198 | mov r1, #0x11 |
| 199 | str r1, [r0, #0x28] |
| 200 | |
| 201 | ldr r0, =0x50008000 |
| 202 | ldr r1, =0x54 |
| 203 | str r1, [r0, #0x20] |
| 204 | |
| 205 | /* reset nand controller, or it is dead to us */ |
| 206 | |
| 207 | mov r1, #0x4E000000 |
| 208 | ldr r2, =0xfff0 @ initial value tacls=3,rph0=7,rph1=7 |
| 209 | ldr r3, [r1, #0] |
| 210 | orr r3, r3, r2 |
| 211 | str r3, [r1, #0] |
| 212 | |
| 213 | ldr r3, [r1, #4] |
| 214 | orr r3, r3, #1 @ enable nand controller |
| 215 | str r3, [r1, #4] |
| 216 | |
| 217 | |
| 218 | /* take sdram out of power down */ |
| 219 | ldr r0, =0x56000080 /* misccr */ |
| 220 | ldr r1, [ r0 ] |
| 221 | bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE) |
| 222 | str r1, [ r0 ] |
| 223 | |
| 224 | /* ensure signals stabalise */ |
| 225 | mov r1, #128 |
| 226 | 1: subs r1, r1, #1 |
| 227 | bpl 1b |
| 228 | |
| 229 | bl cpu_init_crit |
| 230 | |
| 231 | /* ensure some refresh has happened */ |
| 232 | ldr r1, =0xfffff |
| 233 | 1: subs r1, r1, #1 |
| 234 | bpl 1b |
| 235 | |
| 236 | /* capture full EINT situation into gstatus 4 */ |
| 237 | |
| 238 | ldr r0, =0x4A000000 /* SRCPND */ |
| 239 | ldr r1, [ r0 ] |
| 240 | and r1, r1, #0xf |
| 241 | |
| 242 | ldr r0, =0x560000BC /* gstatus4 */ |
| 243 | str r1, [ r0 ] |
| 244 | |
| 245 | ldr r0, =0x560000A8 /* EINTPEND */ |
| 246 | ldr r1, [ r0 ] |
| 247 | ldr r0, =0xfff0 |
| 248 | and r1, r1, r0 |
| 249 | ldr r0, =0x560000BC /* gstatus4 */ |
| 250 | ldr r0, [ r0 ] |
| 251 | orr r1, r1, r0 |
| 252 | ldr r0, =0x560000BC /* gstatus4 */ |
| 253 | str r1, [ r0 ] |
| 254 | |
| 255 | /* test for resume */ |
| 256 | |
| 257 | ldr r1, =0x560000B4 /* gstatus2 */ |
| 258 | ldr r0, [ r1 ] |
| 259 | tst r0, #0x02 /* is this resume from power down */ |
| 260 | /* well, if it was, we are going to jump to |
| 261 | * whatever address we stashed in gstatus3, |
| 262 | * and gstatus4 will hold the wake interrupt |
| 263 | * source for the OS to look at |
| 264 | */ |
| 265 | ldrne pc, [r1, #4] |
| 266 | |
| 267 | |
| 268 | /* >> CFG_VIDEO_LOGO_MAX_SIZE */ |
| 269 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 270 | |
| 271 | stack_setup: |
| 272 | ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ |
| 273 | sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ |
| 274 | sub sp, r0, #12 /* leave 3 words for abort-stack */ |
| 275 | |
| 276 | clear_bss: |
| 277 | ldr r0, _bss_start /* find start of bss segment */ |
| 278 | ldr r1, _bss_end /* stop here */ |
| 279 | mov r2, #0x00000000 /* clear */ |
| 280 | |
| 281 | clbss_l: |
| 282 | str r2, [r0] /* clear loop... */ |
| 283 | add r0, r0, #4 |
| 284 | cmp r0, r1 |
| 285 | ble clbss_l |
| 286 | |
| 287 | /* we are going to jump into the C part of the init now */ |
| 288 | spin: |
| 289 | b _steppingstone_done |
| 290 | |
| 291 | /* |
| 292 | ************************************************************************* |
| 293 | * |
| 294 | * CPU_init_critical registers |
| 295 | * |
| 296 | * setup important registers |
| 297 | * setup memory timing |
| 298 | * |
| 299 | ************************************************************************* |
| 300 | */ |
| 301 | |
| 302 | cpu_init_crit: |
| 303 | |
| 304 | /* |
| 305 | * flush v4 I/D caches |
| 306 | */ |
| 307 | mov r0, #0 |
| 308 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
| 309 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
| 310 | |
| 311 | /* |
| 312 | * disable MMU stuff and caches |
| 313 | */ |
| 314 | mrc p15, 0, r0, c1, c0, 0 |
| 315 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) |
| 316 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) |
| 317 | orr r0, r0, #0x00000002 @ set bit 2 (A) Align |
| 318 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache |
| 319 | mcr p15, 0, r0, c1, c0, 0 |
| 320 | |
| 321 | /* |
| 322 | * before relocating, we have to setup RAM timing |
| 323 | * because memory timing is board-dependend, you will |
| 324 | * find a lowlevel_init.S in your board directory. |
| 325 | */ |
| 326 | mov ip, lr |
| 327 | |
| 328 | bl lowlevel_init |
| 329 | |
| 330 | mov lr, ip |
| 331 | mov pc, lr |
| 332 | |
| 333 | |
