Root/usbboot/xburst_stage1/board_4750.c

1/*
2 * Board init routines.
3 *
4 * Copyright 2009 (C) Qi Hardware Inc.,
5 * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 3 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
19 * Boston, MA 02110-1301, USA
20 */
21
22#include "jz4750.h"
23#include "configs.h"
24
25void gpio_init_4750(void)
26{
27    __gpio_as_sdram_32bit();
28    __gpio_as_uart1();
29    __gpio_as_uart0();
30    __gpio_as_uart2();
31    __gpio_as_uart3();
32    __gpio_as_nand_8bit();
33}
34
35void ccpll_init_4750(void)
36{
37    register unsigned int cfcr, plcr1;
38    int n2FR[33] = {
39        0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
40        7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
41        9
42    };
43// int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:L:M */
44    int nf, pllout2;
45
46    cfcr = ~CPM_CPCCR_ECS &
47        (n2FR[1] << CPM_CPCCR_CDIV_BIT) |
48        (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
49        (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
50        (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
51        (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
52
53    pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
54
55    nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
56    plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
57        (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
58        (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
59        (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
60        CPM_CPPCR_PLLEN; /* enable PLL */
61
62    /* init PLL */
63    REG_CPM_CPCCR = cfcr;
64    REG_CPM_CPPCR = plcr1;
65}
66
67int nf, pllout2;
68
69void pll_init_4750(void)
70{
71    register unsigned int cfcr, plcr1,tmp;
72    int n2FR[33] = {
73        0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
74        7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
75        9
76    };
77    int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
78
79    cfcr = CPM_CPCCR_PCS |
80        (n2FR[1] << CPM_CPCCR_CDIV_BIT) |
81        (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
82        (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
83        (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
84        (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
85
86    if (CFG_EXTAL > 16000000)
87        cfcr |= CPM_CPCCR_ECS;
88
89    pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
90
91    /* Init USB Host clock, pllout2 must be n*48MHz */
92// REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
93
94    nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
95    plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
96        (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
97        (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
98        (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
99        CPM_CPPCR_PLLEN; /* enable PLL */
100
101    cfcr |= CPM_CPCCR_UCS; /* set PLL as UDC PHY*/
102    tmp = pllout2 / 1000000 / 12 - 1;
103    cfcr |= (tmp << CPM_CPCCR_UDIV_BIT); /* set UDC DIV*/
104
105    /* init PLL */
106    REG_CPM_CPCCR = cfcr;
107    REG_CPM_CPPCR = plcr1;
108}
109
110void sdram_init_4750(void)
111{
112    register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
113    register unsigned int sdemode; /*SDRAM Extended Mode*/
114
115    unsigned int cas_latency_sdmr[2] = {
116        EMC_SDMR_CAS_2,
117        EMC_SDMR_CAS_3,
118    };
119
120    unsigned int cas_latency_dmcr[2] = {
121        1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
122        2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
123    };
124
125    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
126
127    cpu_clk = CFG_CPU_SPEED;
128    mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
129
130    /* set REG_EMC_DMAR0 for supporting 128MB sdram on DCS0 */
131    REG_EMC_DMAR0 = EMC_DMAR0_BASE | EMC_DMAR_MASK_128_128;
132
133    REG_EMC_BCR = 0; /* Disable bus release */
134    REG_EMC_RTCSR = 0; /* Disable clock for counting */
135
136    /* Basic DMCR value */
137    dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
138        ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
139        (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
140        (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
141        EMC_DMCR_EPIN |
142        cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
143
144    /* SDRAM timimg */
145    ns = 1000000000 / mem_clk;
146    tmp = SDRAM_TRAS/ns;
147    if (tmp < 4) tmp = 4;
148    if (tmp > 11) tmp = 11;
149    dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
150    tmp = SDRAM_RCD/ns;
151    if (tmp > 3) tmp = 3;
152    dmcr |= (tmp << EMC_DMCR_RCD_BIT);
153    tmp = SDRAM_TPC/ns;
154    if (tmp > 7) tmp = 7;
155    dmcr |= (tmp << EMC_DMCR_TPC_BIT);
156    tmp = SDRAM_TRWL/ns;
157    if (tmp > 3) tmp = 3;
158    dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
159    tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
160    if (tmp > 14) tmp = 14;
161    dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
162
163    /* SDRAM mode value */
164    sdmode = EMC_SDMR_BT_SEQ |
165         EMC_SDMR_OM_NORMAL |
166         EMC_SDMR_BL_4 |
167         cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
168
169    /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
170    REG_EMC_DMCR = dmcr;
171    REG8(EMC_SDMR0|sdmode) = 0;
172
173    if (CONFIG_MOBILE_SDRAM == 1)
174        /* Mobile SDRAM Extended Mode Register */
175        sdemode = EMC_SDMR_SET_BA1 | EMC_SDMR_DS_FULL | EMC_SDMR_PRSR_ALL;
176
177    /* Wait for precharge, > 200us */
178    tmp = (cpu_clk / 1000000) * 1000;
179    while (tmp--);
180
181    /* Stage 2. Enable auto-refresh */
182    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
183
184    tmp = SDRAM_TREF/ns;
185    tmp = tmp/64 + 1;
186    if (tmp > 0xff) tmp = 0xff;
187    REG_EMC_RTCOR = tmp;
188    REG_EMC_RTCNT = 0;
189    REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
190
191    /* Wait for number of auto-refresh cycles */
192    tmp = (cpu_clk / 1000000) * 1000;
193    while (tmp--);
194
195     /* Stage 3. Mode Register Set */
196    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET | EMC_DMCR_MBSEL_B0;
197    REG8(EMC_SDMR0|sdmode) = 0;
198
199    if (CONFIG_MOBILE_SDRAM == 1)
200        REG8(EMC_SDMR0|sdemode) = 0; /* Set Mobile SDRAM Extended Mode Register */
201
202    /* Set back to basic DMCR value */
203    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
204
205    /* everything is ok now */
206}
207
208void serial_setbrg_4750(void)
209{
210    volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
211    volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
212    volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
213    u32 baud_div, tmp;
214
215    baud_div = (REG_CPM_CPCCR & CPM_CPCCR_ECS) ?
216        (CFG_EXTAL / 32 / CONFIG_BAUDRATE) : (CFG_EXTAL / 16 / CONFIG_BAUDRATE);
217    tmp = *uart_lcr;
218    tmp |= UART_LCR_DLAB;
219    *uart_lcr = tmp;
220
221    *uart_dlhr = (baud_div >> 8) & 0xff;
222    *uart_dllr = baud_div & 0xff;
223
224    tmp &= ~UART_LCR_DLAB;
225    *uart_lcr = tmp;
226}
227
228

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