| 1 | # Configuration variables: |
| 2 | # STAGE1_FILE, STAGE2_FILE |
| 3 | |
| 4 | set STAGE1_FILE firmware/spl_stage1.bin |
| 5 | set STAGE2_FILE firmware/spl_stage2_usb.bin |
| 6 | |
| 7 | set EXTCLK 12 # Define the external crystal in MHz |
| 8 | set CPUSPEED 252 # Define the PLL output frequency |
| 9 | set PHMDIV 3 # Define the frequency divider ratio of PLL=CCLK:PCLK=HCLK=MCLK |
| 10 | set BAUDRATE 57600 # Define the uart baudrate |
| 11 | set USEUART 0 # UART number |
| 12 | |
| 13 | set SDRAM_BUSWIDTH 16 # The bus width of the SDRAM in bits (16|32) |
| 14 | set SDRAM_BANKS 4 # The bank number (2|4) |
| 15 | set SDRAM_ROWADDR 13 # Row address width in bits (11-13) |
| 16 | set SDRAM_COLADDR 9 # Column address width in bits (8-12) |
| 17 | set SDRAM_ISMOBILE 0 # Define whether SDRAM is mobile SDRAM (only or Jz4750), 1: yes 0: no |
| 18 | set SDRAM_ISBUSSHARE 1 # Define whether SDRAM bus share with NAND 1:shared 0:unshared |
| 19 | |
| 20 | set NAND_BUSWIDTH 8 # The width of the NAND flash chip in bits (8|16|32) |
| 21 | set NAND_ROWCYCLES 3 # The row address cycles (2|3) |
| 22 | set NAND_PAGESIZE 2048 # The page size of the NAND chip in bytes(512|2048|4096) |
| 23 | set NAND_PAGEPERBLOCK 128 # The page number per block |
| 24 | set NAND_FORCEERASE 1 # The force to erase flag (0|1) |
| 25 | set NAND_OOBSIZE 64 # OOB size in byte |
| 26 | set NAND_ECCPOS 3 # Specify the ECC offset inside the oob data (0-[oobsize-1]) |
| 27 | set NAND_BADBLOCKPOS 0 # Specify the badblock flag offset inside the oob (0-[oobsize-1]) |
| 28 | set NAND_BADBLOCKPAGE 0 # Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1]) |
| 29 | set NAND_PLANENUM 1 # The planes number of target nand flash |
| 30 | set NAND_BCHBIT 8 # Specify the hardware BCH algorithm for 4750 (4|8) |
| 31 | set NAND_WPPIN 0 # Specify the write protect pin number |
| 32 | set NAND_BLOCKPERCHIP 4096 # Specify the block number per chip,0 means ignore |
| 33 | |
| 34 | rebuildcfg |
| 35 | |
