| 1 | /* This file is based on code by Ingenic Semiconductor Co., Ltd. */ |
| 2 | |
| 3 | #ifndef __INGENIC__H__ |
| 4 | #define __INGENIC__H__ |
| 5 | |
| 6 | #include <stdint.h> |
| 7 | |
| 8 | #define VR_GET_CPU_INFO 0x00 |
| 9 | #define VR_SET_DATA_ADDRESS 0x01 |
| 10 | #define VR_SET_DATA_LENGTH 0x02 |
| 11 | #define VR_FLUSH_CACHES 0x03 |
| 12 | #define VR_PROGRAM_START1 0x04 |
| 13 | #define VR_PROGRAM_START2 0x05 |
| 14 | #define VR_NOR_OPS 0x06 |
| 15 | #define VR_NAND_OPS 0x07 |
| 16 | #define VR_SDRAM_OPS 0x08 |
| 17 | #define VR_CONFIGRATION 0x09 |
| 18 | #define VR_GET_NUM 0x0a |
| 19 | |
| 20 | #define CMDSET_SPL 1 |
| 21 | #define CMDSET_USBBOOT 2 |
| 22 | |
| 23 | #define INGENIC_STAGE1 1 |
| 24 | #define INGENIC_STAGE2 2 |
| 25 | |
| 26 | #define STAGE1_DEBUG_BOOT 0 |
| 27 | #define STAGE1_DEBUG_MEMTEST 1 |
| 28 | #define STAGE1_DEBUG_GPIO_SET 2 |
| 29 | #define STAGE1_DEBUG_GPIO_CLEAR 3 |
| 30 | |
| 31 | #define STAGE1_BASE 0x2000 |
| 32 | #define STAGE2_CODESIZE 0x400000 |
| 33 | #define SDRAM_BASE 0x80000000 |
| 34 | |
| 35 | #define STAGE2_IOBUF (2048 * 128) |
| 36 | |
| 37 | #define DS_flash_info 0 |
| 38 | #define DS_hand 1 |
| 39 | |
| 40 | #define SDRAM_LOAD 0 |
| 41 | |
| 42 | #define NAND_QUERY 0 |
| 43 | #define NAND_INIT 1 |
| 44 | #define NAND_MARK_BAD 2 |
| 45 | #define NAND_READ_OOB 3 |
| 46 | #define NAND_READ_RAW 4 |
| 47 | #define NAND_ERASE 5 |
| 48 | #define NAND_READ 6 |
| 49 | #define NAND_PROGRAM 7 |
| 50 | #define NAND_READ_TO_RAM 8 |
| 51 | |
| 52 | #define OOB_ECC 0 |
| 53 | #define OOB_NO_ECC 1 |
| 54 | #define NO_OOB 2 |
| 55 | #define NAND_RAW (1 << 7) |
| 56 | |
| 57 | #define PROGRESS_INIT 0 |
| 58 | #define PROGRESS_UPDATE 1 |
| 59 | #define PROGRESS_FINI 2 |
| 60 | |
| 61 | typedef struct { |
| 62 | /* debug args */ |
| 63 | uint8_t debug_ops; |
| 64 | uint8_t pin_num; |
| 65 | uint32_t start; |
| 66 | uint32_t size; |
| 67 | } __attribute__((packed)) ingenic_stage1_debug_t; |
| 68 | |
| 69 | typedef struct { |
| 70 | /* CPU ID */ |
| 71 | uint32_t cpu_id; |
| 72 | |
| 73 | /* PLL args */ |
| 74 | uint8_t ext_clk; |
| 75 | uint8_t cpu_speed; |
| 76 | uint8_t phm_div; |
| 77 | uint8_t use_uart; |
| 78 | uint32_t baudrate; |
| 79 | |
| 80 | /* SDRAM args */ |
| 81 | uint8_t bus_width; |
| 82 | uint8_t bank_num; |
| 83 | uint8_t row_addr; |
| 84 | uint8_t col_addr; |
| 85 | uint8_t is_mobile; |
| 86 | uint8_t is_busshare; |
| 87 | |
| 88 | ingenic_stage1_debug_t debug; |
| 89 | } __attribute__((packed)) firmware_config_t; |
| 90 | |
| 91 | typedef struct { |
| 92 | /* nand flash info */ |
| 93 | uint32_t cpuid; /* cpu type */ |
| 94 | uint32_t nand_bw; /* bus width */ |
| 95 | uint32_t nand_rc; /* row cycle */ |
| 96 | uint32_t nand_ps; /* page size */ |
| 97 | uint32_t nand_ppb; /* page number per block */ |
| 98 | uint32_t nand_force_erase; |
| 99 | uint32_t nand_pn; /* page number in total */ |
| 100 | uint32_t nand_os; /* oob size */ |
| 101 | uint32_t nand_eccpos; |
| 102 | uint32_t nand_bbpage; |
| 103 | uint32_t nand_bbpos; |
| 104 | uint32_t nand_plane; |
| 105 | uint32_t nand_bchbit; |
| 106 | uint32_t nand_wppin; |
| 107 | uint32_t nand_bpc; /* block number per chip */ |
| 108 | } nand_config_t; |
| 109 | |
| 110 | typedef struct { |
| 111 | uint8_t vid; |
| 112 | uint8_t pid; |
| 113 | uint8_t chip; |
| 114 | uint8_t page; |
| 115 | uint8_t plane; |
| 116 | } nand_info_t; |
| 117 | |
| 118 | |
| 119 | typedef struct { |
| 120 | void (*cmdset_change)(uint32_t cmdset, void *arg); |
| 121 | void (*progress)(int action, int value, int max, void *arg); |
| 122 | } ingenic_callbacks_t; |
| 123 | |
| 124 | void *ingenic_open(void *usb_hndl); |
| 125 | void ingenic_close(void *hndl); |
| 126 | void ingenic_set_callbacks(void *hndl, const ingenic_callbacks_t *callbacks, void *arg); |
| 127 | |
| 128 | int ingenic_redetect(void *hndl); |
| 129 | int ingenic_cmdset(void *hndl); |
| 130 | int ingenic_type(void *hndl); |
| 131 | uint32_t ingenic_sdram_size(void *hndl); |
| 132 | |
| 133 | int ingenic_rebuild(void *hndl); |
| 134 | int ingenic_loadstage(void *hndl, int id, const char *filename); |
| 135 | int ingenic_stage1_debugop(void *device, const char *filename, uint32_t op, uint32_t pin, uint32_t base, uint32_t size); |
| 136 | int ingenic_memtest(void *hndl, const char *filename, uint32_t base, uint32_t size, uint32_t *fail); |
| 137 | |
| 138 | int ingenic_configure_stage2(void *hndl); |
| 139 | int ingenic_load_sdram(void *hndl, void *data, uint32_t base, uint32_t size); |
| 140 | int ingenic_load_sdram_file(void *hndl, uint32_t base, const char *filename); |
| 141 | int ingenic_go(void *hndl, uint32_t address); |
| 142 | |
| 143 | int ingenic_query_nand(void *hndl, int cs, nand_info_t *info); |
| 144 | int ingenic_dump_nand(void *hndl, int cs, int start, int pages, int type, const char *filename); |
| 145 | int ingenic_program_nand(void *hndl, int cs, int start, int type, const char *filename); |
| 146 | int ingenic_erase_nand(void *hndl, int cs, int start, int blocks); |
| 147 | int ingenic_load_nand(void *hndl, int cs, int start, int pages, uint32_t base); |
| 148 | |
| 149 | #endif |
| 150 | |
