| 1 | # [PLL] |
| 2 | EXTCLK = 12 #Define the external crystal in MHz |
| 3 | CPUSPEED = 240 #Define the PLL output frequency |
| 4 | PHMDIV = 3 #Define the frequency divider ratio of PLL=CCLK:PCLK=HCLK=MCLK |
| 5 | BOUDRATE = 115200 #Define the uart boudrate |
| 6 | USEUART = 1 #Use which uart, 0/1 for jz4740,0/1/2/3 for jz4750 |
| 7 | |
| 8 | # [SDRAM] |
| 9 | BUSWIDTH = 32 #The bus width of the SDRAM in bits (16|32) |
| 10 | BANKS = 4 #The bank number (2|4) |
| 11 | ROWADDR = 12 #Row address width in bits (11-13) |
| 12 | COLADDR = 9 #Column address width in bits (8-12) |
| 13 | ISMOBILE = 1 #Define whether SDRAM is mobile SDRAM, this only valid for Jz4750 ,1:yes 0:no |
| 14 | ISBUSSHARE = 0 #Define whether SDRAM bus share with NAND 1:shared 0:unshared |
| 15 | # SDRAMTYPE = 2 #Define SDRAM Type 0:sdram 1:ddr1 2:ddr2 3:mobile ddr |
| 16 | |
| 17 | # [NAND] |
| 18 | NAND_BUSWIDTH = 8 #The width of the NAND flash chip in bits (8|16|32) |
| 19 | NAND_ROWCYCLES = 3 #The row address cycles (2|3) |
| 20 | NAND_PAGESIZE = 4096 #The page size of the NAND chip in bytes(512|2048|4096) |
| 21 | NAND_PAGEPERBLOCK = 128 #The page number per block |
| 22 | NAND_FORCEERASE = 1 #The force to erase flag (0|1) |
| 23 | NAND_OOBSIZE = 128 #oob size in byte |
| 24 | NAND_ECCPOS = 24 #Specify the ECC offset inside the oob data (0-[oobsize-1]) |
| 25 | NAND_BADBLOCKPOS = 0 #Specify the badblock flag offset inside the oob (0-[oobsize-1]) |
| 26 | NAND_BADBLOCKPAGE = 0 #Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1]) |
| 27 | NAND_PLANENUM = 1 #The planes number of target nand flash |
| 28 | NAND_BCHBIT = 8 #Specify the hardware BCH algorithm for 4750 (4|8) |
| 29 | NAND_WPPIN = 0 #Specify the write protect pin number |
| 30 | NAND_BLOCKPERCHIP = 0 #Specify the block number per chip,0 means ignore |
| 31 | |
