Root/usbboot/src/ingenic_cfg.c

1/*
2 * Copyright(C) 2009 Qi Hardware Inc.,
3 * Authors: Marek Lindner <lindner_marek@yahoo.de>
4 *
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <errno.h>
20#include <confuse.h>
21#include <unistd.h>
22#include <string.h>
23#include "ingenic_cfg.h"
24#include "usb_boot_defines.h"
25
26extern unsigned int total_size;
27
28int check_dump_cfg(struct hand *h)
29{
30    printf("Now checking whether all configure args valid:");
31    /* check PLL */
32    if (h->fw_args.ext_clk > 27 || h->fw_args.ext_clk < 12) {
33        printf(" EXTCLK setting invalid!\n");
34        return 0;
35    }
36    if (h->fw_args.phm_div > 32 || h->fw_args.ext_clk < 2) {
37        printf(" PHMDIV setting invalid!\n");
38        return 0;
39    }
40    if ((h->fw_args.cpu_speed * h->fw_args.ext_clk ) % 12 != 0) {
41        printf(" CPUSPEED setting invalid!\n");
42        return 0;
43    }
44
45    /* check SDRAM */
46    if (h->fw_args.bus_width > 1 ) {
47        printf(" SDRAMWIDTH setting invalid!\n");
48        return 0;
49    }
50    if (h->fw_args.bank_num > 1 ) {
51        printf(" BANKNUM setting invalid!\n");
52        return 0;
53    }
54    if (h->fw_args.row_addr > 13 && h->fw_args.row_addr < 11 ) {
55        printf(" ROWADDR setting invalid!\n");
56        return 0;
57    }
58    if (h->fw_args.col_addr > 13 && h->fw_args.col_addr < 11 ) {
59        printf(" COLADDR setting invalid!\n");
60        return 0;
61    }
62
63    /* check NAND */
64    if (h->nand_ps < 2048 && h->nand_os > 16) {
65        printf(" PAGESIZE or OOBSIZE setting invalid!\n");
66        printf(" PAGESIZE is %d,\t OOBSIZE is %d\n",
67               h->nand_ps, h->nand_os);
68        return 0;
69    }
70    if (h->nand_ps < 2048 && h->nand_ppb > 32) {
71        printf(" PAGESIZE or PAGEPERBLOCK setting invalid!\n");
72        return 0;
73    }
74
75    if (h->nand_ps > 512 && h->nand_os <= 16) {
76        printf(" PAGESIZE or OOBSIZE setting invalid!\n");
77        printf(" PAGESIZE is %d,\t OOBSIZE is %d\n",
78               h->nand_ps, h->nand_os);
79        return 0;
80    }
81    if (h->nand_ps > 512 && h->nand_ppb < 64) {
82        printf(" PAGESIZE or PAGEPERBLOCK setting invalid!\n");
83        return 0;
84    }
85    printf(" YES\n");
86
87    printf("Current device setup information:\n");
88    printf("Crystal work at %dMHz, the CCLK up to %dMHz and PMH_CLK up to %dMHz\n",
89        h->fw_args.ext_clk,
90        (unsigned int)h->fw_args.cpu_speed * h->fw_args.ext_clk,
91        ((unsigned int)h->fw_args.cpu_speed * h->fw_args.ext_clk) / h->fw_args.phm_div);
92
93    printf("SDRAM Total size is %d MB, work in %d bank and %d bit mode\n",
94        total_size / 0x100000, 2 * (h->fw_args.bank_num + 1),
95           16 * (2 - h->fw_args.bus_width));
96
97    printf("Nand page per block %d, "
98           "Nand page size %d, "
99           "ECC offset in OOB %d, "
100           "bad block offset in OOB %d, "
101           "bad block page %d, "
102           "use %d plane mode\n",
103           h->nand_ppb,
104           h->nand_ps,
105           h->nand_eccpos,
106           h->nand_bbpos,
107           h->nand_bbpage,
108           h->nand_plane);
109    return 1;
110}
111
112int parse_configure(struct hand *h, char * file_path)
113{
114    cfg_t *cfg;
115    cfg_opt_t opts[] = {
116        CFG_INT("BOUDRATE", 57600, CFGF_NONE),
117        CFG_INT("EXTCLK", 0, CFGF_NONE),
118        CFG_INT("CPUSPEED", 0, CFGF_NONE),
119        CFG_INT("PHMDIV", 0, CFGF_NONE),
120        CFG_INT("USEUART", 0, CFGF_NONE),
121
122        CFG_INT("BUSWIDTH", 0, CFGF_NONE),
123        CFG_INT("BANKS", 0, CFGF_NONE),
124        CFG_INT("ROWADDR", 0, CFGF_NONE),
125        CFG_INT("COLADDR", 0, CFGF_NONE),
126
127        CFG_INT("ISMOBILE", 0, CFGF_NONE),
128        CFG_INT("ISBUSSHARE", 0, CFGF_NONE),
129        CFG_INT("DEBUGOPS", 0, CFGF_NONE),
130        CFG_INT("PINNUM", 0, CFGF_NONE),
131        CFG_INT("START", 0, CFGF_NONE),
132        CFG_INT("SIZE", 0, CFGF_NONE),
133
134        CFG_INT("NAND_BUSWIDTH", 0, CFGF_NONE),
135        CFG_INT("NAND_ROWCYCLES", 0, CFGF_NONE),
136        CFG_INT("NAND_PAGESIZE", 0, CFGF_NONE),
137        CFG_INT("NAND_PAGEPERBLOCK", 0, CFGF_NONE),
138        CFG_INT("NAND_FORCEERASE", 0, CFGF_NONE),
139        CFG_INT("NAND_OOBSIZE", 0, CFGF_NONE),
140        CFG_INT("NAND_ECCPOS", 0, CFGF_NONE),
141        CFG_INT("NAND_BADBLOCKPOS", 0, CFGF_NONE),
142        CFG_INT("NAND_BADBLOCKPAGE", 0, CFGF_NONE),
143        CFG_INT("NAND_PLANENUM", 0, CFGF_NONE),
144        CFG_INT("NAND_BCHBIT", 0, CFGF_NONE),
145        CFG_INT("NAND_WPPIN", 0, CFGF_NONE),
146        CFG_INT("NAND_BLOCKPERCHIP", 0, CFGF_NONE),
147
148        CFG_END()
149    };
150
151    if (access(file_path, F_OK)) {
152        fprintf(stderr, "Error - can't read configure file %s.\n",
153            file_path);
154        return -1;
155    }
156
157    cfg = cfg_init(opts, 0);
158    if (cfg_parse(cfg, file_path) == CFG_PARSE_ERROR)
159        return -1;
160
161    h->fw_args.boudrate = cfg_getint(cfg, "BOUDRATE");
162    h->fw_args.ext_clk = cfg_getint(cfg, "EXTCLK");
163    h->fw_args.cpu_speed = cfg_getint(cfg, "CPUSPEED");
164    h->fw_args.phm_div = cfg_getint(cfg, "PHMDIV");
165    h->fw_args.use_uart = cfg_getint(cfg, "USEUART");
166
167    h->fw_args.bus_width = cfg_getint(cfg, "BUSWIDTH");
168    h->fw_args.bank_num = cfg_getint(cfg, "BANKS");
169    h->fw_args.row_addr = cfg_getint(cfg, "ROWADDR");
170    h->fw_args.col_addr = cfg_getint(cfg, "COLADDR");
171
172    h->fw_args.is_mobile = cfg_getint(cfg, "ISMOBILE");
173    h->fw_args.is_busshare = cfg_getint(cfg, "ISBUSSHARE");
174    h->fw_args.debug_ops = cfg_getint(cfg, "DEBUGOPS");
175    h->fw_args.pin_num = cfg_getint(cfg, "PINNUM");
176    h->fw_args.start = cfg_getint(cfg, "START");
177    h->fw_args.size = cfg_getint(cfg, "SIZE");
178
179    h->nand_bw = cfg_getint(cfg, "NAND_BUSWIDTH");
180    h->nand_rc = cfg_getint(cfg, "NAND_ROWCYCLES");
181    h->nand_ps = cfg_getint(cfg, "NAND_PAGESIZE");
182    h->nand_ppb = cfg_getint(cfg, "NAND_PAGEPERBLOCK");
183    h->nand_force_erase = cfg_getint(cfg, "NAND_FORCEERASE");
184    h->nand_os = cfg_getint(cfg, "NAND_OOBSIZE");
185    h->nand_eccpos = cfg_getint(cfg, "NAND_ECCPOS");
186    h->nand_bbpos = cfg_getint(cfg, "NAND_BADBLOCKPOS");
187    h->nand_bbpage = cfg_getint(cfg, "NAND_BADBLOCKPAGE");
188    h->nand_plane = cfg_getint(cfg, "NAND_PLANENUM");
189    h->nand_bchbit = cfg_getint(cfg, "NAND_BCHBIT");
190    h->nand_wppin = cfg_getint(cfg, "NAND_WPPIN");
191    h->nand_bpc = cfg_getint(cfg, "NAND_BLOCKPERCHIP");
192
193    cfg_free(cfg);
194
195    if (h->fw_args.bus_width == 32)
196        h->fw_args.bus_width = 0;
197    else
198        h->fw_args.bus_width = 1;
199    h->fw_args.bank_num = h->fw_args.bank_num / 4;
200    h->fw_args.cpu_speed = h->fw_args.cpu_speed / h->fw_args.ext_clk;
201
202    total_size = (unsigned int)
203        (2 << (h->fw_args.row_addr + h->fw_args.col_addr - 1)) * 2
204        * (h->fw_args.bank_num + 1) * 2
205        * (2 - h->fw_args.bus_width);
206
207    if (check_dump_cfg(h) < 1)
208        return -1;
209
210    return 1;
211}
212

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