Root/usbboot/xburst_include/target/jz4760.h

1/*
2 * Include file for Ingenic Semiconductor's JZ4760 CPU.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 3 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
16 * Boston, MA 02110-1301, USA
17 */
18#ifndef __JZ4760_H__
19#define __JZ4760_H__
20
21#include "target/xburst_types.h"
22
23#if 0 /* if 0, for spl program */
24#define cache_unroll(base,op) \
25    __asm__ __volatile__(" \
26        .set noreorder; \
27        .set mips3; \
28        cache %1, (%0); \
29        .set mips0; \
30        .set reorder" \
31        : \
32        : "r" (base), \
33          "i" (op));
34
35static inline void jz_flush_dcache(void)
36{
37    unsigned long start;
38    unsigned long end;
39
40    start = KSEG0;
41    end = start + CONFIG_SYS_DCACHE_SIZE;
42    while (start < end) {
43        cache_unroll(start,Index_Writeback_Inv_D);
44        start += CONFIG_SYS_CACHELINE_SIZE;
45    }
46}
47
48static inline void jz_flush_icache(void)
49{
50    unsigned long start;
51    unsigned long end;
52
53    start = KSEG0;
54    end = start + CONFIG_SYS_ICACHE_SIZE;
55    while(start < end) {
56        cache_unroll(start,Index_Invalidate_I);
57        start += CONFIG_SYS_CACHELINE_SIZE;
58    }
59}
60#endif
61
62/* cpu pipeline flush */
63static inline void jz_sync(void)
64{
65    __asm__ volatile ("sync");
66}
67
68static inline void jz_writeb(u32 address, u8 value)
69{
70    *((volatile u8 *)address) = value;
71}
72
73static inline void jz_writew(u32 address, u16 value)
74{
75    *((volatile u16 *)address) = value;
76}
77
78static inline void jz_writel(u32 address, u32 value)
79{
80    *((volatile u32 *)address) = value;
81}
82
83static inline u8 jz_readb(u32 address)
84{
85    return *((volatile u8 *)address);
86}
87
88static inline u16 jz_readw(u32 address)
89{
90    return *((volatile u16 *)address);
91}
92
93static inline u32 jz_readl(u32 address)
94{
95    return *((volatile u32 *)address);
96}
97
98//----------------------------------------------------------------------
99// Boot ROM Specification
100//
101
102/* NOR Boot config */
103#define JZ4760_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
104#define JZ4760_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
105#define JZ4760_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
106
107/* NAND Boot config */
108#define JZ4760_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
109#define JZ4760_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
110#define JZ4760_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
111#define JZ4760_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
112
113
114//----------------------------------------------------------------------
115// Register Definitions
116//
117/* AHB0 BUS Devices Base */
118#define HARB0_BASE 0xB3000000
119#define EMC_BASE 0xB3010000
120#define DDRC_BASE 0xB3020000
121#define MDMAC_BASE 0xB3030000
122#define LCD_BASE 0xB3050000
123#define TVE_BASE 0xB3050000
124#define SLCD_BASE 0xB3050000
125#define CIM_BASE 0xB3060000
126#define IPU_BASE 0xB3080000
127/* AHB1 BUS Devices Base */
128#define HARB1_BASE 0xB3200000
129#define DMAGP0_BASE 0xB3210000
130#define DMAGP1_BASE 0xB3220000
131#define DMAGP2_BASE 0xB3230000
132#define MC_BASE 0xB3250000
133#define ME_BASE 0xB3260000
134#define DEBLK_BASE 0xB3270000
135#define IDCT_BASE 0xB3280000
136#define CABAC_BASE 0xB3290000
137#define TCSM0_BASE 0xB32B0000
138#define TCSM1_BASE 0xB32C0000
139#define SRAM_BASE 0xB32D0000
140/* AHB2 BUS Devices Base */
141#define HARB2_BASE 0xB3400000
142#define NEMC_BASE 0xB3410000
143#define DMAC_BASE 0xB3420000
144#define UHC_BASE 0xB3430000
145#define UDC_BASE 0xB3440000
146#define BDMAC_BASE 0xB3450000
147#define GPS_BASE 0xB3480000
148#define ETHC_BASE 0xB34B0000
149#define BCH_BASE 0xB34D0000
150/* APB BUS Devices Base */
151#define CPM_BASE 0xB0000000
152#define INTC_BASE 0xB0001000
153#define TCU_BASE 0xB0002000
154#define OST_BASE 0xB0002000
155#define WDT_BASE 0xB0002000
156#define RTC_BASE 0xB0003000
157#define GPIO_BASE 0xB0010000
158#define AIC_BASE 0xB0020000
159#define ICDC_BASE 0xB0020000
160#define MSC0_BASE 0xB0021000
161#define MSC1_BASE 0xB0022000
162#define MSC2_BASE 0xB0023000
163#define UART0_BASE 0xB0030000
164#define UART1_BASE 0xB0031000
165#define UART2_BASE 0xB0032000
166#define UART3_BASE 0xB0033000
167#define SCC_BASE 0xB0040000
168#define SSI0_BASE 0xB0043000
169#define SSI1_BASE 0xB0044000
170#define SSI2_BASE 0xB0045000
171#define I2C0_BASE 0xB0050000
172#define I2C1_BASE 0xB0051000
173#define PS2_BASE 0xB0060000
174#define SADC_BASE 0xB0070000
175#define OWI_BASE 0xB0072000
176#define TSSI_BASE 0xB0073000
177
178/*************************************************************************
179 * INTC (Interrupt Controller)
180 *************************************************************************/
181#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20)
182#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20)
183#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20)
184#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20)
185#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20)
186
187#define REG_INTC_ISR(n) REG32(INTC_ISR((n)))
188#define REG_INTC_IMR(n) REG32(INTC_IMR((n)))
189#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n)))
190#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n)))
191#define REG_INTC_IPR(n) REG32(INTC_IPR((n)))
192
193
194// 1st-level interrupts
195#define IRQ_I2C1 0
196#define IRQ_I2C0 1
197#define IRQ_UART3 2
198#define IRQ_UART2 3
199#define IRQ_UART1 4
200#define IRQ_UART0 5
201#define IRQ_SSI2 6
202#define IRQ_SSI1 7
203#define IRQ_SSI0 8
204#define IRQ_TSSI 9
205#define IRQ_BDMA 10
206#define IRQ_KBC 11
207#define IRQ_GPIO5 12
208#define IRQ_GPIO4 13
209#define IRQ_GPIO3 14
210#define IRQ_GPIO2 15
211#define IRQ_GPIO1 16
212#define IRQ_GPIO0 17
213#define IRQ_SADC 18
214#define IRQ_ETH 19
215#define IRQ_UHC 20
216#define IRQ_OTG 21
217#define IRQ_MDMA 22
218#define IRQ_DMAC1 23
219#define IRQ_DMAC0 24
220#define IRQ_TCU2 25
221#define IRQ_TCU1 26
222#define IRQ_TCU0 27
223#define IRQ_GPS 28
224#define IRQ_IPU 29
225#define IRQ_CIM 30
226#define IRQ_LCD 31
227
228#define IRQ_RTC 32
229#define IRQ_OWI 33
230#define IRQ_AIC 34
231#define IRQ_MSC2 35
232#define IRQ_MSC1 36
233#define IRQ_MSC0 37
234#define IRQ_SCC 38
235#define IRQ_BCH 39
236#define IRQ_PCM 40
237
238// 2nd-level interrupts
239#define IRQ_DMA_0 64 /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */
240#define IRQ_DMA_1 (IRQ_DMA_0 + HALF_DMA_NUM) /* 64 ~ 75 for DMAC0 channel 0 ~ 5 & DMAC1 channel 0 ~ 5 */
241#define IRQ_MDMA_0 (IRQ_DMA_0 + MAX_DMA_NUM) /* 64 ~ 66 for MDMAC channel 0 ~ 2 */
242
243#define IRQ_GPIO_0 96 /* 96 to 287 for GPIO pin 0 to 127 */
244
245#define NUM_INTC 41
246#define NUM_DMA MAX_DMA_NUM /* 12 */
247#define NUM_MDMA MAX_MDMA_NUM /* 3 */
248#define NUM_GPIO MAX_GPIO_NUM /* GPIO NUM: 192, Jz4760 real num GPIO 178 */
249
250/*************************************************************************
251 * RTC
252 *************************************************************************/
253#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
254#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
255#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
256#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
257
258#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
259#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
260#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
261#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
262#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
263#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
264#define RTC_WENR (RTC_BASE + 0x3c) /* Write enable pattern register */
265
266#define REG_RTC_RCR REG32(RTC_RCR)
267#define REG_RTC_RSR REG32(RTC_RSR)
268#define REG_RTC_RSAR REG32(RTC_RSAR)
269#define REG_RTC_RGR REG32(RTC_RGR)
270#define REG_RTC_HCR REG32(RTC_HCR)
271#define REG_RTC_HWFCR REG32(RTC_HWFCR)
272#define REG_RTC_HRCR REG32(RTC_HRCR)
273#define REG_RTC_HWCR REG32(RTC_HWCR)
274#define REG_RTC_HWRSR REG32(RTC_HWRSR)
275#define REG_RTC_HSPR REG32(RTC_HSPR)
276#define REG_RTC_WENR REG32(RTC_WENR)
277
278/* RTC Control Register */
279#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
280#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
281#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
282#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
283#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
284#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
285#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
286
287/* RTC Regulator Register */
288#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
289#define RTC_RGR_ADJC_BIT 16
290#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
291#define RTC_RGR_NC1HZ_BIT 0
292#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
293
294/* Hibernate Control Register */
295#define RTC_HCR_PD (1 << 0) /* Power Down */
296
297/* Hibernate Wakeup Filter Counter Register */
298#define RTC_HWFCR_BIT 5
299#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
300
301/* Hibernate Reset Counter Register */
302#define RTC_HRCR_BIT 5
303#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
304
305/* Hibernate Wakeup Control Register */
306#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
307
308/* Hibernate Wakeup Status Register */
309#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
310#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
311#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
312#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
313
314/* Write enable pattern register */
315#define RTC_WENR_WEN (1 << 31) /* write has been enabled */
316#define RTC_WENR_WENPAT_BIT 0
317#define RTC_WENR_WENPAT_MASK (0xffff << RTC_WENR_WENPAT_BIT) /* The write enable pattern. */
318
319
320/*************************************************************************
321 * CPM (Clock reset and Power control Management)
322 *************************************************************************/
323#define CPM_CPCCR (CPM_BASE+0x00) /* Clock control register */
324#define CPM_CPPCR (CPM_BASE+0x10) /* PLL control register 0 */
325#define CPM_CPPSR (CPM_BASE+0x14) /* PLL switch and status Register */
326#define CPM_CPPCR1 (CPM_BASE+0x30) /* PLL control register 1 */
327#define CPM_CPSPR (CPM_BASE+0x34) /* CPM scratch pad register */
328#define CPM_CPSPPR (CPM_BASE+0x38) /* CPM scratch protected register */
329#define CPM_USBPCR (CPM_BASE+0x3c) /* USB parameter control register */
330#define CPM_USBRDT (CPM_BASE+0x40) /* USB reset detect timer register */
331#define CPM_USBVBFIL (CPM_BASE+0x44) /* USB jitter filter register */
332#define CPM_USBCDR (CPM_BASE+0x50) /* USB OTG PHY clock divider register */
333#define CPM_I2SCDR (CPM_BASE+0x60) /* I2S device clock divider register */
334#define CPM_LPCDR (CPM_BASE+0x64) /* LCD pix clock divider register */
335#define CPM_MSCCDR (CPM_BASE+0x68) /* MSC clock divider register */
336#define CPM_UHCCDR (CPM_BASE+0x6C) /* UHC 48M clock divider register */
337#define CPM_SSICDR (CPM_BASE+0x74) /* SSI clock divider register */
338#define CPM_CIMCDR (CPM_BASE+0x7c) /* CIM MCLK clock divider register */
339#define CPM_GPSCDR (CPM_BASE+0x80) /* GPS clock divider register */
340#define CPM_PCMCDR (CPM_BASE+0x84) /* PCM device clock divider register */
341#define CPM_GPUCDR (CPM_BASE+0x88) /* GPU clock divider register */
342
343#define CPM_LCR (CPM_BASE+0x04)
344#define CPM_PSWCST(n) (CPM_BASE+0x4*(n)+0x90)
345#define CPM_CLKGR0 (CPM_BASE+0x20) /* Clock Gate Register0 */
346#define CPM_CLKGR1 (CPM_BASE+0x28) /* Clock Gate Register1 */
347#define CPM_OPCR (CPM_BASE+0x24) /* Oscillator and Power Control Register */
348
349#define CPM_RSR (CPM_BASE+0x08)
350
351
352#define REG_CPM_CPCCR REG32(CPM_CPCCR)
353#define REG_CPM_CPPCR REG32(CPM_CPPCR)
354#define REG_CPM_CPPSR REG32(CPM_CPPSR)
355#define REG_CPM_CPPCR1 REG32(CPM_CPPCR1)
356#define REG_CPM_CPSPR REG32(CPM_CPSPR)
357#define REG_CPM_CPSPPR REG32(CPM_CPSPPR)
358#define REG_CPM_USBPCR REG32(CPM_USBPCR)
359#define REG_CPM_USBRDT REG32(CPM_USBRDT)
360#define REG_CPM_USBVBFIL REG32(CPM_USBVBFIL)
361#define REG_CPM_USBCDR REG32(CPM_USBCDR)
362#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
363#define REG_CPM_LPCDR REG32(CPM_LPCDR)
364#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
365#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
366#define REG_CPM_SSICDR REG32(CPM_SSICDR)
367#define REG_CPM_CIMCDR REG32(CPM_CIMCDR)
368#define REG_CPM_GPSCDR REG32(CPM_GPSCDR)
369#define REG_CPM_PCMCDR REG32(CPM_PCMCDR)
370#define REG_CPM_GPUCDR REG32(CPM_GPUCDR)
371
372#define REG_CPM_LCR REG32(CPM_LCR)
373#define REG_CPM_CLKGR0 REG32(CPM_CLKGR0)
374#define REG_CPM_CLKGR1 REG32(CPM_CLKGR1)
375#define REG_CPM_OPCR REG32(CPM_OPCR)
376
377#define REG_CPM_RSR REG32(CPM_RSR)
378/* Clock control register */
379#define CPM_CPCCR_ECS (0x01 << 31)
380#define CPM_CPCCR_MEM (0x01 << 30)
381#define CPM_CPCCR_SDIV_BIT 24
382#define CPM_CPCCR_SDIV_MASK (0x0f << CPM_CPCCR_SDIV_BIT)
383#define CPM_CPCCR_CE (0x01 << 22)
384#define CPM_CPCCR_PCS (0x01 << 21)
385#define CPM_CPCCR_H2DIV_BIT 16
386#define CPM_CPCCR_H2DIV_MASK (0x0f << CPM_CPCCR_H2DIV_BIT)
387#define CPM_CPCCR_MDIV_BIT 12
388#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
389#define CPM_CPCCR_PDIV_BIT 8
390#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
391#define CPM_CPCCR_HDIV_BIT 4
392#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
393#define CPM_CPCCR_CDIV_BIT 0
394#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
395
396/* PLL control register 0 */
397#define CPM_CPPCR_PLLM_BIT 24
398#define CPM_CPPCR_PLLM_MASK (0x7f << CPM_CPPCR_PLLM_BIT)
399#define CPM_CPPCR_PLLN_BIT 18
400#define CPM_CPPCR_PLLN_MASK (0x0f << CPM_CPPCR_PLLN_BIT)
401#define CPM_CPPCR_PLLOD_BIT 16
402#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
403#define CPM_CPPCR_LOCK0 (1 << 15)
404#define CPM_CPPCR_ENLOCK (1 << 14)
405#define CPM_CPPCR_PLLS (1 << 10)
406#define CPM_CPPCR_PLLBP (1 << 9)
407#define CPM_CPPCR_PLLEN (1 << 8)
408#define CPM_CPPCR_PLLST_BIT 0
409#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
410
411/* PLL control register 1 */
412#define CPM_CPPCR1_PLL1M_BIT 24
413#define CPM_CPPCR1_PLL1M_MASK (0x7f << CPM_CPPCR1_PLL1M_BIT)
414#define CPM_CPPCR1_PLL1N_BIT 18
415#define CPM_CPPCR1_PLL1N_MASK (0x0f << CPM_CPPCR1_PLL1N_BIT)
416#define CPM_CPPCR1_PLL1OD_BIT 16
417#define CPM_CPPCR1_PLL1OD_MASK (0x03 << CPM_CPPCR1_PLL1OD_BIT)
418#define CPM_CPPCR1_P1SCS (1 << 15)
419#define CPM_CPPCR1_P1SDIV_BIT 9
420#define CPM_CPPCR1_P1SDIV_MASK (0x3f << CPM_CPPCR1_P1SDIV_BIT)
421#define CPM_CPPCR1_PLL1EN (1 << 7)
422#define CPM_CPPCR1_PLL1S (1 << 6)
423#define CPM_CPPCR1_LOCK1 (1 << 2)
424#define CPM_CPPCR1_PLL1OFF (1 << 1)
425#define CPM_CPPCR1_PLL1ON (1 << 0)
426
427/* PLL switch and status Register */
428#define CPM_CPPSR_PLLOFF (1 << 31)
429#define CPM_CPPSR_PLLBP (1 << 30)
430#define CPM_CPPSR_PLLON (1 << 29)
431#define CPM_CPPSR_PS (1 << 28)
432#define CPM_CPPSR_FS (1 << 27)
433#define CPM_CPPSR_CS (1 << 26)
434#define CPM_CPPSR_SM (1 << 2)
435#define CPM_CPPSR_PM (1 << 1)
436#define CPM_CPPSR_FM (1 << 0)
437
438/* CPM scratch protected register */
439#define CPM_CPSPPR_BIT 0
440#define CPM_CPSPPR_MASK (0xffff << CPM_CPSPPR_BIT)
441
442/* USB parameter control register */
443#define CPM_USBPCR_USB_MODE (1 << 31) /* 1: OTG, 0: UDC*/
444#define CPM_USBPCR_AVLD_REG (1 << 30)
445#define CPM_USBPCR_IDPULLUP_MASK_BIT 28
446#define CPM_USBPCR_IDPULLUP_MASK_MASK (0x02 << IDPULLUP_MASK_BIT)
447#define CPM_USBPCR_INCR_MASK (1 << 27)
448#define CPM_USBPCR_CLK12_EN (1 << 26)
449#define CPM_USBPCR_COMMONONN (1 << 25)
450#define CPM_USBPCR_VBUSVLDEXT (1 << 24)
451#define CPM_USBPCR_VBUSVLDEXTSEL (1 << 23)
452#define CPM_USBPCR_POR (1 << 22)
453#define CPM_USBPCR_SIDDQ (1 << 21)
454#define CPM_USBPCR_OTG_DISABLE (1 << 20)
455#define CPM_USBPCR_COMPDISTUNE_BIT 17
456#define CPM_USBPCR_COMPDISTUNE_MASK (0x07 << COMPDISTUNE_BIT)
457#define CPM_USBPCR_OTGTUNE_BIT 14
458#define CPM_USBPCR_OTGTUNE_MASK (0x07 << OTGTUNE_BIT)
459#define CPM_USBPCR_SQRXTUNE_BIT 11
460#define CPM_USBPCR_SQRXTUNE_MASK (0x7x << SQRXTUNE_BIT)
461#define CPM_USBPCR_TXFSLSTUNE_BIT 7
462#define CPM_USBPCR_TXFSLSTUNE_MASK (0x0f << TXFSLSTUNE_BIT)
463#define CPM_USBPCR_TXPREEMPHTUNE (1 << 6)
464#define CPM_USBPCR_TXRISETUNE_BIT 4
465#define CPM_USBPCR_TXRISETUNE_MASK (0x03 << TXRISETUNE_BIT)
466#define CPM_USBPCR_TXVREFTUNE_BIT 0
467#define CPM_USBPCR_TXVREFTUNE_MASK (0x0f << TXVREFTUNE_BIT)
468
469/* USB reset detect timer register */
470#define CPM_USBRDT_VBFIL_LD_EN (1 << 25)
471#define CPM_USBRDT_IDDIG_EN (1 << 24)
472#define CPM_USBRDT_IDDIG_REG (1 << 23)
473#define CPM_USBRDT_USBRDT_BIT 0
474#define CPM_USBRDT_USBRDT_MASK (0x7fffff << CPM_USBRDT_USBRDT_BIT)
475
476/* USB OTG PHY clock divider register */
477#define CPM_USBCDR_UCS (1 << 31)
478#define CPM_USBCDR_UPCS (1 << 30)
479#define CPM_USBCDR_OTGDIV_BIT 0
480#define CPM_USBCDR_OTGDIV_MASK (0x3f << CPM_USBCDR_OTGDIV_BIT)
481
482/* I2S device clock divider register */
483#define CPM_I2SCDR_I2CS (1 << 31)
484#define CPM_I2SCDR_I2PCS (1 << 30)
485#define CPM_I2SCDR_I2SDIV_BIT 0
486#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
487
488/* LCD pix clock divider register */
489#define CPM_LPCDR_LSCS (1 << 31)
490#define CPM_LPCDR_LTCS (1 << 30)
491#define CPM_LPCDR_LPCS (1 << 29)
492#define CPM_LPCDR_PIXDIV_BIT 0
493#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
494
495/* MSC clock divider register */
496#define CPM_MSCCDR_MCS (1 << 31)
497#define CPM_MSCCDR_MSCDIV_BIT 0
498#define CPM_MSCCDR_MSCDIV_MASK (0x3f << CPM_MSCCDR_PIXDIV_BIT)
499
500/* UHC 48M clock divider register */
501#define CPM_UHCCDR_UHPCS (1 << 31)
502#define CPM_UHCCDR_UHCDIV_BIT 0
503#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
504
505/* SSI clock divider register */
506#define CPM_SSICDR_SCS (1 << 31)
507#define CPM_SSICDR_SSIDIV_BIT 0
508#define CPM_SSICDR_SSIDIV_MASK (0x3f << CPM_SSICDR_SSIDIV_BIT)
509
510/* CIM MCLK clock divider register */
511#define CPM_CIMCDR_CIMDIV_BIT 0
512#define CPM_CIMCDR_CIMDIV_MASK (0xff << CPM_CIMCDR_CIMDIV_BIT)
513
514/* GPS clock divider register */
515#define CPM_GPSCDR_GPCS (1 << 31)
516#define CPM_GPSCDR_GPSDIV_BIT 0
517#define CPM_GSPCDR_GPSDIV_MASK (0xf << CPM_GPSCDR_GPSDIV_BIT)
518
519/* PCM device clock divider register */
520#define CPM_PCMCDR_PCMS (1 << 31)
521#define CPM_PCMCDR_PCMPCS (1 << 30)
522#define CPM_PCMCDR_PCMDIV_BIT 0
523#define CPM_PCMCDR_PCMDIV_MASK (0x1ff << CPM_PCMCDR_PCMDIV_BIT)
524
525/* GPU clock divider register */
526#define CPM_GPUCDR_GPCS (1 << 31)
527#define CPM_GPUCDR_GPUDIV_BIT 0
528#define CPM_GPUCDR_GPUDIV_MASK (0x7 << CPM_GPUCDR_GPUDIV_BIT)
529
530/* Low Power Control Register */
531#define CPM_LCR_PD_AHB1 (1 << 30)
532#define CPM_LCR_VBAT_IR (1 << 29)
533#define CPM_LCR_PD_GPS (1 << 28)
534#define CPM_LCR_PD_AHB1S (1 << 26)
535#define CPM_LCR_PD_GPSS (1 << 24)
536#define CPM_LCR_PST_BIT 8
537#define CPM_LCR_PST_MASK (0xfff << CPM_LCR_PST_BIT)
538#define CPM_LCR_DOZE_DUTY_BIT 3
539#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
540#define CPM_LCR_DOZE_ON (1 << 2)
541#define CPM_LCR_LPM_BIT 0
542#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
543  #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
544  #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
545
546/* Clock Gate Register0 */
547#define CPM_CLKGR0_EMC (1 << 31)
548#define CPM_CLKGR0_DDR (1 << 30)
549#define CPM_CLKGR0_IPU (1 << 29)
550#define CPM_CLKGR0_LCD (1 << 28)
551#define CPM_CLKGR0_TVE (1 << 27)
552#define CPM_CLKGR0_CIM (1 << 26)
553#define CPM_CLKGR0_MDMA (1 << 25)
554#define CPM_CLKGR0_UHC (1 << 24)
555#define CPM_CLKGR0_MAC (1 << 23)
556#define CPM_CLKGR0_GPS (1 << 22)
557#define CPM_CLKGR0_DMAC (1 << 21)
558#define CPM_CLKGR0_SSI2 (1 << 20)
559#define CPM_CLKGR0_SSI1 (1 << 19)
560#define CPM_CLKGR0_UART3 (1 << 18)
561#define CPM_CLKGR0_UART2 (1 << 17)
562#define CPM_CLKGR0_UART1 (1 << 16)
563#define CPM_CLKGR0_UART0 (1 << 15)
564#define CPM_CLKGR0_SADC (1 << 14)
565#define CPM_CLKGR0_KBC (1 << 13)
566#define CPM_CLKGR0_MSC2 (1 << 12)
567#define CPM_CLKGR0_MSC1 (1 << 11)
568#define CPM_CLKGR0_OWI (1 << 10)
569#define CPM_CLKGR0_TSSI (1 << 9)
570#define CPM_CLKGR0_AIC (1 << 8)
571#define CPM_CLKGR0_SCC (1 << 7)
572#define CPM_CLKGR0_I2C1 (1 << 6)
573#define CPM_CLKGR0_I2C0 (1 << 5)
574#define CPM_CLKGR0_SSI0 (1 << 4)
575#define CPM_CLKGR0_MSC0 (1 << 3)
576#define CPM_CLKGR0_OTG (1 << 2)
577#define CPM_CLKGR0_BCH (1 << 1)
578#define CPM_CLKGR0_NEMC (1 << 0)
579
580/* Clock Gate Register1 */
581#define CPM_CLKGR1_GPU (1 << 9)
582#define CPM_CLKGR1_PCM (1 << 8)
583#define CPM_CLKGR1_AHB1 (1 << 7)
584#define CPM_CLKGR1_CABAC (1 << 6)
585#define CPM_CLKGR1_SRAM (1 << 5)
586#define CPM_CLKGR1_DCT (1 << 4)
587#define CPM_CLKGR1_ME (1 << 3)
588#define CPM_CLKGR1_DBLK (1 << 2)
589#define CPM_CLKGR1_MC (1 << 1)
590#define CPM_CLKGR1_BDMA (1 << 0)
591
592/* Oscillator and Power Control Register */
593#define CPM_OPCR_O1ST_BIT 8
594#define CPM_OPCR_O1ST_MASK (0xff << CPM_OPCR_O1ST_BIT)
595#define CPM_OPCR_SPENDN (1 << 7)
596#define CPM_OPCR_GPSEN (1 << 6)
597#define CPM_OPCR_SPENDH (1 << 5)
598#define CPM_OPCR_O1SE (1 << 4) /* */
599#define CPM_OPCR_ERCS (1 << 2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
600#define CPM_OPCR_USBM (1 << 0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
601
602
603/* Reset Status Register */
604#define CPM_RSR_P0R (1 << 2)
605#define CPM_RSR_WR (1 << 1)
606#define CPM_RSR_PR (1 << 0)
607
608
609/*************************************************************************
610 * TCU (Timer Counter Unit)
611 *************************************************************************/
612#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
613#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
614#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
615#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
616#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
617#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
618#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
619#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
620#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
621#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
622#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
623#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
624#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
625#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
626#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
627#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
628#define TCU_TDFR1 (TCU_BASE + 0x50)
629#define TCU_TDHR1 (TCU_BASE + 0x54)
630#define TCU_TCNT1 (TCU_BASE + 0x58)
631#define TCU_TCSR1 (TCU_BASE + 0x5C)
632#define TCU_TDFR2 (TCU_BASE + 0x60)
633#define TCU_TDHR2 (TCU_BASE + 0x64)
634#define TCU_TCNT2 (TCU_BASE + 0x68)
635#define TCU_TCSR2 (TCU_BASE + 0x6C)
636#define TCU_TDFR3 (TCU_BASE + 0x70)
637#define TCU_TDHR3 (TCU_BASE + 0x74)
638#define TCU_TCNT3 (TCU_BASE + 0x78)
639#define TCU_TCSR3 (TCU_BASE + 0x7C)
640#define TCU_TDFR4 (TCU_BASE + 0x80)
641#define TCU_TDHR4 (TCU_BASE + 0x84)
642#define TCU_TCNT4 (TCU_BASE + 0x88)
643#define TCU_TCSR4 (TCU_BASE + 0x8C)
644#define TCU_TDFR5 (TCU_BASE + 0x90)
645#define TCU_TDHR5 (TCU_BASE + 0x94)
646#define TCU_TCNT5 (TCU_BASE + 0x98)
647#define TCU_TCSR5 (TCU_BASE + 0x9C)
648#define TCU_TDFR6 (TCU_BASE + 0xA0)
649#define TCU_TDHR6 (TCU_BASE + 0xA4)
650#define TCU_TCNT6 (TCU_BASE + 0xA8)
651#define TCU_TCSR6 (TCU_BASE + 0xAC)
652#define TCU_TDFR7 (TCU_BASE + 0xB0)
653#define TCU_TDHR7 (TCU_BASE + 0xB4)
654#define TCU_TCNT7 (TCU_BASE + 0xB8)
655#define TCU_TCSR7 (TCU_BASE + 0xBC)
656
657#define REG_TCU_TSR REG32(TCU_TSR)
658#define REG_TCU_TSSR REG32(TCU_TSSR)
659#define REG_TCU_TSCR REG32(TCU_TSCR)
660#define REG_TCU_TER REG16(TCU_TER)
661#define REG_TCU_TESR REG16(TCU_TESR)
662#define REG_TCU_TECR REG16(TCU_TECR)
663#define REG_TCU_TFR REG32(TCU_TFR)
664#define REG_TCU_TFSR REG32(TCU_TFSR)
665#define REG_TCU_TFCR REG32(TCU_TFCR)
666#define REG_TCU_TMR REG32(TCU_TMR)
667#define REG_TCU_TMSR REG32(TCU_TMSR)
668#define REG_TCU_TMCR REG32(TCU_TMCR)
669#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
670#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
671#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
672#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
673#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
674#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
675#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
676#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
677#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
678#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
679#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
680#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
681#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
682#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
683#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
684#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
685#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
686#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
687#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
688#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
689#define REG_TCU_TDFR5 REG16(TCU_TDFR5)
690#define REG_TCU_TDHR5 REG16(TCU_TDHR5)
691#define REG_TCU_TCNT5 REG16(TCU_TCNT5)
692#define REG_TCU_TCSR5 REG16(TCU_TCSR5)
693#define REG_TCU_TDFR6 REG16(TCU_TDFR6)
694#define REG_TCU_TDHR6 REG16(TCU_TDHR6)
695#define REG_TCU_TCNT6 REG16(TCU_TCNT6)
696#define REG_TCU_TCSR6 REG16(TCU_TCSR6)
697#define REG_TCU_TDFR7 REG16(TCU_TDFR7)
698#define REG_TCU_TDHR7 REG16(TCU_TDHR7)
699#define REG_TCU_TCNT7 REG16(TCU_TCNT7)
700#define REG_TCU_TCSR7 REG16(TCU_TCSR7)
701
702// n = 0,1,2,3,4,5,6,7
703#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
704#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
705#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
706#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
707
708#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
709#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
710#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
711#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
712
713// Register definitions
714#define TCU_TSTR_REAL2 (1 << 18)
715#define TCU_TSTR_REAL1 (1 << 17)
716#define TCU_TSTR_BUSY2 (1 << 2)
717#define TCU_TSTR_BUSY1 (1 << 1)
718
719#define TCU_TSTSR_REAL2 (1 << 18)
720#define TCU_TSTSR_REAL1 (1 << 17)
721#define TCU_TSTSR_BUSY2 (1 << 2)
722#define TCU_TSTSR_BUSY1 (1 << 1)
723
724#define TCU_TSTCR_REAL2 (1 << 18)
725#define TCU_TSTCR_REAL1 (1 << 17)
726#define TCU_TSTCR_BUSY2 (1 << 2)
727#define TCU_TSTCR_BUSY1 (1 << 1)
728
729#define TCU_TCSR_PWM_SD (1 << 9)
730#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
731#define TCU_TCSR_PWM_EN (1 << 7)
732#define TCU_TCSR_PRESCALE_BIT 3
733#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
734  #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
735  #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
736  #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
737  #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
738  #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
739  #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
740#define TCU_TCSR_EXT_EN (1 << 2)
741#define TCU_TCSR_RTC_EN (1 << 1)
742#define TCU_TCSR_PCK_EN (1 << 0)
743
744#define TCU_TER_OSTEN (1 << 15)
745#define TCU_TER_TCEN7 (1 << 7)
746#define TCU_TER_TCEN6 (1 << 6)
747#define TCU_TER_TCEN5 (1 << 5)
748#define TCU_TER_TCEN4 (1 << 4)
749#define TCU_TER_TCEN3 (1 << 3)
750#define TCU_TER_TCEN2 (1 << 2)
751#define TCU_TER_TCEN1 (1 << 1)
752#define TCU_TER_TCEN0 (1 << 0)
753
754#define TCU_TESR_OSTEN (1 << 15)
755#define TCU_TESR_TCEN7 (1 << 7)
756#define TCU_TESR_TCEN6 (1 << 6)
757#define TCU_TESR_TCST5 (1 << 5)
758#define TCU_TESR_TCST4 (1 << 4)
759#define TCU_TESR_TCST3 (1 << 3)
760#define TCU_TESR_TCST2 (1 << 2)
761#define TCU_TESR_TCST1 (1 << 1)
762#define TCU_TESR_TCST0 (1 << 0)
763
764#define TCU_TECR_OSTEN (1 << 15)
765#define TCU_TECR_TCEN7 (1 << 7)
766#define TCU_TECR_TCEN6 (1 << 6)
767#define TCU_TECR_TCCL5 (1 << 5)
768#define TCU_TECR_TCCL4 (1 << 4)
769#define TCU_TECR_TCCL3 (1 << 3)
770#define TCU_TECR_TCCL2 (1 << 2)
771#define TCU_TECR_TCCL1 (1 << 1)
772#define TCU_TECR_TCCL0 (1 << 0)
773
774#define TCU_TFR_HFLAG7 (1 << 23)
775#define TCU_TFR_HFLAG6 (1 << 22)
776#define TCU_TFR_HFLAG5 (1 << 21)
777#define TCU_TFR_HFLAG4 (1 << 20)
778#define TCU_TFR_HFLAG3 (1 << 19)
779#define TCU_TFR_HFLAG2 (1 << 18)
780#define TCU_TFR_HFLAG1 (1 << 17)
781#define TCU_TFR_HFLAG0 (1 << 16)
782#define TCU_TFR_FLAGOST (1 << 15)
783#define TCU_TFR_FFLAG7 (1 << 7)
784#define TCU_TFR_FFLAG6 (1 << 6)
785#define TCU_TFR_FFLAG5 (1 << 5)
786#define TCU_TFR_FFLAG4 (1 << 4)
787#define TCU_TFR_FFLAG3 (1 << 3)
788#define TCU_TFR_FFLAG2 (1 << 2)
789#define TCU_TFR_FFLAG1 (1 << 1)
790#define TCU_TFR_FFLAG0 (1 << 0)
791
792#define TCU_TFSR_HFLAG7 (1 << 23)
793#define TCU_TFSR_HFLAG6 (1 << 22)
794#define TCU_TFSR_HFLAG5 (1 << 21)
795#define TCU_TFSR_HFLAG4 (1 << 20)
796#define TCU_TFSR_HFLAG3 (1 << 19)
797#define TCU_TFSR_HFLAG2 (1 << 18)
798#define TCU_TFSR_HFLAG1 (1 << 17)
799#define TCU_TFSR_HFLAG0 (1 << 16)
800#define TCU_TFSR_FLAGOST (1 << 15)
801#define TCU_TFSR_FFLAG7 (1 << 7)
802#define TCU_TFSR_FFLAG6 (1 << 6)
803#define TCU_TFSR_FFLAG5 (1 << 5)
804#define TCU_TFSR_FFLAG4 (1 << 4)
805#define TCU_TFSR_FFLAG3 (1 << 3)
806#define TCU_TFSR_FFLAG2 (1 << 2)
807#define TCU_TFSR_FFLAG1 (1 << 1)
808#define TCU_TFSR_FFLAG0 (1 << 0)
809
810#define TCU_TFCR_HFLAG7 (1 << 23)
811#define TCU_TFCR_HFLAG6 (1 << 22)
812#define TCU_TFCR_HFLAG5 (1 << 21)
813#define TCU_TFCR_HFLAG4 (1 << 20)
814#define TCU_TFCR_HFLAG3 (1 << 19)
815#define TCU_TFCR_HFLAG2 (1 << 18)
816#define TCU_TFCR_HFLAG1 (1 << 17)
817#define TCU_TFCR_HFLAG0 (1 << 16)
818#define TCU_TFCR_FLAGOST (1 << 15)
819#define TCU_TFCR_FFLAG7 (1 << 7)
820#define TCU_TFCR_FFLAG6 (1 << 6)
821#define TCU_TFCR_FFLAG5 (1 << 5)
822#define TCU_TFCR_FFLAG4 (1 << 4)
823#define TCU_TFCR_FFLAG3 (1 << 3)
824#define TCU_TFCR_FFLAG2 (1 << 2)
825#define TCU_TFCR_FFLAG1 (1 << 1)
826#define TCU_TFCR_FFLAG0 (1 << 0)
827
828#define TCU_TMR_HMASK7 (1 << 23)
829#define TCU_TMR_HMASK6 (1 << 22)
830#define TCU_TMR_HMASK5 (1 << 21)
831#define TCU_TMR_HMASK4 (1 << 20)
832#define TCU_TMR_HMASK3 (1 << 19)
833#define TCU_TMR_HMASK2 (1 << 18)
834#define TCU_TMR_HMASK1 (1 << 17)
835#define TCU_TMR_HMASK0 (1 << 16)
836#define TCU_TMR_MASKOST (1 << 15)
837#define TCU_TMR_FMASK7 (1 << 7)
838#define TCU_TMR_FMASK6 (1 << 6)
839#define TCU_TMR_FMASK5 (1 << 5)
840#define TCU_TMR_FMASK4 (1 << 4)
841#define TCU_TMR_FMASK3 (1 << 3)
842#define TCU_TMR_FMASK2 (1 << 2)
843#define TCU_TMR_FMASK1 (1 << 1)
844#define TCU_TMR_FMASK0 (1 << 0)
845
846#define TCU_TMSR_HMST7 (1 << 23)
847#define TCU_TMSR_HMST6 (1 << 22)
848#define TCU_TMSR_HMST5 (1 << 21)
849#define TCU_TMSR_HMST4 (1 << 20)
850#define TCU_TMSR_HMST3 (1 << 19)
851#define TCU_TMSR_HMST2 (1 << 18)
852#define TCU_TMSR_HMST1 (1 << 17)
853#define TCU_TMSR_HMST0 (1 << 16)
854#define TCU_TMSR_MSTOST (1 << 15)
855#define TCU_TMSR_FMST7 (1 << 7)
856#define TCU_TMSR_FMST6 (1 << 6)
857#define TCU_TMSR_FMST5 (1 << 5)
858#define TCU_TMSR_FMST4 (1 << 4)
859#define TCU_TMSR_FMST3 (1 << 3)
860#define TCU_TMSR_FMST2 (1 << 2)
861#define TCU_TMSR_FMST1 (1 << 1)
862#define TCU_TMSR_FMST0 (1 << 0)
863
864#define TCU_TMCR_HMCL7 (1 << 23)
865#define TCU_TMCR_HMCL6 (1 << 22)
866#define TCU_TMCR_HMCL5 (1 << 21)
867#define TCU_TMCR_HMCL4 (1 << 20)
868#define TCU_TMCR_HMCL3 (1 << 19)
869#define TCU_TMCR_HMCL2 (1 << 18)
870#define TCU_TMCR_HMCL1 (1 << 17)
871#define TCU_TMCR_HMCL0 (1 << 16)
872#define TCU_TMCR_MCLOST (1 << 15)
873#define TCU_TMCR_FMCL7 (1 << 7)
874#define TCU_TMCR_FMCL6 (1 << 6)
875#define TCU_TMCR_FMCL5 (1 << 5)
876#define TCU_TMCR_FMCL4 (1 << 4)
877#define TCU_TMCR_FMCL3 (1 << 3)
878#define TCU_TMCR_FMCL2 (1 << 2)
879#define TCU_TMCR_FMCL1 (1 << 1)
880#define TCU_TMCR_FMCL0 (1 << 0)
881
882#define TCU_TSR_WDTS (1 << 16)
883#define TCU_TSR_OST (1 << 15)
884#define TCU_TSR_STOP7 (1 << 7)
885#define TCU_TSR_STOP6 (1 << 6)
886#define TCU_TSR_STOP5 (1 << 5)
887#define TCU_TSR_STOP4 (1 << 4)
888#define TCU_TSR_STOP3 (1 << 3)
889#define TCU_TSR_STOP2 (1 << 2)
890#define TCU_TSR_STOP1 (1 << 1)
891#define TCU_TSR_STOP0 (1 << 0)
892
893#define TCU_TSSR_WDTSC (1 << 16)
894#define TCU_TSSR_OST (1 << 15)
895#define TCU_TSSR_STPS7 (1 << 7)
896#define TCU_TSSR_STPS6 (1 << 6)
897#define TCU_TSSR_STPS5 (1 << 5)
898#define TCU_TSSR_STPS4 (1 << 4)
899#define TCU_TSSR_STPS3 (1 << 3)
900#define TCU_TSSR_STPS2 (1 << 2)
901#define TCU_TSSR_STPS1 (1 << 1)
902#define TCU_TSSR_STPS0 (1 << 0)
903
904#define TCU_TSCR_WDTSC (1 << 16)
905#define TCU_TSCR_OST (1 << 15)
906#define TCU_TSCR_STPS7 (1 << 7)
907#define TCU_TSCR_STPS6 (1 << 6)
908#define TCU_TSCR_STPS5 (1 << 5)
909#define TCU_TSCR_STPS4 (1 << 4)
910#define TCU_TSCR_STPS3 (1 << 3)
911#define TCU_TSCR_STPS2 (1 << 2)
912#define TCU_TSCR_STPS1 (1 << 1)
913#define TCU_TSCR_STPS0 (1 << 0)
914
915
916/*************************************************************************
917 * WDT (WatchDog Timer)
918 *************************************************************************/
919#define WDT_TDR (WDT_BASE + 0x00)
920#define WDT_TCER (WDT_BASE + 0x04)
921#define WDT_TCNT (WDT_BASE + 0x08)
922#define WDT_TCSR (WDT_BASE + 0x0C)
923
924#define REG_WDT_TDR REG16(WDT_TDR)
925#define REG_WDT_TCER REG8(WDT_TCER)
926#define REG_WDT_TCNT REG16(WDT_TCNT)
927#define REG_WDT_TCSR REG16(WDT_TCSR)
928
929// Register definition
930#define WDT_TCSR_PRESCALE_BIT 3
931#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
932  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
933  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
934  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
935  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
936  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
937  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
938#define WDT_TCSR_EXT_EN (1 << 2)
939#define WDT_TCSR_RTC_EN (1 << 1)
940#define WDT_TCSR_PCK_EN (1 << 0)
941
942#define WDT_TCER_TCEN (1 << 0)
943
944/*************************************************************************
945 * OST (Operation System Timer)
946 *************************************************************************/
947#define OST_DR (OST_BASE + 0xE0)
948#define OST_CNT (OST_BASE + 0xE8)
949#define OST_CSR (OST_BASE + 0xEC)
950
951#define REG_OST_DR REG32(OST_DR)
952#define REG_OST_CNT REG32(OST_CNT)
953#define REG_OST_CSR REG16(OST_CSR)
954
955#define OST_CSR_CNT_MD (1 << 15)
956#define OST_CSR_PWM_SD (1 << 9)
957#define OST_CSR_PRESCALE_BIT 3
958#define OST_CSR_PRESCALE_MASK (0x7 << OST_CSR_PRESCALE_BIT)
959  #define OST_CSR_PRESCALE1 (0x0 << OST_CSR_PRESCALE_BIT)
960  #define OST_CSR_PRESCALE4 (0x1 << OST_CSR_PRESCALE_BIT)
961  #define OST_CSR_PRESCALE16 (0x2 << OST_CSR_PRESCALE_BIT)
962  #define OST_CSR_PRESCALE64 (0x3 << OST_CSR_PRESCALE_BIT)
963  #define OST_CSR_PRESCALE256 (0x4 << OST_CSR_PRESCALE_BIT)
964  #define OST_CSR_PRESCALE1024 (0x5 << OST_CSR_PRESCALE_BIT)
965#define OST_CSR_EXT_EN (1 << 2)
966#define OST_CSR_RTC_EN (1 << 1)
967#define OST_CSR_PCK_EN (1 << 0)
968
969/*************************************************************************
970 * MDMAC (MEM Copy DMA Controller)
971 *************************************************************************/
972
973#define MAX_MDMA_NUM 3 /* max 3 channels */
974
975/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
976
977#define MDMAC_DSAR(n) (MDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
978#define MDMAC_DTAR(n) (MDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
979#define MDMAC_DTCR(n) (MDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
980#define MDMAC_DRSR(n) (MDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
981#define MDMAC_DCCSR(n) (MDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
982#define MDMAC_DCMD(n) (MDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
983#define MDMAC_DDA(n) (MDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
984#define MDMAC_DSD(n) (MDMAC_BASE + (0xc0 + (n) * 0x04)) /* DMA Stride Address */
985
986#define MDMAC_DMACR (MDMAC_BASE + 0x0300) /* DMA control register */
987#define MDMAC_DMAIPR (MDMAC_BASE + 0x0304) /* DMA interrupt pending */
988#define MDMAC_DMADBR (MDMAC_BASE + 0x0308) /* DMA doorbell */
989#define MDMAC_DMADBSR (MDMAC_BASE + 0x030C) /* DMA doorbell set */
990#define MDMAC_DMACKE (MDMAC_BASE + 0x0310)
991
992#define REG_MDMAC_DSAR(n) REG32(MDMAC_DSAR((n)))
993#define REG_MDMAC_DTAR(n) REG32(MDMAC_DTAR((n)))
994#define REG_MDMAC_DTCR(n) REG32(MDMAC_DTCR((n)))
995#define REG_MDMAC_DRSR(n) REG32(MDMAC_DRSR((n)))
996#define REG_MDMAC_DCCSR(n) REG32(MDMAC_DCCSR((n)))
997#define REG_MDMAC_DCMD(n) REG32(MDMAC_DCMD((n)))
998#define REG_MDMAC_DDA(n) REG32(MDMAC_DDA((n)))
999#define REG_MDMAC_DSD(n) REG32(MDMAC_DSD(n))
1000#define REG_MDMAC_DMACR REG32(MDMAC_DMACR)
1001#define REG_MDMAC_DMAIPR REG32(MDMAC_DMAIPR)
1002#define REG_MDMAC_DMADBR REG32(MDMAC_DMADBR)
1003#define REG_MDMAC_DMADBSR REG32(MDMAC_DMADBSR)
1004#define REG_MDMAC_DMACKE REG32(MDMAC_DMACKE)
1005
1006
1007/***************************************************************************
1008 * BCH & NAND DMAC
1009 ***************************************************************************/
1010/* n is the DMA channel index (0 - 2) */
1011#define BDMAC_DSAR(n) (BDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
1012#define BDMAC_DTAR(n) (BDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
1013#define BDMAC_DTCR(n) (BDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
1014#define BDMAC_DRSR(n) (BDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
1015#define BDMAC_DCCSR(n) (BDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
1016#define BDMAC_DCMD(n) (BDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
1017#define BDMAC_DDA(n) (BDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
1018#define BDMAC_DSD(n) (BDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */
1019#define BDMAC_DNT(n) (BDMAC_BASE + (0xc0 + (n) * 0x04)) /* NAND Detect Timer */
1020
1021#define BDMAC_DMACR (BDMAC_BASE + 0x0300) /* DMA control register */
1022#define BDMAC_DMAIPR (BDMAC_BASE + 0x0304) /* DMA interrupt pending */
1023#define BDMAC_DMADBR (BDMAC_BASE + 0x0308) /* DMA doorbell */
1024#define BDMAC_DMADBSR (BDMAC_BASE + 0x030C) /* DMA doorbell set */
1025#define BDMAC_DMACKE (BDMAC_BASE + 0x0310)
1026
1027#define REG_BDMAC_DSAR(n) REG32(BDMAC_DSAR((n)))
1028#define REG_BDMAC_DTAR(n) REG32(BDMAC_DTAR((n)))
1029#define REG_BDMAC_DTCR(n) REG32(BDMAC_DTCR((n)))
1030#define REG_BDMAC_DRSR(n) REG32(BDMAC_DRSR((n)))
1031#define REG_BDMAC_DCCSR(n) REG32(BDMAC_DCCSR((n)))
1032#define REG_BDMAC_DCMD(n) REG32(BDMAC_DCMD((n)))
1033#define REG_BDMAC_DDA(n) REG32(BDMAC_DDA((n)))
1034#define REG_BDMAC_DSD(n) REG32(BDMAC_DSD(n))
1035#define REG_BDMAC_DNT(n) REG32(BDMAC_DNT(n))
1036
1037#define REG_BDMAC_DMACR REG32(BDMAC_DMACR)
1038#define REG_BDMAC_DMAIPR REG32(BDMAC_DMAIPR)
1039#define REG_BDMAC_DMADBR REG32(BDMAC_DMADBR)
1040#define REG_BDMAC_DMADBSR REG32(BDMAC_DMADBSR)
1041#define REG_BDMAC_DMACKE REG32(BDMAC_DMACKE)
1042
1043// BDMA request source register
1044#define BDMAC_DRSR_RS_BIT 0
1045  #define BDMAC_DRSR_RS_MASK (0x3f << DMAC_DRSR_RS_BIT)
1046  #define BDMAC_DRSR_RS_NAND (1 << DMAC_DRSR_RS_BIT)
1047  #define BDMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT)
1048  #define BDMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT)
1049  #define BDMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
1050  #define BDMAC_DRSR_RS_EXT (12 << DMAC_DRSR_RS_BIT)
1051
1052// BDMA channel control/status register
1053#define BDMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
1054#define BDMAC_DCCSR_DES8 (1 << 30) /* Descriptor 8 Word */
1055#define BDMAC_DCCSR_DES4 (0 << 30) /* Descriptor 4 Word */
1056#define BDMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
1057  #define BDMAC_DCCSR_CDOA_MASK (0xff << BDMACC_DCCSR_CDOA_BIT)
1058#define BDMAC_DCCSR_BERR (1 << 7) /* BCH error within this transfer, Only for channel 0 */
1059#define BDMAC_DCCSR_AR (1 << 4) /* address error */
1060#define BDMAC_DCCSR_TT (1 << 3) /* transfer terminated */
1061#define BDMAC_DCCSR_HLT (1 << 2) /* DMA halted */
1062#define BDMAC_DCCSR_EN (1 << 0) /* channel enable bit */
1063
1064// BDMA channel command register
1065#define BDMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */
1066#define BDMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */
1067#define BDMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */
1068#define BDMAC_DCMD_EACKM_READ (0 << 30) /* External DACK Output Mode Select, output in read cycle */
1069#define BDMAC_DCMD_ERDM_BIT 28 /* External DREQ Detection Mode Select */
1070  #define BDMAC_DCMD_ERDM_MASK (0x03 << BDMAC_DCMD_ERDM_BIT)
1071  #define BDMAC_DCMD_ERDM_LOW (0 << BDMAC_DCMD_ERDM_BIT)
1072  #define BDMAC_DCMD_ERDM_FALL (1 << BDMAC_DCMD_ERDM_BIT)
1073  #define BDMAC_DCMD_ERDM_HIGH (2 << BDMAC_DCMD_ERDM_BIT)
1074  #define BDMAC_DCMD_ERDM_RISE (3 << BDMAC_DCMD_ERDM_BIT)
1075#define BDMAC_DCMD_BLAST (1 << 25) /* BCH last */
1076#define BDMAC_DCMD_SAI (1 << 23) /* source address increment */
1077#define BDMAC_DCMD_DAI (1 << 22) /* dest address increment */
1078#define BDMAC_DCMD_SWDH_BIT 14 /* source port width */
1079  #define BDMAC_DCMD_SWDH_MASK (0x03 << BDMAC_DCMD_SWDH_BIT)
1080  #define BDMAC_DCMD_SWDH_32 (0 << BDMAC_DCMD_SWDH_BIT)
1081  #define BDMAC_DCMD_SWDH_8 (1 << BDMAC_DCMD_SWDH_BIT)
1082  #define BDMAC_DCMD_SWDH_16 (2 << BDMAC_DCMD_SWDH_BIT)
1083#define BDMAC_DCMD_DWDH_BIT 12 /* dest port width */
1084  #define BDMAC_DCMD_DWDH_MASK (0x03 << BDMAC_DCMD_DWDH_BIT)
1085  #define BDMAC_DCMD_DWDH_32 (0 << BDMAC_DCMD_DWDH_BIT)
1086  #define BDMAC_DCMD_DWDH_8 (1 << BDMAC_DCMD_DWDH_BIT)
1087  #define BDMAC_DCMD_DWDH_16 (2 << BDMAC_DCMD_DWDH_BIT)
1088#define BDMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
1089  #define BDMAC_DCMD_DS_MASK (0x07 << BDMAC_DCMD_DS_BIT)
1090  #define BDMAC_DCMD_DS_32BIT (0 << BDMAC_DCMD_DS_BIT)
1091  #define BDMAC_DCMD_DS_8BIT (1 << BDMAC_DCMD_DS_BIT)
1092  #define BDMAC_DCMD_DS_16BIT (2 << BDMAC_DCMD_DS_BIT)
1093  #define BDMAC_DCMD_DS_16BYTE (3 << BDMAC_DCMD_DS_BIT)
1094  #define BDMAC_DCMD_DS_32BYTE (4 << BDMAC_DCMD_DS_BIT)
1095  #define BDMAC_DCMD_DS_64BYTE (5 << BDMAC_DCMD_DS_BIT)
1096#define BDMAC_DCMD_NRD (1 << 7) /* NAND direct read */
1097#define BDMAC_DCMD_NWR (1 << 6) /* NAND direct write */
1098#define BDMAC_DCMD_NAC (1 << 5) /* NAND AL/CL enable */
1099#define BDMAC_DCMD_STDE (1 << 2) /* Stride Disable/Enable */
1100#define BDMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
1101#define BDMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
1102
1103// BDMA descriptor address register
1104#define BDMAC_DDA_BASE_BIT 12 /* descriptor base address */
1105  #define BDMAC_DDA_BASE_MASK (0x0fffff << BDMAC_DDA_BASE_BIT)
1106#define BDMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
1107  #define BDMAC_DDA_OFFSET_MASK (0x0ff << BDMAC_DDA_OFFSET_BIT)
1108
1109// BDMA stride address register
1110#define BDMAC_DSD_TSD_BIT 16 /* target stride address */
1111  #define BDMAC_DSD_TSD_MASK (0xffff << BDMAC_DSD_TSD_BIT)
1112#define BDMAC_DSD_SSD_BIT 0 /* source stride address */
1113  #define BDMAC_DSD_SSD_MASK (0xffff << BDMAC_DSD_SSD_BIT)
1114
1115// BDMA NAND Detect timer register
1116#define BDMAC_NDTCTIMER_EN (1 << 15) /* enable detect timer */
1117#define BDMAC_TAILCNT_BIT 16
1118
1119// BDMA control register
1120#define BDMAC_DMACR_PR_BIT 8 /* channel priority mode */
1121  #define BDMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
1122  #define BDMAC_DMACR_PR_01_2 (0 << BDMAC_DMACR_PR_BIT)
1123  #define BDMAC_DMACR_PR_12_0 (1 << BDMAC_DMACR_PR_BIT)
1124  #define BDMAC_DMACR_PR_20_1 (2 << BDMAC_DMACR_PR_BIT)
1125  #define BDMAC_DMACR_PR_012 (3 << BDMAC_DMACR_PR_BIT)
1126#define BDMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
1127#define BDMAC_DMACR_AR (1 << 2) /* address error flag */
1128#define BDMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
1129
1130// BDMA interrupt pending register
1131#define BDMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
1132#define BDMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
1133#define BDMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
1134
1135// BDMA doorbell register
1136#define BDMAC_DMADBR_DB2 (1 << 2) /* doorbell for channel 2 */
1137#define BDMAC_DMADBR_DB1 (1 << 1) /* doorbell for channel 1 */
1138#define BDMAC_DMADBR_DB0 (1 << 0) /* doorbell for channel 0 */
1139
1140// BDMA doorbell set register
1141#define BDMAC_DMADBSR_DBS2 (1 << 2) /* enable doorbell for channel 2 */
1142#define BDMAC_DMADBSR_DBS1 (1 << 1) /* enable doorbell for channel 1 */
1143#define BDMAC_DMADBSR_DBS0 (1 << 0) /* enable doorbell for channel 0 */
1144
1145/* n is the DMA channel index (0 - 2) */
1146
1147#define __bdmac_test_halt_error ( REG_BDMAC_DMACR & BDMAC_DMACR_HLT )
1148#define __bdmac_test_addr_error ( REG_BDMAC_DMACR & BDMAC_DMACR_AR )
1149
1150#define __bdmac_channel_enable_clk(n) \
1151    REG_BDMAC_DMACKE |= 1 << (n);
1152
1153#define __bdmac_enable_descriptor(n) \
1154  ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_NDES )
1155#define __bdmac_disable_descriptor(n) \
1156  ( REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_NDES )
1157
1158#define __bdmac_enable_channel(n) \
1159do { \
1160    REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_EN; \
1161} while (0)
1162#define __bdmac_disable_channel(n) \
1163do { \
1164    REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_EN; \
1165} while (0)
1166
1167#define __bdmac_channel_enable_irq(n) \
1168  ( REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_TIE )
1169#define __bdmac_channel_disable_irq(n) \
1170  ( REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_TIE )
1171
1172#define __bdmac_channel_transmit_halt_detected(n) \
1173  ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_HLT )
1174#define __bdmac_channel_transmit_end_detected(n) \
1175  ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_TT )
1176#define __bdmac_channel_address_error_detected(n) \
1177  ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_AR )
1178#define __bdmac_channel_count_terminated_detected(n) \
1179  ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_CT )
1180#define __bdmac_channel_descriptor_invalid_detected(n) \
1181  ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_INV )
1182#define __bdmac_BCH_error_detected(n) \
1183  ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_BERR )
1184
1185#define __bdmac_channel_clear_transmit_halt(n) \
1186    do { \
1187        /* clear both channel halt error and globle halt error */ \
1188        REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_HLT; \
1189        REG_BDMAC_DMACR &= ~BDMAC_DMACR_HLT; \
1190    } while (0)
1191#define __bdmac_channel_clear_transmit_end(n) \
1192  ( REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_TT )
1193#define __bdmac_channel_clear_address_error(n) \
1194    do { \
1195        REG_BDMAC_DDA(n) = 0; /* clear descriptor address register */ \
1196        REG_BDMAC_DSAR(n) = 0; /* clear source address register */ \
1197        REG_BDMAC_DTAR(n) = 0; /* clear target address register */ \
1198        /* clear both channel addr error and globle address error */ \
1199        REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_AR; \
1200        REG_BDMAC_DMACR &= ~BDMAC_DMACR_AR; \
1201    } while (0)
1202#define __bdmac_channel_clear_count_terminated(n) \
1203  ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_CT )
1204#define __bdmac_channel_clear_descriptor_invalid(n) \
1205  ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_INV )
1206
1207#define __bdmac_channel_set_transfer_unit_32bit(n) \
1208do { \
1209    REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
1210    REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BIT; \
1211} while (0)
1212
1213#define __bdmac_channel_set_transfer_unit_16bit(n) \
1214do { \
1215    REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
1216    REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BIT; \
1217} while (0)
1218
1219#define __bdmac_channel_set_transfer_unit_8bit(n) \
1220do { \
1221    REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
1222    REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_8BIT; \
1223} while (0)
1224
1225#define __bdmac_channel_set_transfer_unit_16byte(n) \
1226do { \
1227    REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
1228    REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BYTE; \
1229} while (0)
1230
1231#define __bdmac_channel_set_transfer_unit_32byte(n) \
1232do { \
1233    REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \
1234    REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BYTE; \
1235} while (0)
1236
1237/* w=8,16,32 */
1238#define __bdmac_channel_set_dest_port_width(n,w) \
1239do { \
1240    REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DWDH_MASK; \
1241    REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DWDH_##w; \
1242} while (0)
1243
1244/* w=8,16,32 */
1245#define __bdmac_channel_set_src_port_width(n,w) \
1246do { \
1247    REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SWDH_MASK; \
1248    REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SWDH_##w; \
1249} while (0)
1250
1251#define __bdmac_channel_dest_addr_fixed(n) \
1252    (REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DAI)
1253#define __bdmac_channel_dest_addr_increment(n) \
1254    (REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DAI)
1255
1256#define __bdmac_channel_src_addr_fixed(n) \
1257    (REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SAI)
1258#define __bdmac_channel_src_addr_increment(n) \
1259    (REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SAI)
1260
1261#define __bdmac_channel_set_doorbell(n) \
1262    (REG_BDMAC_DMADBSR = (1 << (n)))
1263
1264#define __bdmac_channel_irq_detected(n) (REG_BDMAC_DMAIPR & (1 << (n)))
1265#define __bdmac_channel_ack_irq(n) (REG_BDMAC_DMAIPR &= ~(1 <<(n)))
1266
1267/*************************************************************************
1268 * DMAC (DMA Controller)
1269 *************************************************************************/
1270
1271#define MAX_DMA_NUM 12 /* max 12 channels */
1272#define HALF_DMA_NUM 6 /* the number of one dma controller's channels */
1273
1274/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
1275
1276#define DMAC_DSAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x00 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA source address */
1277#define DMAC_DTAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x04 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA target address */
1278#define DMAC_DTCR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x08 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA transfer count */
1279#define DMAC_DRSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x0c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA request source */
1280#define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */
1281#define DMAC_DCMD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */
1282#define DMAC_DDA(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */
1283#define DMAC_DSD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0xc0 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */
1284
1285#define DMAC_DMACR(m) (DMAC_BASE + 0x0300 + 0x100 * (m)) /* DMA control register */
1286#define DMAC_DMAIPR(m) (DMAC_BASE + 0x0304 + 0x100 * (m)) /* DMA interrupt pending */
1287#define DMAC_DMADBR(m) (DMAC_BASE + 0x0308 + 0x100 * (m)) /* DMA doorbell */
1288#define DMAC_DMADBSR(m) (DMAC_BASE + 0x030C + 0x100 * (m)) /* DMA doorbell set */
1289#define DMAC_DMACKE(m) (DMAC_BASE + 0x0310 + 0x100 * (m))
1290
1291
1292#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
1293#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
1294#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
1295#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
1296#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
1297#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
1298#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
1299#define REG_DMAC_DSD(n) REG32(DMAC_DSD(n))
1300#define REG_DMAC_DMACR(m) REG32(DMAC_DMACR(m))
1301#define REG_DMAC_DMAIPR(m) REG32(DMAC_DMAIPR(m))
1302#define REG_DMAC_DMADBR(m) REG32(DMAC_DMADBR(m))
1303#define REG_DMAC_DMADBSR(m) REG32(DMAC_DMADBSR(m))
1304#define REG_DMAC_DMACKE(m) REG32(DMAC_DMACKE(m))
1305
1306// DMA request source register
1307#define DMAC_DRSR_RS_BIT 0
1308#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
1309  #define DMAC_DRSR_RS_EXT (0 << DMAC_DRSR_RS_BIT)
1310  #define DMAC_DRSR_RS_NAND (1 << DMAC_DRSR_RS_BIT)
1311  #define DMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT)
1312  #define DMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT)
1313  #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
1314  #define DMAC_DRSR_RS_TSSIIN (9 << DMAC_DRSR_RS_BIT)
1315  #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT)
1316  #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT)
1317  #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT)
1318  #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT)
1319  #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT)
1320  #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT)
1321  #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
1322  #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
1323  #define DMAC_DRSR_RS_SSI0OUT (22 << DMAC_DRSR_RS_BIT)
1324  #define DMAC_DRSR_RS_SSI0IN (23 << DMAC_DRSR_RS_BIT)
1325  #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
1326  #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
1327  #define DMAC_DRSR_RS_MSC0OUT (26 << DMAC_DRSR_RS_BIT)
1328  #define DMAC_DRSR_RS_MSC0IN (27 << DMAC_DRSR_RS_BIT)
1329  #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
1330  #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
1331  #define DMAC_DRSR_RS_MSC1OUT (30 << DMAC_DRSR_RS_BIT)
1332  #define DMAC_DRSR_RS_MSC1IN (31 << DMAC_DRSR_RS_BIT)
1333  #define DMAC_DRSR_RS_SSI1OUT (32 << DMAC_DRSR_RS_BIT)
1334  #define DMAC_DRSR_RS_SSI1IN (33 << DMAC_DRSR_RS_BIT)
1335  #define DMAC_DRSR_RS_PMOUT (34 << DMAC_DRSR_RS_BIT)
1336  #define DMAC_DRSR_RS_PMIN (35 << DMAC_DRSR_RS_BIT)
1337
1338// DMA channel control/status register
1339#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
1340#define DMAC_DCCSR_DES8 (1 << 30) /* Descriptor 8 Word */
1341#define DMAC_DCCSR_DES4 (0 << 30) /* Descriptor 4 Word */
1342#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
1343#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
1344#define DMAC_DCCSR_BERR (1 << 7) /* BCH error within this transfer, Only for channel 0 */
1345#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
1346#define DMAC_DCCSR_AR (1 << 4) /* address error */
1347#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
1348#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
1349#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
1350#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
1351
1352// DMA channel command register
1353#define DMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */
1354#define DMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */
1355#define DMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */
1356#define DMAC_DCMD_EACKM_READ (0 << 30) /* External DACK Output Mode Select, output in read cycle */
1357#define DMAC_DCMD_ERDM_BIT 28 /* External DREQ Detection Mode Select */
1358#define DMAC_DCMD_ERDM_MASK (0x03 << DMAC_DCMD_ERDM_BIT)
1359  #define DMAC_DCMD_ERDM_LOW (0 << DMAC_DCMD_ERDM_BIT)
1360  #define DMAC_DCMD_ERDM_FALL (1 << DMAC_DCMD_ERDM_BIT)
1361  #define DMAC_DCMD_ERDM_HIGH (2 << DMAC_DCMD_ERDM_BIT)
1362  #define DMAC_DCMD_ERDM_RISE (3 << DMAC_DCMD_ERDM_BIT)
1363#define DMAC_DCMD_BLAST (1 << 25) /* BCH last */
1364#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
1365#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
1366#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
1367#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
1368  #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
1369  #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
1370  #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
1371  #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
1372  #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
1373  #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
1374  #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
1375  #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
1376  #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
1377  #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
1378  #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
1379  #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
1380  #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
1381  #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
1382  #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
1383  #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
1384#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
1385#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
1386  #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
1387  #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
1388  #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
1389#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
1390#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
1391  #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
1392  #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
1393  #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
1394#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
1395#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
1396  #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
1397  #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
1398  #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
1399  #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
1400  #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
1401  #define DMAC_DCMD_DS_64BYTE (5 << DMAC_DCMD_DS_BIT)
1402#define DMAC_DCMD_STDE (1 << 5) /* Stride Disable/Enable */
1403#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
1404#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
1405#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
1406#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
1407#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
1408
1409// DMA descriptor address register
1410#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
1411#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
1412#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
1413#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
1414
1415// DMA stride address register
1416#define DMAC_DSD_TSD_BIT 16 /* target stride address */
1417#define DMAC_DSD_TSD_MASK (0xffff << DMAC_DSD_TSD_BIT)
1418#define DMAC_DSD_SSD_BIT 0 /* source stride address */
1419#define DMAC_DSD_SSD_MASK (0xffff << DMAC_DSD_SSD_BIT)
1420
1421// DMA control register
1422#define DMAC_DMACR_FMSC (1 << 31) /* MSC Fast DMA mode */
1423#define DMAC_DMACR_FSSI (1 << 30) /* SSI Fast DMA mode */
1424#define DMAC_DMACR_FTSSI (1 << 29) /* TSSI Fast DMA mode */
1425#define DMAC_DMACR_FUART (1 << 28) /* UART Fast DMA mode */
1426#define DMAC_DMACR_FAIC (1 << 27) /* AIC Fast DMA mode */
1427#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
1428#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
1429  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
1430  #define DMAC_DMACR_PR_120345 (1 << DMAC_DMACR_PR_BIT)
1431  #define DMAC_DMACR_PR_230145 (2 << DMAC_DMACR_PR_BIT)
1432  #define DMAC_DMACR_PR_340125 (3 << DMAC_DMACR_PR_BIT)
1433#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
1434#define DMAC_DMACR_AR (1 << 2) /* address error flag */
1435#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
1436
1437// DMA doorbell register
1438#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
1439#define DMAC_DMADBR_DB4 (1 << 4) /* doorbell for channel 4 */
1440#define DMAC_DMADBR_DB3 (1 << 3) /* doorbell for channel 3 */
1441#define DMAC_DMADBR_DB2 (1 << 2) /* doorbell for channel 2 */
1442#define DMAC_DMADBR_DB1 (1 << 1) /* doorbell for channel 1 */
1443#define DMAC_DMADBR_DB0 (1 << 0) /* doorbell for channel 0 */
1444
1445// DMA doorbell set register
1446#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
1447#define DMAC_DMADBSR_DBS4 (1 << 4) /* enable doorbell for channel 4 */
1448#define DMAC_DMADBSR_DBS3 (1 << 3) /* enable doorbell for channel 3 */
1449#define DMAC_DMADBSR_DBS2 (1 << 2) /* enable doorbell for channel 2 */
1450#define DMAC_DMADBSR_DBS1 (1 << 1) /* enable doorbell for channel 1 */
1451#define DMAC_DMADBSR_DBS0 (1 << 0) /* enable doorbell for channel 0 */
1452
1453// DMA interrupt pending register
1454#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
1455#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
1456#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
1457#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
1458#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
1459#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
1460
1461
1462/*************************************************************************
1463 * GPIO (General-Purpose I/O Ports)
1464 *************************************************************************/
1465#define MAX_GPIO_NUM 192
1466
1467//n = 0,1,2,3,4,5
1468#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
1469#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
1470#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
1471#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
1472#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
1473#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
1474#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
1475#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Disable Register */
1476#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Disable Set Reg. */
1477#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Disable Clear Reg. */
1478#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
1479#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
1480#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
1481#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
1482#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
1483#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
1484#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
1485#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
1486#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
1487#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
1488#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
1489#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Clear Register */
1490#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
1491#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
1492
1493#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
1494#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
1495#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
1496#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
1497#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
1498#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
1499#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
1500#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
1501#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
1502#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
1503#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO/INTR, 1:FUNC */
1504#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
1505#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
1506#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
1507#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
1508#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
1509#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
1510#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
1511#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
1512#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:Level-trigger/Fun0, 1:Edge-trigger/Fun1 */
1513#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
1514#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
1515#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
1516#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
1517
1518
1519/*************************************************************************
1520 * UART
1521 *************************************************************************/
1522
1523#define IRDA_BASE UART0_BASE
1524//#define UART_BASE UART0_BASE
1525#define UART_OFF 0x1000
1526
1527/* Register Offset */
1528#define OFF_RDR (0x00) /* R 8b H'xx */
1529#define OFF_TDR (0x00) /* W 8b H'xx */
1530#define OFF_DLLR (0x00) /* RW 8b H'00 */
1531#define OFF_DLHR (0x04) /* RW 8b H'00 */
1532#define OFF_IER (0x04) /* RW 8b H'00 */
1533#define OFF_ISR (0x08) /* R 8b H'01 */
1534#define OFF_FCR (0x08) /* W 8b H'00 */
1535#define OFF_LCR (0x0C) /* RW 8b H'00 */
1536#define OFF_MCR (0x10) /* RW 8b H'00 */
1537#define OFF_LSR (0x14) /* R 8b H'00 */
1538#define OFF_MSR (0x18) /* R 8b H'00 */
1539#define OFF_SPR (0x1C) /* RW 8b H'00 */
1540#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
1541#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
1542#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
1543
1544/* Register Address */
1545#define UART0_RDR (UART0_BASE + OFF_RDR)
1546#define UART0_TDR (UART0_BASE + OFF_TDR)
1547#define UART0_DLLR (UART0_BASE + OFF_DLLR)
1548#define UART0_DLHR (UART0_BASE + OFF_DLHR)
1549#define UART0_IER (UART0_BASE + OFF_IER)
1550#define UART0_ISR (UART0_BASE + OFF_ISR)
1551#define UART0_FCR (UART0_BASE + OFF_FCR)
1552#define UART0_LCR (UART0_BASE + OFF_LCR)
1553#define UART0_MCR (UART0_BASE + OFF_MCR)
1554#define UART0_LSR (UART0_BASE + OFF_LSR)
1555#define UART0_MSR (UART0_BASE + OFF_MSR)
1556#define UART0_SPR (UART0_BASE + OFF_SPR)
1557#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
1558#define UART0_UMR (UART0_BASE + OFF_UMR)
1559#define UART0_UACR (UART0_BASE + OFF_UACR)
1560
1561/*
1562 * Define macros for UART_IER
1563 * UART Interrupt Enable Register
1564 */
1565#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
1566#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
1567#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
1568#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
1569#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
1570
1571/*
1572 * Define macros for UART_ISR
1573 * UART Interrupt Status Register
1574 */
1575#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
1576#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
1577#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
1578#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
1579#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
1580#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
1581#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
1582#define UART_ISR_FFMS_NO_FIFO (0 << 6)
1583#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
1584
1585/*
1586 * Define macros for UART_FCR
1587 * UART FIFO Control Register
1588 */
1589#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
1590#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
1591#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
1592#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
1593#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
1594#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
1595#define UART_FCR_RTRG_1 (0 << 6)
1596#define UART_FCR_RTRG_4 (1 << 6)
1597#define UART_FCR_RTRG_8 (2 << 6)
1598#define UART_FCR_RTRG_15 (3 << 6)
1599
1600/*
1601 * Define macros for UART_LCR
1602 * UART Line Control Register
1603 */
1604#define UART_LCR_WLEN (3 << 0) /* word length */
1605#define UART_LCR_WLEN_5 (0 << 0)
1606#define UART_LCR_WLEN_6 (1 << 0)
1607#define UART_LCR_WLEN_7 (2 << 0)
1608#define UART_LCR_WLEN_8 (3 << 0)
1609#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1610                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1611#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1612                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1613#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1614                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1615
1616#define UART_LCR_PE (1 << 3) /* 0: parity disable */
1617#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
1618#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
1619#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
1620#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
1621
1622/*
1623 * Define macros for UART_LSR
1624 * UART Line Status Register
1625 */
1626#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
1627#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
1628#define UART_LSR_PER (1 << 2) /* 0: no parity error */
1629#define UART_LSR_FER (1 << 3) /* 0; no framing error */
1630#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
1631#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
1632#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
1633#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
1634
1635/*
1636 * Define macros for UART_MCR
1637 * UART Modem Control Register
1638 */
1639#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
1640#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
1641#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
1642#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
1643#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
1644#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
1645
1646/*
1647 * Define macros for UART_MSR
1648 * UART Modem Status Register
1649 */
1650#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
1651#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
1652#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
1653#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
1654#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
1655#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
1656#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
1657#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
1658
1659/*
1660 * Define macros for SIRCR
1661 * Slow IrDA Control Register
1662 */
1663#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
1664#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
1665#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1666                       1: 0 pulse width is 1.6us for 115.2Kbps */
1667#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1668#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1669
1670
1671/*************************************************************************
1672 * AIC (AC97/I2S Controller)
1673 *************************************************************************/
1674#define AIC_FR (AIC_BASE + 0x000)
1675#define AIC_CR (AIC_BASE + 0x004)
1676#define AIC_ACCR1 (AIC_BASE + 0x008)
1677#define AIC_ACCR2 (AIC_BASE + 0x00C)
1678#define AIC_I2SCR (AIC_BASE + 0x010)
1679#define AIC_SR (AIC_BASE + 0x014)
1680#define AIC_ACSR (AIC_BASE + 0x018)
1681#define AIC_I2SSR (AIC_BASE + 0x01C)
1682#define AIC_ACCAR (AIC_BASE + 0x020)
1683#define AIC_ACCDR (AIC_BASE + 0x024)
1684#define AIC_ACSAR (AIC_BASE + 0x028)
1685#define AIC_ACSDR (AIC_BASE + 0x02C)
1686#define AIC_I2SDIV (AIC_BASE + 0x030)
1687#define AIC_DR (AIC_BASE + 0x034)
1688
1689#define REG_AIC_FR REG32(AIC_FR)
1690#define REG_AIC_CR REG32(AIC_CR)
1691#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1692#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1693#define REG_AIC_I2SCR REG32(AIC_I2SCR)
1694#define REG_AIC_SR REG32(AIC_SR)
1695#define REG_AIC_ACSR REG32(AIC_ACSR)
1696#define REG_AIC_I2SSR REG32(AIC_I2SSR)
1697#define REG_AIC_ACCAR REG32(AIC_ACCAR)
1698#define REG_AIC_ACCDR REG32(AIC_ACCDR)
1699#define REG_AIC_ACSAR REG32(AIC_ACSAR)
1700#define REG_AIC_ACSDR REG32(AIC_ACSDR)
1701#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1702#define REG_AIC_DR REG32(AIC_DR)
1703
1704/* AIC Controller Configuration Register (AIC_FR) */
1705
1706#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1707#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1708#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1709#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1710#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1711#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1712#define AIC_FR_RST (1 << 3) /* AIC registers reset */
1713#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1714#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1715#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1716
1717/* AIC Controller Common Control Register (AIC_CR) */
1718
1719#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1720#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1721  #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1722  #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1723  #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1724  #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1725  #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1726#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1727#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1728  #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1729  #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1730  #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1731  #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1732  #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1733#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1734#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1735#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1736#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1737#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1738#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1739#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1740#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1741#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1742#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1743#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1744#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1745#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1746
1747/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1748
1749#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1750#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1751  #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1752  #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1753  #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1754  #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1755  #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1756  #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1757  #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1758  #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1759  #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1760  #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1761#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1762#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1763  #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1764  #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1765  #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1766  #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1767  #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1768  #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1769  #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1770  #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1771  #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1772  #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1773
1774/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1775
1776#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1777#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1778#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1779#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1780#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1781  #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1782  #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1783  #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1784  #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1785#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1786#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1787  #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1788  #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1789  #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1790  #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1791#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1792#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1793#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1794#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1795
1796/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1797
1798#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1799#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1800#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1801  #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1802  #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1803  #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1804  #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1805  #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1806#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1807
1808/* AIC Controller FIFO Status Register (AIC_SR) */
1809
1810#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1811#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1812#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1813#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1814#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1815#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1816#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1817#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1818
1819/* AIC Controller AC-link Status Register (AIC_ACSR) */
1820
1821#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1822#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1823#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1824#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1825#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1826#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1827
1828/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1829
1830#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1831
1832/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1833
1834#define AIC_ACCAR_CAR_BIT 0
1835#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1836
1837/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1838
1839#define AIC_ACCDR_CDR_BIT 0
1840#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1841
1842/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1843
1844#define AIC_ACSAR_SAR_BIT 0
1845#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1846
1847/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1848
1849#define AIC_ACSDR_SDR_BIT 0
1850#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1851
1852/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1853
1854#define AIC_I2SDIV_DIV_BIT 0
1855#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1856  #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1857  #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1858  #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1859  #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1860  #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1861  #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1862
1863
1864/*************************************************************************
1865 * ICDC (Internal CODEC)
1866 *************************************************************************/
1867#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1868#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1869#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1870#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1871#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1872#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1873#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1874
1875#define REG_ICDC_CR REG32(ICDC_CR)
1876#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1877#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1878#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1879#define REG_ICDC_APSR REG32(ICDC_APSR)
1880#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1881#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1882
1883/* ICDC Control Register */
1884#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1885#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1886#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1887#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1888  #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1889  #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1890  #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1891  #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1892  #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1893  #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1894  #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1895  #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1896  #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1897#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1898#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1899  #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1900  #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1901  #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1902  #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1903#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1904#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1905  #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1906  #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1907  #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1908  #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1909#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1910#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1911#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1912#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1913#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1914#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1915#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1916#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1917#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1918#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1919#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1920#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1921
1922/* Anti-Pop WAIT Stage Timing Control Register */
1923#define ICDC_APWAIT_WAITSN_BIT 0
1924#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1925
1926/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1927#define ICDC_APPRE_PRESN_BIT 0
1928#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1929
1930/* Anti-Pop HPEN Stage Timing Control Register */
1931#define ICDC_APHPEN_HPENSN_BIT 0
1932#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1933
1934/* Anti-Pop Status Register */
1935#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1936#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1937#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1938#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1939  #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1940#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1941  #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1942  #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1943  #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1944  #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1945#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1946#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1947
1948
1949/*************************************************************************
1950 * I2C
1951 *************************************************************************/
1952#define I2C_DR (I2C_BASE + 0x000)
1953#define I2C_CR (I2C_BASE + 0x004)
1954#define I2C_SR (I2C_BASE + 0x008)
1955#define I2C_GR (I2C_BASE + 0x00C)
1956
1957#define REG_I2C_DR REG8(I2C_DR)
1958#define REG_I2C_CR REG8(I2C_CR)
1959#define REG_I2C_SR REG8(I2C_SR)
1960#define REG_I2C_GR REG16(I2C_GR)
1961
1962/* I2C Control Register (I2C_CR) */
1963
1964#define I2C_CR_IEN (1 << 4)
1965#define I2C_CR_STA (1 << 3)
1966#define I2C_CR_STO (1 << 2)
1967#define I2C_CR_AC (1 << 1)
1968#define I2C_CR_I2CE (1 << 0)
1969
1970/* I2C Status Register (I2C_SR) */
1971
1972#define I2C_SR_STX (1 << 4)
1973#define I2C_SR_BUSY (1 << 3)
1974#define I2C_SR_TEND (1 << 2)
1975#define I2C_SR_DRF (1 << 1)
1976#define I2C_SR_ACKF (1 << 0)
1977
1978
1979/*************************************************************************
1980 * SSI (Synchronous Serial Interface)
1981 *************************************************************************/
1982/* n = 0, 1, 2 (SSI0, SSI1, SSI2) */
1983#define SSI_DR(n) (SSI##n##_BASE + 0x000)
1984#define SSI_CR0(n) (SSI##n##_BASE + 0x004)
1985#define SSI_CR1(n) (SSI##n##_BASE + 0x008)
1986#define SSI_SR(n) (SSI##n##_BASE + 0x00C)
1987#define SSI_ITR(n) (SSI##n##_BASE + 0x010)
1988#define SSI_ICR(n) (SSI##n##_BASE + 0x014)
1989#define SSI_GR(n) (SSI##n##_BASE + 0x018)
1990
1991#define REG_SSI_DR(n) REG32(SSI_DR(n))
1992#define REG_SSI_CR0(n) REG16(SSI_CR0(n))
1993#define REG_SSI_CR1(n) REG32(SSI_CR1(n))
1994#define REG_SSI_SR(n) REG32(SSI_SR(n))
1995#define REG_SSI_ITR(n) REG16(SSI_ITR(n))
1996#define REG_SSI_ICR(n) REG8(SSI_ICR(n))
1997#define REG_SSI_GR(n) REG16(SSI_GR(n))
1998
1999/* SSI Data Register (SSI_DR) */
2000
2001#define SSI_DR_GPC_BIT 0
2002#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
2003
2004#define SSI_MAX_FIFO_ENTRIES 128 /* 128 txfifo and 128 rxfifo */
2005
2006/* SSI Control Register 0 (SSI_CR0) */
2007
2008#define SSI_CR0_SSIE (1 << 15)
2009#define SSI_CR0_TIE (1 << 14)
2010#define SSI_CR0_RIE (1 << 13)
2011#define SSI_CR0_TEIE (1 << 12)
2012#define SSI_CR0_REIE (1 << 11)
2013#define SSI_CR0_LOOP (1 << 10)
2014#define SSI_CR0_RFINE (1 << 9)
2015#define SSI_CR0_RFINC (1 << 8)
2016#define SSI_CR0_EACLRUN (1 << 7) /* hardware auto clear underrun when TxFifo no empty */
2017#define SSI_CR0_FSEL (1 << 6)
2018#define SSI_CR0_TFLUSH (1 << 2)
2019#define SSI_CR0_RFLUSH (1 << 1)
2020#define SSI_CR0_DISREV (1 << 0)
2021
2022/* SSI Control Register 1 (SSI_CR1) */
2023
2024#define SSI_CR1_FRMHL_BIT 30
2025#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
2026  #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
2027  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
2028  #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
2029  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
2030#define SSI_CR1_TFVCK_BIT 28
2031#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
2032  #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
2033  #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
2034  #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
2035  #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
2036#define SSI_CR1_TCKFI_BIT 26
2037#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
2038  #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
2039  #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
2040  #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
2041  #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
2042#define SSI_CR1_LFST (1 << 25)
2043#define SSI_CR1_ITFRM (1 << 24)
2044#define SSI_CR1_UNFIN (1 << 23)
2045#define SSI_CR1_MULTS (1 << 22)
2046#define SSI_CR1_FMAT_BIT 20
2047#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
2048  #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
2049  #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
2050  #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
2051  #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
2052#define SSI_CR1_TTRG_BIT 16 /* SSI1 TX trigger */
2053#define SSI_CR1_TTRG_MASK (0xf << SSI1_CR1_TTRG_BIT)
2054#define SSI_CR1_MCOM_BIT 12
2055#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
2056  #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
2057  #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
2058  #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
2059  #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
2060  #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
2061  #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
2062  #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
2063  #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
2064  #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
2065  #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
2066  #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
2067  #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
2068  #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
2069  #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
2070  #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
2071  #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
2072#define SSI_CR1_RTRG_BIT 8 /* SSI RX trigger */
2073#define SSI_CR1_RTRG_MASK (0xf << SSI1_CR1_RTRG_BIT)
2074#define SSI_CR1_FLEN_BIT 4
2075#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
2076  #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
2077  #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
2078  #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
2079  #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
2080  #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
2081  #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
2082  #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
2083  #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
2084  #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
2085  #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
2086  #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
2087  #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
2088  #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
2089  #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
2090  #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
2091  #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
2092#define SSI_CR1_PHA (1 << 1)
2093#define SSI_CR1_POL (1 << 0)
2094
2095/* SSI Status Register (SSI_SR) */
2096
2097#define SSI_SR_TFIFONUM_BIT 16
2098#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
2099#define SSI_SR_RFIFONUM_BIT 8
2100#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
2101#define SSI_SR_END (1 << 7)
2102#define SSI_SR_BUSY (1 << 6)
2103#define SSI_SR_TFF (1 << 5)
2104#define SSI_SR_RFE (1 << 4)
2105#define SSI_SR_TFHE (1 << 3)
2106#define SSI_SR_RFHF (1 << 2)
2107#define SSI_SR_UNDR (1 << 1)
2108#define SSI_SR_OVER (1 << 0)
2109
2110/* SSI Interval Time Control Register (SSI_ITR) */
2111
2112#define SSI_ITR_CNTCLK (1 << 15)
2113#define SSI_ITR_IVLTM_BIT 0
2114#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
2115
2116
2117/*************************************************************************
2118 * MSC
2119 *************************************************************************/
2120#define MSC_STRPCL (MSC0_BASE + 0x000)
2121#define MSC_STAT (MSC0_BASE + 0x004)
2122#define MSC_CLKRT (MSC0_BASE + 0x008)
2123#define MSC_CMDAT (MSC0_BASE + 0x00C)
2124#define MSC_RESTO (MSC0_BASE + 0x010)
2125#define MSC_RDTO (MSC0_BASE + 0x014)
2126#define MSC_BLKLEN (MSC0_BASE + 0x018)
2127#define MSC_NOB (MSC0_BASE + 0x01C)
2128#define MSC_SNOB (MSC0_BASE + 0x020)
2129#define MSC_IMASK (MSC0_BASE + 0x024)
2130#define MSC_IREG (MSC0_BASE + 0x028)
2131#define MSC_CMD (MSC0_BASE + 0x02C)
2132#define MSC_ARG (MSC0_BASE + 0x030)
2133#define MSC_RES (MSC0_BASE + 0x034)
2134#define MSC_RXFIFO (MSC0_BASE + 0x038)
2135#define MSC_TXFIFO (MSC0_BASE + 0x03C)
2136
2137#define REG_MSC_STRPCL REG16(MSC_STRPCL)
2138#define REG_MSC_STAT REG32(MSC_STAT)
2139#define REG_MSC_CLKRT REG16(MSC_CLKRT)
2140#define REG_MSC_CMDAT REG32(MSC_CMDAT)
2141#define REG_MSC_RESTO REG16(MSC_RESTO)
2142#define REG_MSC_RDTO REG16(MSC_RDTO)
2143#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
2144#define REG_MSC_NOB REG16(MSC_NOB)
2145#define REG_MSC_SNOB REG16(MSC_SNOB)
2146#define REG_MSC_IMASK REG16(MSC_IMASK)
2147#define REG_MSC_IREG REG16(MSC_IREG)
2148#define REG_MSC_CMD REG8(MSC_CMD)
2149#define REG_MSC_ARG REG32(MSC_ARG)
2150#define REG_MSC_RES REG16(MSC_RES)
2151#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
2152#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
2153
2154/* MSC Clock and Control Register (MSC_STRPCL) */
2155
2156#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
2157#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
2158#define MSC_STRPCL_START_READWAIT (1 << 5)
2159#define MSC_STRPCL_STOP_READWAIT (1 << 4)
2160#define MSC_STRPCL_RESET (1 << 3)
2161#define MSC_STRPCL_START_OP (1 << 2)
2162#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
2163#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
2164  #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
2165  #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
2166
2167/* MSC Status Register (MSC_STAT) */
2168
2169#define MSC_STAT_IS_RESETTING (1 << 15)
2170#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
2171#define MSC_STAT_PRG_DONE (1 << 13)
2172#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
2173#define MSC_STAT_END_CMD_RES (1 << 11)
2174#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
2175#define MSC_STAT_IS_READWAIT (1 << 9)
2176#define MSC_STAT_CLK_EN (1 << 8)
2177#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
2178#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
2179#define MSC_STAT_CRC_RES_ERR (1 << 5)
2180#define MSC_STAT_CRC_READ_ERROR (1 << 4)
2181#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
2182#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
2183  #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
2184  #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
2185  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
2186#define MSC_STAT_TIME_OUT_RES (1 << 1)
2187#define MSC_STAT_TIME_OUT_READ (1 << 0)
2188
2189/* MSC Bus Clock Control Register (MSC_CLKRT) */
2190
2191#define MSC_CLKRT_CLK_RATE_BIT 0
2192#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
2193  #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
2194  #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
2195  #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
2196  #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
2197  #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
2198  #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
2199  #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
2200  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
2201
2202/* MSC Command Sequence Control Register (MSC_CMDAT) */
2203
2204#define MSC_CMDAT_IO_ABORT (1 << 11)
2205#define MSC_CMDAT_BUS_WIDTH_BIT 9
2206#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
2207  #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
2208  #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
2209  #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
2210  #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
2211#define MSC_CMDAT_DMA_EN (1 << 8)
2212#define MSC_CMDAT_INIT (1 << 7)
2213#define MSC_CMDAT_BUSY (1 << 6)
2214#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
2215#define MSC_CMDAT_WRITE (1 << 4)
2216#define MSC_CMDAT_READ (0 << 4)
2217#define MSC_CMDAT_DATA_EN (1 << 3)
2218#define MSC_CMDAT_RESPONSE_BIT 0
2219#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
2220  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
2221  #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
2222  #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
2223  #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
2224  #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
2225  #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
2226  #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
2227
2228#define CMDAT_DMA_EN (1 << 8)
2229#define CMDAT_INIT (1 << 7)
2230#define CMDAT_BUSY (1 << 6)
2231#define CMDAT_STREAM (1 << 5)
2232#define CMDAT_WRITE (1 << 4)
2233#define CMDAT_DATA_EN (1 << 3)
2234
2235/* MSC Interrupts Mask Register (MSC_IMASK) */
2236
2237#define MSC_IMASK_SDIO (1 << 7)
2238#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
2239#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
2240#define MSC_IMASK_END_CMD_RES (1 << 2)
2241#define MSC_IMASK_PRG_DONE (1 << 1)
2242#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
2243
2244
2245/* MSC Interrupts Status Register (MSC_IREG) */
2246
2247#define MSC_IREG_SDIO (1 << 7)
2248#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
2249#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
2250#define MSC_IREG_END_CMD_RES (1 << 2)
2251#define MSC_IREG_PRG_DONE (1 << 1)
2252#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
2253
2254/*************************************************************************
2255 * EMC (External SDR Controller)
2256 *************************************************************************/
2257#define EMC_LOW_SDRAM_SPACE_SIZE 0x10000000 /* 256M */
2258#define EMC_MEM_PHY_BASE 0x20000000
2259#define EMC_MEM_PHY_BASE_SHIFT 24
2260
2261
2262#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
2263
2264#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
2265#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
2266#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
2267#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
2268
2269#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
2270#define EMC_DMAR1 (EMC_BASE + 0x94) /* SDRAM Bank 1 Addr Config Register */
2271#define EMC_SDMR0 (EMC_BASE + 0x8000) /* Mode Register of SDRAM bank 0 */
2272
2273#define REG_EMC_BCR REG32(EMC_BCR)
2274
2275#define REG_EMC_DMCR REG32(EMC_DMCR)
2276#define REG_EMC_RTCSR REG16(EMC_RTCSR)
2277#define REG_EMC_RTCNT REG16(EMC_RTCNT)
2278#define REG_EMC_RTCOR REG16(EMC_RTCOR)
2279#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
2280#define REG_EMC_DMAR1 REG32(EMC_DMAR1)
2281
2282#define EMC_PMEMPS0 (EMC_BASE + 0x6008)
2283#define EMC_PMEMPS1 (EMC_BASE + 0x6004)
2284#define EMC_PMEMPS2 (EMC_BASE + 0x600c)
2285#define EMC_PMEMPS3 (EMC_BASE + 0x6010)
2286 
2287#define REG_EMC_PMEMPS0 REG32(EMC_PMEMPS0)
2288#define REG_EMC_PMEMPS1 REG32(EMC_PMEMPS1)
2289#define REG_EMC_PMEMPS2 REG32(EMC_PMEMPS2)
2290#define REG_EMC_PMEMPS3 REG32(EMC_PMEMPS3)
2291
2292
2293/* DRAM Control Register */
2294#define EMC_DMCR_BW_BIT 31
2295#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
2296#define EMC_DMCR_CA_BIT 26
2297#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
2298  #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
2299  #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
2300  #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
2301  #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
2302  #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
2303#define EMC_DMCR_RMODE (1 << 25)
2304#define EMC_DMCR_RFSH (1 << 24)
2305#define EMC_DMCR_MRSET (1 << 23)
2306#define EMC_DMCR_RA_BIT 20
2307#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
2308  #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
2309  #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
2310  #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
2311#define EMC_DMCR_BA_BIT 19
2312#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
2313#define EMC_DMCR_PDM (1 << 18)
2314#define EMC_DMCR_EPIN (1 << 17)
2315#define EMC_DMCR_MBSEL_BIT 16
2316  #define EMC_DMCR_MBSEL_B0 (0 << 16)
2317  #define EMC_DMCR_MBSEL_B1 (1 << 16)
2318#define EMC_DMCR_TRAS_BIT 13
2319#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
2320#define EMC_DMCR_RCD_BIT 11
2321#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
2322#define EMC_DMCR_TPC_BIT 8
2323#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
2324#define EMC_DMCR_TRWL_BIT 5
2325#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
2326#define EMC_DMCR_TRC_BIT 2
2327#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
2328#define EMC_DMCR_TCL_BIT 0
2329#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
2330
2331/* Refresh Time Control/Status Register */
2332#define EMC_RTCSR_CMF (1 << 7)
2333#define EMC_RTCSR_CKS_BIT 0
2334#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
2335  #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
2336  #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
2337  #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
2338  #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
2339  #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
2340  #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
2341  #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
2342  #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
2343
2344/* SDRAM Bank Address Configuration Register */
2345#define EMC_DMAR_BASE_BIT 8
2346#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
2347#define EMC_DMAR_MASK_BIT 0
2348#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
2349
2350/* Mode Register of SDRAM bank 0 */
2351#define EMC_SDMR_BM (1 << 9) /* Write Single Mode */
2352#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
2353#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
2354  #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
2355#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
2356#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
2357  #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
2358  #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
2359  #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
2360#define EMC_SDMR_BT_BIT 3 /* Burst Type */
2361#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
2362  #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
2363  #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
2364#define EMC_SDMR_BL_BIT 0 /* Burst Length */
2365#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
2366  #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
2367  #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
2368  #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
2369  #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
2370
2371#define EMC_SDMR_CAS2_16BIT \
2372  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
2373#define EMC_SDMR_CAS2_32BIT \
2374  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
2375#define EMC_SDMR_CAS3_16BIT \
2376  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
2377#define EMC_SDMR_CAS3_32BIT \
2378  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
2379
2380/* Extended Mode Register of Mobile SDRAM*/
2381#define EMC_SDMR_SET_BA1 (1 << 14) /*BA1*/
2382#define EMC_SDMR_SET_BA0 (1 << 13) /*BA0*/
2383
2384#define EMC_SDMR_DS_BIT 5 /* Driver strength */
2385#define EMC_SDMR_DS_MASK (3 << EMC_SDMR_DS_BIT)
2386  #define EMC_SDMR_DS_FULL (0 << EMC_SDMR_DS_BIT) /*Full*/
2387  #define EMC_SDMR_DS_HALF (1 << EMC_SDMR_DS_BIT) /*1/2 Strength*/
2388  #define EMC_SDMR_DS_QUTR (2 << EMC_SDMR_DS_BIT) /*1/4 Strength*/
2389
2390#define EMC_SDMR_PRSR_BIT 0 /* Partial Array Self Refresh */
2391#define EMC_SDMR_PRSR_MASK (7 << EMC_SDMR_PRSR_BIT)
2392  #define EMC_SDMR_PRSR_ALL (0 << EMC_SDMR_PRSR_BIT) /*All Banks*/
2393  #define EMC_SDMR_PRSR_HALF_TL (1 << EMC_SDMR_PRSR_BIT) /*Half of Total Bank*/
2394  #define EMC_SDMR_PRSR_QUTR_TL (2 << EMC_SDMR_PRSR_BIT) /*Quarter of Total Bank*/
2395  #define EMC_SDMR_PRSR_HALF_B0 (5 << EMC_SDMR_PRSR_BIT) /*Half of Bank0*/
2396  #define EMC_SDMR_PRSR_QUTR_B0 (6 << EMC_SDMR_PRSR_BIT) /*Quarter of Bank0*/
2397
2398#define EMC_DMAR_BASE_BIT 8
2399#define EMC_DMAR_MASK_BIT 0
2400
2401#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
2402#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
2403
2404#define EMC_DMAR0_BASE (0x20 << EMC_DMAR_BASE_BIT)
2405#define EMC_DMAR1_BASE_64M (0x24 << EMC_DMAR_BASE_BIT) /*when bank0 is 64M*/
2406#define EMC_DMAR1_BASE_128M (0x28 << EMC_DMAR_BASE_BIT) /*when bank0 is 128M*/
2407
2408#define EMC_DMAR_MASK_64_64 (0xfc << EMC_DMAR_MASK_BIT) /*mask for two 64M SDRAM*/
2409#define EMC_DMAR_MASK_128_128 (0xf8 << EMC_DMAR_MASK_BIT) /*mask for two 128M SDRAM*/
2410
2411#define EMC_PMEMPS0_PDDQS_BIT 28
2412 #define EMC_PMEMPS0_PDDQS (0xf << EMC_PMEMPS0_PDDQS_BIT)
2413#define EMC_PMEMPS0_PDDQ_BIT 24
2414 #define EMC_PMEMPS0_PDDQ (0xf << EMC_PMEMPS0_PDDQ_BIT)
2415#define EMC_PMEMPS0_SCHMITT_TRIGGER_DQS_BIT 20
2416 #define EMC_PMEMPS0_SCHMITT_TRIGGER_DQS (0xf << EMC_PMEMPS0_SCHMITT_TRIGGER_DQS_BIT)
2417#define EMC_PMEMPS0_SCHMITT_TRIGGER_DQ_BIT 16
2418 #define EMC_PMEMPS0_SCHMITT_TRIGGER_DQ (0xf << EMC_PMEMPS0_SCHMITT_TRIGGER_DQ_BIT)
2419#define EMC_PMEMPS0_ENPULL_DQS_BIT 12
2420 #define EMC_PMEMPS0_ENPULL_DQS (0xf << EMC_PMEMPS0_ENPULL_DQS_BIT)
2421#define EMC_PMEMPS0_ENPULL_DQ_BIT 8
2422 #define EMC_PMEMPS0_ENPULL_DQ (0xf << EMC_PMEMPS0_ENPULL_DQ_BIT)
2423#define EMC_PMEMPS0_PULLUP_DQS_BIT 4
2424 #define EMC_PMEMPS0_PULLUP_DQS (0xf << EMC_PMEMPS0_PULLUP_DQS_BIT)
2425#define EMC_PMEMPS0_PULLUP_DQ_BIT 0
2426 #define EMC_PMEMPS0_PULLUP_DQ (0xf << EMC_PMEMPS0_PULLUP_DQ_BIT)
2427
2428#define EMC_PMEMPS1_INEDQS_BIT 28
2429 #define EMC_PMEMPS1_INEDQS (0xf << EMC_PMEMPS1_INEDQS_BIT)
2430#define EMC_PMEMPS1_INEDQ_BIT 24
2431 #define EMC_PMEMPS1_INEDQ (0xf << EMC_PMEMPS1_INEDQ_BIT)
2432#define EMC_PMEMPS1_SSTL_MODE (1 << 16)
2433#define EMC_PMEMPS1_STRENGTH_DQS_BIT 8
2434 #define EMC_PMEMPS1_STRENGTH_DQS_FULL (0xff << EMC_PMEMPS1_STRENGTH_DQS_BIT)
2435#define EMC_PMEMPS1_STRENGTH_DQ_BIT 0
2436 #define EMC_PMEMPS1_STRENGTH_DQ_FULL (0xff << EMC_PMEMPS1_STRENGTH_DQ_BIT)
2437
2438#define EMC_PMEMPS2_STRENGTH_CKO_BIT 18
2439#define EMC_PMEMPS2_STRENGTH_CKE_BIT 16
2440#define EMC_PMEMPS2_STRENGTH_ADDR_BIT 14
2441#define EMC_PMEMPS2_STRENGTH_DM3_BIT 12
2442#define EMC_PMEMPS2_STRENGTH_DM2_BIT 10
2443#define EMC_PMEMPS2_STRENGTH_DM1_BIT 8
2444#define EMC_PMEMPS2_STRENGTH_DM0_BIT 6
2445#define EMC_PMEMPS2_STRENGTH_CMD_BIT 4
2446#define EMC_PMEMPS2_STRENGTH_CS1_BIT 2
2447#define EMC_PMEMPS2_STRENGTH_CS0_BIT 0
2448
2449#define EMC_PMEMPS2_STRENGTH_ALL_FULL ((1 << 20) - 1)
2450
2451#define STRENGTH_SSTL18_REDUCED 1
2452#define STRENGTH_SSTL18_FULL 3
2453#define STRENGTH_SSTL2_REDUCED 0
2454#define STRENGTH_SSTL2_FULL 2
2455#define STRENGTH_LPDDR_REDUCED 0
2456#define STRENGTH_LPDDR_FULL 3
2457#define STRENGTH_LVTTL_12MA_REDUCED 0
2458#define STRENGTH_LVTTL_16MA_REDUCED 1
2459#define STRENGTH_LVTTL_24MA_FULL 2
2460#define STRENGTH_LVTTL_30MA_FULL 3
2461
2462/*************************************************************************
2463 * NEMC (External Normal Memory Controller)
2464 *************************************************************************/
2465#define NEMC_BCR (NEMC_BASE + 0x0) /* BCR */
2466
2467#define NEMC_SMCR1 (NEMC_BASE + 0x14) /* Static Memory Control Register 1 */
2468#define NEMC_SMCR2 (NEMC_BASE + 0x18) /* Static Memory Control Register 2 */
2469#define NEMC_SMCR3 (NEMC_BASE + 0x1c) /* Static Memory Control Register 3 */
2470#define NEMC_SMCR4 (NEMC_BASE + 0x20) /* Static Memory Control Register 4 */
2471#define NEMC_SMCR5 (NEMC_BASE + 0x24) /* Static Memory Control Register 5 */
2472#define NEMC_SMCR6 (NEMC_BASE + 0x28) /* Static Memory Control Register 6 */
2473#define NEMC_SACR1 (NEMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
2474#define NEMC_SACR2 (NEMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
2475#define NEMC_SACR3 (NEMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
2476#define NEMC_SACR4 (NEMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
2477#define NEMC_SACR5 (NEMC_BASE + 0x44) /* Static Memory Bank 5 Addr Config Reg */
2478#define NEMC_SACR6 (NEMC_BASE + 0x48) /* Static Memory Bank 6 Addr Config Reg */
2479
2480#define NEMC_NFCSR (NEMC_BASE + 0x050) /* NAND Flash Control/Status Register */
2481
2482#define REG_NEMC_BCR REG32(NEMC_BCR)
2483#define REG_NEMC_SMCR1 REG32(NEMC_SMCR1)
2484#define REG_NEMC_SMCR2 REG32(NEMC_SMCR2)
2485#define REG_NEMC_SMCR3 REG32(NEMC_SMCR3)
2486#define REG_NEMC_SMCR4 REG32(NEMC_SMCR4)
2487#define REG_NEMC_SMCR5 REG32(NEMC_SMCR5)
2488#define REG_NEMC_SMCR6 REG32(NEMC_SMCR6)
2489#define REG_NEMC_SACR1 REG32(NEMC_SACR1)
2490#define REG_NEMC_SACR2 REG32(NEMC_SACR2)
2491#define REG_NEMC_SACR3 REG32(NEMC_SACR3)
2492#define REG_NEMC_SACR4 REG32(NEMC_SACR4)
2493#define REG_NEMC_SACR5 REG32(NEMC_SACR5)
2494#define REG_NEMC_SACR6 REG32(NEMC_SACR6)
2495
2496
2497#define REG_NEMC_NFCSR REG32(NEMC_NFCSR)
2498
2499
2500/* Bus Control Register */
2501#define NEMC_BCR_BT_SEL_BIT 30
2502#define NEMC_BCR_BT_SEL_MASK (0x3 << NEMC_BCR_BT_SEL_BIT)
2503#define NEMC_BCR_PK_SEL (1 << 24)
2504#define NEMC_BCR_BSR_MASK (1 << 2) /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */
2505  #define NEMC_BCR_BSR_SHARE (0 << 2)
2506  #define NEMC_BCR_BSR_UNSHARE (1 << 2)
2507#define NEMC_BCR_BRE (1 << 1)
2508#define NEMC_BCR_ENDIAN (1 << 0)
2509
2510/* Static Memory Control Register */
2511#define NEMC_SMCR_STRV_BIT 24
2512#define NEMC_SMCR_STRV_MASK (0x0f << NEMC_SMCR_STRV_BIT)
2513#define NEMC_SMCR_TAW_BIT 20
2514#define NEMC_SMCR_TAW_MASK (0x0f << NEMC_SMCR_TAW_BIT)
2515#define NEMC_SMCR_TBP_BIT 16
2516#define NEMC_SMCR_TBP_MASK (0x0f << NEMC_SMCR_TBP_BIT)
2517#define NEMC_SMCR_TAH_BIT 12
2518#define NEMC_SMCR_TAH_MASK (0x07 << NEMC_SMCR_TAH_BIT)
2519#define NEMC_SMCR_TAS_BIT 8
2520#define NEMC_SMCR_TAS_MASK (0x07 << NEMC_SMCR_TAS_BIT)
2521#define NEMC_SMCR_BW_BIT 6
2522#define NEMC_SMCR_BW_MASK (0x03 << NEMC_SMCR_BW_BIT)
2523  #define NEMC_SMCR_BW_8BIT (0 << NEMC_SMCR_BW_BIT)
2524  #define NEMC_SMCR_BW_16BIT (1 << NEMC_SMCR_BW_BIT)
2525  #define NEMC_SMCR_BW_32BIT (2 << NEMC_SMCR_BW_BIT)
2526#define NEMC_SMCR_BCM (1 << 3)
2527#define NEMC_SMCR_BL_BIT 1
2528#define NEMC_SMCR_BL_MASK (0x03 << NEMC_SMCR_BL_BIT)
2529  #define NEMC_SMCR_BL_4 (0 << NEMC_SMCR_BL_BIT)
2530  #define NEMC_SMCR_BL_8 (1 << NEMC_SMCR_BL_BIT)
2531  #define NEMC_SMCR_BL_16 (2 << NEMC_SMCR_BL_BIT)
2532  #define NEMC_SMCR_BL_32 (3 << NEMC_SMCR_BL_BIT)
2533#define NEMC_SMCR_SMT (1 << 0)
2534
2535/* Static Memory Bank Addr Config Reg */
2536#define NEMC_SACR_BASE_BIT 8
2537#define NEMC_SACR_BASE_MASK (0xff << NEMC_SACR_BASE_BIT)
2538#define NEMC_SACR_MASK_BIT 0
2539#define NEMC_SACR_MASK_MASK (0xff << NEMC_SACR_MASK_BIT)
2540
2541/* NAND Flash Control/Status Register */
2542#define NEMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
2543#define NEMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
2544#define NEMC_NFCSR_NFCE3 (1 << 5)
2545#define NEMC_NFCSR_NFE3 (1 << 4)
2546#define NEMC_NFCSR_NFCE2 (1 << 3)
2547#define NEMC_NFCSR_NFE2 (1 << 2)
2548#define NEMC_NFCSR_NFCE1 (1 << 1)
2549#define NEMC_NFCSR_NFE1 (1 << 0)
2550
2551/*************************************************************************
2552 * DDRC (DDR Controller)
2553 *************************************************************************/
2554#define DDR_MEM_PHY_BASE 0x20000000
2555
2556#define DDRC_ST (DDRC_BASE + 0x0) /* DDR Status Register */
2557#define DDRC_CFG (DDRC_BASE + 0x4) /* DDR Configure Register */
2558#define DDRC_CTRL (DDRC_BASE + 0x8) /* DDR Control Register */
2559#define DDRC_LMR (DDRC_BASE + 0xc) /* DDR Load-Mode-Register */
2560#define DDRC_TIMING1 (DDRC_BASE + 0x10) /* DDR Timing Config Register 1 */
2561#define DDRC_TIMING2 (DDRC_BASE + 0x14) /* DDR Timing Config Register 2 */
2562#define DDRC_REFCNT (DDRC_BASE + 0x18) /* DDR Auto-Refresh Counter */
2563#define DDRC_DQS (DDRC_BASE + 0x1c) /* DDR DQS Delay Control Register */
2564#define DDRC_DQS_ADJ (DDRC_BASE + 0x20) /* DDR DQS Delay Adjust Register */
2565#define DDRC_MMAP0 (DDRC_BASE + 0x24) /* DDR Memory Map Config Register */
2566#define DDRC_MMAP1 (DDRC_BASE + 0x28) /* DDR Memory Map Config Register */
2567#define DDRC_MDELAY (DDRC_BASE + 0x2c) /* DDR Memory Map Config Register */
2568
2569/* DDRC Register */
2570#define REG_DDRC_ST REG32(DDRC_ST)
2571#define REG_DDRC_CFG REG32(DDRC_CFG)
2572#define REG_DDRC_CTRL REG32(DDRC_CTRL)
2573#define REG_DDRC_LMR REG32(DDRC_LMR)
2574#define REG_DDRC_TIMING1 REG32(DDRC_TIMING1)
2575#define REG_DDRC_TIMING2 REG32(DDRC_TIMING2)
2576#define REG_DDRC_REFCNT REG32(DDRC_REFCNT)
2577#define REG_DDRC_DQS REG32(DDRC_DQS)
2578#define REG_DDRC_DQS_ADJ REG32(DDRC_DQS_ADJ)
2579#define REG_DDRC_MMAP0 REG32(DDRC_MMAP0)
2580#define REG_DDRC_MMAP1 REG32(DDRC_MMAP1)
2581#define REG_DDRC_MDELAY REG32(DDRC_MDELAY)
2582
2583/* DDRC Status Register */
2584#define DDRC_ST_ENDIAN (1 << 7) /* 0 Little data endian
2585                        1 Big data endian */
2586#define DDRC_ST_DPDN (1 << 5) /* 0 DDR memory is NOT in deep-power-down state
2587                        1 DDR memory is in deep-power-down state */
2588#define DDRC_ST_PDN (1 << 4) /* 0 DDR memory is NOT in power-down state
2589                        1 DDR memory is in power-down state */
2590#define DDRC_ST_AREF (1 << 3) /* 0 DDR memory is NOT in auto-refresh state
2591                        1 DDR memory is in auto-refresh state */
2592#define DDRC_ST_SREF (1 << 2) /* 0 DDR memory is NOT in self-refresh state
2593                        1 DDR memory is in self-refresh state */
2594#define DDRC_ST_CKE1 (1 << 1) /* 0 CKE1 Pin is low
2595                        1 CKE1 Pin is high */
2596#define DDRC_ST_CKE0 (1 << 0) /* 0 CKE0 Pin is low
2597                        1 CKE0 Pin is high */
2598
2599/* DDRC Configure Register */
2600#define DDRC_CFG_MSEL_BIT 16 /* Mask delay select */
2601#define DDRC_CFG_MSEL_MASK (0x3 << DDRC_CFG_MSEL_BIT)
2602  #define DDRC_CFG_MSEL_0 (0 << DDRC_CFG_MSEL_BIT) /* 00 No delay */
2603  #define DDRC_CFG_MSEL_1 (1 << DDRC_CFG_MSEL_BIT) /* 01 delay 1 tCK */
2604  #define DDRC_CFG_MSEL_2 (2 << DDRC_CFG_MSEL_BIT) /* 10 delay 2 tCK */
2605  #define DDRC_CFG_MSEL_3 (3 << DDRC_CFG_MSEL_BIT) /* 11 delay 3 tCK */
2606
2607#define DDRC_CFG_MPRT (1 << 15) /* mem protect */
2608
2609#define DDRC_CFG_ROW1_BIT 27 /* Row Address width. */
2610#define DDRC_CFG_COL1_BIT 25 /* Row Address width. */
2611#define DDRC_CFG_BA1 (1 << 24)
2612#define DDRC_CFG_IMBA (1 << 23)
2613#define DDRC_CFG_BTRUN (1 << 21)
2614
2615#define DDRC_CFG_TYPE_BIT 12
2616#define DDRC_CFG_TYPE_MASK (0x7 << DDRC_CFG_TYPE_BIT)
2617#define DDRC_CFG_TYPE_DDR1 (2 << DDRC_CFG_TYPE_BIT)
2618#define DDRC_CFG_TYPE_MDDR (3 << DDRC_CFG_TYPE_BIT)
2619#define DDRC_CFG_TYPE_DDR2 (4 << DDRC_CFG_TYPE_BIT)
2620
2621#define DDRC_CFG_ROW_BIT 10 /* Row Address width. */
2622#define DDRC_CFG_ROW_MASK (0x3 << DDRC_CFG_ROW_BIT)
2623  #define DDRC_CFG_ROW_13 (0 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */
2624  #define DDRC_CFG_ROW_14 (1 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */
2625
2626#define DDRC_CFG_COL_BIT 8 /* Column Address width.
2627                     Specify the Column address width of external DDR. */
2628#define DDRC_CFG_COL_MASK (0x3 << DDRC_CFG_COL_BIT)
2629  #define DDRC_CFG_COL_9 (0 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */
2630  #define DDRC_CFG_COL_10 (1 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */
2631
2632#define DDRC_CFG_CS1EN (1 << 7) /* 0 DDR Pin CS1 un-used
2633                        1 There're DDR memory connected to CS1 */
2634#define DDRC_CFG_CS0EN (1 << 6) /* 0 DDR Pin CS0 un-used
2635                        1 There're DDR memory connected to CS0 */
2636
2637#define DDRC_CFG_TSEL_BIT 18 /* Read delay select */
2638#define DDRC_CFG_TSEL_MASK (0x3 << DDRC_CFG_TSEL_BIT)
2639#define DDRC_CFG_TSEL_0 (0 << DDRC_CFG_TSEL_BIT) /* No delay */
2640#define DDRC_CFG_TSEL_1 (1 << DDRC_CFG_TSEL_BIT) /* delay 1 tCK */
2641#define DDRC_CFG_TSEL_2 (2 << DDRC_CFG_TSEL_BIT) /* delay 2 tCK */
2642#define DDRC_CFG_TSEL_3 (3 << DDRC_CFG_TSEL_BIT) /* delay 3 tCK */
2643
2644#define DDRC_CFG_CL_BIT 2 /* CAS Latency */
2645#define DDRC_CFG_CL_MASK (0xf << DDRC_CFG_CL_BIT)
2646#define DDRC_CFG_CL_3 (0 << DDRC_CFG_CL_BIT) /* CL = 3 tCK */
2647#define DDRC_CFG_CL_4 (1 << DDRC_CFG_CL_BIT) /* CL = 4 tCK */
2648#define DDRC_CFG_CL_5 (2 << DDRC_CFG_CL_BIT) /* CL = 5 tCK */
2649#define DDRC_CFG_CL_6 (3 << DDRC_CFG_CL_BIT) /* CL = 6 tCK */
2650
2651#define DDRC_CFG_BA (1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used
2652                        1 8 bank device, Pin ba[2:0] valid*/
2653#define DDRC_CFG_DW (1 << 0) /*0 External memory data width is 16-bit
2654                       1 External memory data width is 32-bit */
2655
2656/* DDRC Control Register */
2657#define DDRC_CTRL_ACTPD (1 << 15) /* 0 Precharge all banks before entering power-down
2658                         1 Do not precharge banks before entering power-down */
2659#define DDRC_CTRL_PDT_BIT 12 /* Power-Down Timer */
2660#define DDRC_CTRL_PDT_MASK (0x7 << DDRC_CTRL_PDT_BIT)
2661  #define DDRC_CTRL_PDT_DIS (0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
2662  #define DDRC_CTRL_PDT_8 (1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
2663  #define DDRC_CTRL_PDT_16 (2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
2664  #define DDRC_CTRL_PDT_32 (3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
2665  #define DDRC_CTRL_PDT_64 (4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
2666  #define DDRC_CTRL_PDT_128 (5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */
2667
2668#define DDRC_CTRL_PRET_BIT 8 /* Precharge Timer */
2669#define DDRC_CTRL_PRET_MASK (0x7 << DDRC_CTRL_PRET_BIT) /* */
2670  #define DDRC_CTRL_PRET_DIS (0 << DDRC_CTRL_PRET_BIT) /* PRET function Disabled */
2671  #define DDRC_CTRL_PRET_8 (1 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 8 tCK idle */
2672  #define DDRC_CTRL_PRET_16 (2 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 16 tCK idle */
2673  #define DDRC_CTRL_PRET_32 (3 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 32 tCK idle */
2674  #define DDRC_CTRL_PRET_64 (4 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 64 tCK idle */
2675  #define DDRC_CTRL_PRET_128 (5 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 128 tCK idle */
2676
2677#define DDRC_CTRL_DPD (1 << 6) /* 1 Drive external DDR device entering self-refresh mode */
2678
2679#define DDRC_CTRL_SR (1 << 5) /* 1 Drive external DDR device entering self-refresh mode
2680                        0 Drive external DDR device exiting self-refresh mode */
2681#define DDRC_CTRL_UNALIGN (1 << 4) /* 0 Disable unaligned transfer on AXI BUS
2682                        1 Enable unaligned transfer on AXI BUS */
2683#define DDRC_CTRL_ALH (1 << 3) /* Advanced Latency Hiding:
2684                        0 Disable ALH
2685                        1 Enable ALH */
2686#define DDRC_CTRL_RDC (1 << 2) /* 0 dclk clock frequency is lower than 60MHz
2687                        1 dclk clock frequency is higher than 60MHz */
2688#define DDRC_CTRL_CKE (1 << 1) /* 0 Not set CKE Pin High
2689                        1 Set CKE Pin HIGH */
2690#define DDRC_CTRL_RESET (1 << 0) /* 0 End resetting ddrc_controller
2691                        1 Resetting ddrc_controller */
2692
2693
2694/* DDRC Load-Mode-Register */
2695#define DDRC_LMR_DDR_ADDR_BIT 16 /* When performing a DDR command, DDRC_ADDR[13:0]
2696                          corresponding to external DDR address Pin A[13:0] */
2697#define DDRC_LMR_DDR_ADDR_MASK (0xff << DDRC_LMR_DDR_ADDR_BIT)
2698
2699#define DDRC_LMR_BA_BIT 8 /* When performing a DDR command, BA[2:0]
2700                     corresponding to external DDR address Pin BA[2:0]. */
2701#define DDRC_LMR_BA_MASK (0x7 << DDRC_LMR_BA_BIT)
2702  /* For DDR2 */
2703  #define DDRC_LMR_BA_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
2704  #define DDRC_LMR_BA_EMRS1 (1 << DDRC_LMR_BA_BIT) /* Extended Mode Register1 set */
2705  #define DDRC_LMR_BA_EMRS2 (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register2 set */
2706  #define DDRC_LMR_BA_EMRS3 (3 << DDRC_LMR_BA_BIT) /* Extended Mode Register3 set */
2707  /* For mobile DDR */
2708  #define DDRC_LMR_BA_M_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
2709  #define DDRC_LMR_BA_M_EMRS (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */
2710  #define DDRC_LMR_BA_M_SR (1 << DDRC_LMR_BA_BIT) /* Status Register set */
2711  /* For Normal DDR1 */
2712  #define DDRC_LMR_BA_N_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */
2713  #define DDRC_LMR_BA_N_EMRS (1 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */
2714
2715#define DDRC_LMR_CMD_BIT 4
2716#define DDRC_LMR_CMD_MASK (0x3 << DDRC_LMR_CMD_BIT)
2717  #define DDRC_LMR_CMD_PREC (0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */
2718  #define DDRC_LMR_CMD_AUREF (1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */
2719  #define DDRC_LMR_CMD_LMR (2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */
2720
2721#define DDRC_LMR_START (1 << 0) /* 0 No command is performed
2722                            1 On the posedge of START, perform a command
2723                            defined by CMD field */
2724
2725/* DDRC Mode Register Set */
2726#define DDR2_MRS_PD_BIT 10 /* Active power down exit time */
2727#define DDR2_MRS_PD_MASK (1 << DDR_MRS_PD_BIT)
2728  #define DDR2_MRS_PD_FAST_EXIT (0 << 10)
2729  #define DDR2_MRS_PD_SLOW_EXIT (1 << 10)
2730#define DDR2_MRS_WR_BIT 9 /* Write Recovery for autoprecharge */
2731#define DDR2_MRS_WR_MASK (7 << DDR_MRS_WR_BIT)
2732#define DDR2_MRS_DLL_RST (1 << 8) /* DLL Reset */
2733#define DDR2_MRS_TM_BIT 7 /* Operating Mode */
2734#define DDR2_MRS_TM_MASK (1 << DDR_MRS_TM_BIT)
2735  #define DDR2_MRS_TM_NORMAL (0 << DDR_MRS_TM_BIT)
2736  #define DDR2_MRS_TM_TEST (1 << DDR_MRS_TM_BIT)
2737#define DDR_MRS_CAS_BIT 4 /* CAS Latency */
2738#define DDR_MRS_CAS_MASK (7 << DDR_MRS_CAS_BIT)
2739#define DDR_MRS_BT_BIT 3 /* Burst Type */
2740#define DDR_MRS_BT_MASK (1 << DDR_MRS_BT_BIT)
2741  #define DDR_MRS_BT_SEQ (0 << DDR_MRS_BT_BIT) /* Sequential */
2742  #define DDR_MRS_BT_INT (1 << DDR_MRS_BT_BIT) /* Interleave */
2743#define DDR_MRS_BL_BIT 0 /* Burst Length */
2744#define DDR_MRS_BL_MASK (7 << DDR_MRS_BL_BIT)
2745  #define DDR_MRS_BL_4 (2 << DDR_MRS_BL_BIT)
2746  #define DDR_MRS_BL_8 (3 << DDR_MRS_BL_BIT)
2747
2748/* DDR2 Extended Mode Register1 Set */
2749#define DDR_EMRS1_QOFF (1<<12) /* 0 Output buffer enabled
2750                       1 Output buffer disabled */
2751#define DDR_EMRS1_RDQS_EN (1<<11) /* 0 Disable
2752                       1 Enable */
2753#define DDR_EMRS1_DQS_DIS (1<<10) /* 0 Enable
2754                       1 Disable */
2755#define DDR_EMRS1_OCD_BIT 7 /* Additive Latency 0 -> 6 */
2756#define DDR_EMRS1_OCD_MASK (0x7 << DDR_EMRS1_OCD_BIT)
2757  #define DDR_EMRS1_OCD_EXIT (0 << DDR_EMRS1_OCD_BIT)
2758  #define DDR_EMRS1_OCD_D0 (1 << DDR_EMRS1_OCD_BIT)
2759  #define DDR_EMRS1_OCD_D1 (2 << DDR_EMRS1_OCD_BIT)
2760  #define DDR_EMRS1_OCD_ADJ (4 << DDR_EMRS1_OCD_BIT)
2761  #define DDR_EMRS1_OCD_DFLT (7 << DDR_EMRS1_OCD_BIT)
2762#define DDR_EMRS1_AL_BIT 3 /* Additive Latency 0 -> 6 */
2763#define DDR_EMRS1_AL_MASK (7 << DDR_EMRS1_AL_BIT)
2764#define DDR_EMRS1_RTT_BIT 2 /* */
2765#define DDR_EMRS1_RTT_MASK (0x11 << DDR_EMRS1_DIC_BIT) /* Bit 6, Bit 2 */
2766#define DDR_EMRS1_DIC_BIT 1 /* Output Driver Impedence Control */
2767#define DDR_EMRS1_DIC_MASK (1 << DDR_EMRS1_DIC_BIT) /* 100% */
2768  #define DDR_EMRS1_DIC_NORMAL (0 << DDR_EMRS1_DIC_BIT) /* 60% */
2769  #define DDR_EMRS1_DIC_HALF (1 << DDR_EMRS1_DIC_BIT)
2770#define DDR_EMRS1_DLL_BIT 0 /* DLL Enable */
2771#define DDR_EMRS1_DLL_MASK (1 << DDR_EMRS1_DLL_BIT)
2772  #define DDR_EMRS1_DLL_EN (0 << DDR_EMRS1_DLL_BIT)
2773  #define DDR_EMRS1_DLL_DIS (1 << DDR_EMRS1_DLL_BIT)
2774
2775/* Mobile SDRAM Extended Mode Register */
2776#define DDR_EMRS_DS_BIT 5 /* Driver strength */
2777#define DDR_EMRS_DS_MASK (3 << DDR_EMRS_DS_BIT)
2778  #define DDR_EMRS_DS_FULL (0 << DDR_EMRS_DS_BIT) /*Full*/
2779  #define DDR_EMRS_DS_HALF (1 << DDR_EMRS_DS_BIT) /*1/2 Strength*/
2780  #define DDR_EMRS_DS_QUTR (2 << DDR_EMRS_DS_BIT) /*1/4 Strength*/
2781
2782#define DDR_EMRS_PRSR_BIT 0 /* Partial Array Self Refresh */
2783#define DDR_EMRS_PRSR_MASK (7 << DDR_EMRS_PRSR_BIT)
2784  #define DDR_EMRS_PRSR_ALL (0 << DDR_EMRS_PRSR_BIT) /*All Banks*/
2785  #define DDR_EMRS_PRSR_HALF_TL (1 << DDR_EMRS_PRSR_BIT) /*Half of Total Bank*/
2786  #define DDR_EMRS_PRSR_QUTR_TL (2 << DDR_EMRS_PRSR_BIT) /*Quarter of Total Bank*/
2787  #define DDR_EMRS_PRSR_HALF_B0 (5 << DDR_EMRS_PRSR_BIT) /*Half of Bank0*/
2788  #define DDR_EMRS_PRSR_QUTR_B0 (6 << DDR_EMRS_PRSR_BIT) /*Quarter of Bank0*/
2789
2790/* DDR1 Mode Register */
2791#define DDR1_MRS_OM_BIT 7 /* Operating Mode */
2792#define DDR1_MRS_OM_MASK (0x3f << DDR1_MRS_OM_BIT)
2793  #define DDR1_MRS_OM_NORMAL (0 << DDR1_MRS_OM_BIT)
2794  #define DDR1_MRS_OM_TEST (1 << DDR1_MRS_OM_BIT)
2795  #define DDR1_MRS_OM_DLLRST (2 << DDR1_MRS_OM_BIT)
2796#if 0
2797#define DDR1_MRS_CAS_BIT 4 /* CAS Latency */
2798#define DDR1_MRS_CAS_MASK (7 << DDR1_MRS_CAS_BIT)
2799#define DDR1_MRS_BT_BIT 3 /* Burst Type */
2800#define DDR1_MRS_BT_MASK (1 << DDR1_MRS_BT_BIT)
2801  #define DDR1_MRS_BT_SEQ (0 << DDR1_MRS_BT_BIT) /* Sequential */
2802  #define DDR1_MRS_BT_INT (1 << DDR1_MRS_BT_BIT) /* Interleave */
2803#define DDR1_MRS_BL_BIT 0 /* Burst Length */
2804#define DDR1_MRS_BL_MASK (7 << DDR1_MRS_BL_BIT)
2805  #define DDR1_MRS_BL_4 (2 << DDR1_MRS_BL_BIT)
2806  #define DDR1_MRS_BL_8 (3 << DDR1_MRS_BL_BIT)
2807#endif
2808/* DDR1 Extended Mode Register */
2809#define DDR1_EMRS_OM_BIT 2 /* Partial Array Self Refresh */
2810#define DDR1_EMRS_OM_MASK (0x3ff << DDR1_EMRS_OM_BIT)
2811  #define DDR1_EMRS_OM_NORMAL (0 << DDR1_EMRS_OM_BIT) /*All Banks*/
2812
2813#define DDR1_EMRS_DS_BIT 1 /* Driver strength */
2814#define DDR1_EMRS_DS_MASK (1 << DDR1_EMRS_DS_BIT)
2815  #define DDR1_EMRS_DS_FULL (0 << DDR1_EMRS_DS_BIT) /*Full*/
2816  #define DDR1_EMRS_DS_HALF (1 << DDR1_EMRS_DS_BIT) /*1/2 Strength*/
2817
2818#define DDR1_EMRS_DLL_BIT 0 /* Driver strength */
2819#define DDR1_EMRS_DLL_MASK (1 << DDR1_EMRS_DLL_BIT)
2820  #define DDR1_EMRS_DLL_EN (0 << DDR1_EMRS_DLL_BIT) /*Full*/
2821  #define DDR1_EMRS_DLL_DIS (1 << DDR1_EMRS_DLL_BIT) /*1/2 Strength*/
2822
2823/* DDRC Timing Config Register 1 */
2824#define DDRC_TIMING1_TRAS_BIT 28 /* ACTIVE to PRECHARGE command period (2 * tRAS + 1) */
2825#define DDRC_TIMING1_TRAS_MASK (0xf << DDRC_TIMING1_TRAS_BIT)
2826
2827#define DDRC_TIMING1_TRTP_BIT 24 /* READ to PRECHARGE command period. */
2828#define DDRC_TIMING1_TRTP_MASK (0x3 << DDRC_TIMING1_TRTP_BIT)
2829
2830#define DDRC_TIMING1_TRP_BIT 20 /* PRECHARGE command period. */
2831#define DDRC_TIMING1_TRP_MASK (0x7 << DDRC_TIMING1_TRP_BIT)
2832
2833#define DDRC_TIMING1_TRCD_BIT 16 /* ACTIVE to READ or WRITE command period. */
2834#define DDRC_TIMING1_TRCD_MASK (0x7 << DDRC_TIMING1_TRCD_BIT)
2835
2836#define DDRC_TIMING1_TRC_BIT 12 /* ACTIVE to ACTIVE command period. */
2837#define DDRC_TIMING1_TRC_MASK (0xf << DDRC_TIMING1_TRC_BIT)
2838
2839#define DDRC_TIMING1_TRRD_BIT 8 /* ACTIVE bank A to ACTIVE bank B command period. */
2840#define DDRC_TIMING1_TRRD_MASK (0x3 << DDRC_TIMING1_TRRD_BIT)
2841#define DDRC_TIMING1_TRRD_DISABLE (0 << DDRC_TIMING1_TRRD_BIT)
2842#define DDRC_TIMING1_TRRD_2 (1 << DDRC_TIMING1_TRRD_BIT)
2843#define DDRC_TIMING1_TRRD_3 (2 << DDRC_TIMING1_TRRD_BIT)
2844#define DDRC_TIMING1_TRRD_4 (3 << DDRC_TIMING1_TRRD_BIT)
2845
2846#define DDRC_TIMING1_TWR_BIT 4 /* WRITE Recovery Time defined by register MR of DDR2 memory */
2847#define DDRC_TIMING1_TWR_MASK (0x7 << DDRC_TIMING1_TWR_BIT)
2848  #define DDRC_TIMING1_TWR_1 (0 << DDRC_TIMING1_TWR_BIT)
2849  #define DDRC_TIMING1_TWR_2 (1 << DDRC_TIMING1_TWR_BIT)
2850  #define DDRC_TIMING1_TWR_3 (2 << DDRC_TIMING1_TWR_BIT)
2851  #define DDRC_TIMING1_TWR_4 (3 << DDRC_TIMING1_TWR_BIT)
2852  #define DDRC_TIMING1_TWR_5 (4 << DDRC_TIMING1_TWR_BIT)
2853  #define DDRC_TIMING1_TWR_6 (5 << DDRC_TIMING1_TWR_BIT)
2854
2855#define DDRC_TIMING1_TWTR_BIT 0 /* WRITE to READ command delay. */
2856#define DDRC_TIMING1_TWTR_MASK (0x3 << DDRC_TIMING1_TWTR_BIT)
2857  #define DDRC_TIMING1_TWTR_1 (0 << DDRC_TIMING1_TWTR_BIT)
2858  #define DDRC_TIMING1_TWTR_2 (1 << DDRC_TIMING1_TWTR_BIT)
2859  #define DDRC_TIMING1_TWTR_3 (2 << DDRC_TIMING1_TWTR_BIT)
2860  #define DDRC_TIMING1_TWTR_4 (3 << DDRC_TIMING1_TWTR_BIT)
2861
2862/* DDRC Timing Config Register 2 */
2863#define DDRC_TIMING2_TRFC_BIT 12 /* AUTO-REFRESH command period. */
2864#define DDRC_TIMING2_TRFC_MASK (0xf << DDRC_TIMING2_TRFC_BIT)
2865#define DDRC_TIMING2_TMINSR_BIT 8 /* Minimum Self-Refresh / Deep-Power-Down time */
2866#define DDRC_TIMING2_TMINSR_MASK (0xf << DDRC_TIMING2_TMINSR_BIT)
2867#define DDRC_TIMING2_TXP_BIT 4 /* EXIT-POWER-DOWN to next valid command period. */
2868#define DDRC_TIMING2_TXP_MASK (0x7 << DDRC_TIMING2_TXP_BIT)
2869#define DDRC_TIMING2_TMRD_BIT 0 /* Load-Mode-Register to next valid command period. */
2870#define DDRC_TIMING2_TMRD_MASK (0x3 << DDRC_TIMING2_TMRD_BIT)
2871
2872/* DDRC Auto-Refresh Counter */
2873#define DDRC_REFCNT_CON_BIT 16 /* Constant value used to compare with CNT value. */
2874#define DDRC_REFCNT_CON_MASK (0xff << DDRC_REFCNT_CON_BIT)
2875#define DDRC_REFCNT_CNT_BIT 8 /* 8-bit counter */
2876#define DDRC_REFCNT_CNT_MASK (0xff << DDRC_REFCNT_CNT_BIT)
2877#define DDRC_REFCNT_CLKDIV_BIT 1 /* Clock Divider for auto-refresh counter. */
2878#define DDRC_REFCNT_CLKDIV_MASK (0x7 << DDRC_REFCNT_CLKDIV_BIT)
2879#define DDRC_REFCNT_REF_EN (1 << 0) /* Enable Refresh Counter */
2880
2881/* DDRC DQS Delay Control Register */
2882#define DDRC_DQS_ERROR (1 << 29) /* ahb_clk Delay Detect ERROR, read-only. */
2883#define DDRC_DQS_READY (1 << 28) /* ahb_clk Delay Detect READY, read-only. */
2884#define DDRC_DQS_AUTO (1 << 23) /* Hardware auto-detect & set delay line */
2885#define DDRC_DQS_DET (1 << 24) /* Start delay detecting. */
2886#define DDRC_DQS_CLKD_BIT 16 /* CLKD is reference value for setting WDQS and RDQS.*/
2887#define DDRC_DQS_CLKD_MASK (0x7f << DDRC_DQS_CLKD_BIT)
2888#define DDRC_DQS_WDQS_BIT 8 /* Set delay element number to write DQS delay-line. */
2889#define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT)
2890#define DDRC_DQS_RDQS_BIT 0 /* Set delay element number to read DQS delay-line. */
2891#define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT)
2892
2893/* DDRC DQS Delay Adjust Register */
2894#define DDRC_DQS_ADJWDQS_BIT 8 /* The adjust value for WRITE DQS delay */
2895#define DDRC_DQS_ADJWDQS_MASK (0x1f << DDRC_DQS_ADJWDQS_BIT)
2896#define DDRC_DQS_ADJRDQS_BIT 0 /* The adjust value for READ DQS delay */
2897#define DDRC_DQS_ADJRDQS_MASK (0x1f << DDRC_DQS_ADJRDQS_BIT)
2898
2899/* DDRC Memory Map Config Register */
2900#define DDRC_MMAP_BASE_BIT 8 /* base address */
2901#define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT)
2902#define DDRC_MMAP_MASK_BIT 0 /* address mask */
2903#define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT)
2904
2905#define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT)
2906#define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
2907#define DDRC_MMAP1_BASE_128M (0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
2908#define DDRC_MMAP1_BASE_256M (0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/
2909
2910#define DDRC_MMAP_MASK_64_64 (0xfc << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/
2911#define DDRC_MMAP_MASK_128_128 (0xf8 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/
2912#define DDRC_MMAP_MASK_256_256 (0xf0 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/
2913
2914
2915
2916#define DDRC_MDELAY_MAUTO_BIT (6)
2917#define DDRC_MDELAY_MAUTO (1 << DDRC_MDELAY_MAUTO_BIT)
2918/*************************************************************************
2919 * CIM
2920 *************************************************************************/
2921#define CIM_CFG (CIM_BASE + 0x0000)
2922#define CIM_CTRL (CIM_BASE + 0x0004)
2923#define CIM_STATE (CIM_BASE + 0x0008)
2924#define CIM_IID (CIM_BASE + 0x000C)
2925#define CIM_RXFIFO (CIM_BASE + 0x0010)
2926#define CIM_DA (CIM_BASE + 0x0020)
2927#define CIM_FA (CIM_BASE + 0x0024)
2928#define CIM_FID (CIM_BASE + 0x0028)
2929#define CIM_CMD (CIM_BASE + 0x002C)
2930
2931#define REG_CIM_CFG REG32(CIM_CFG)
2932#define REG_CIM_CTRL REG32(CIM_CTRL)
2933#define REG_CIM_STATE REG32(CIM_STATE)
2934#define REG_CIM_IID REG32(CIM_IID)
2935#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
2936#define REG_CIM_DA REG32(CIM_DA)
2937#define REG_CIM_FA REG32(CIM_FA)
2938#define REG_CIM_FID REG32(CIM_FID)
2939#define REG_CIM_CMD REG32(CIM_CMD)
2940
2941/* CIM Configuration Register (CIM_CFG) */
2942
2943#define CIM_CFG_INV_DAT (1 << 15)
2944#define CIM_CFG_VSP (1 << 14)
2945#define CIM_CFG_HSP (1 << 13)
2946#define CIM_CFG_PCP (1 << 12)
2947#define CIM_CFG_DUMMY_ZERO (1 << 9)
2948#define CIM_CFG_EXT_VSYNC (1 << 8)
2949#define CIM_CFG_PACK_BIT 4
2950#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
2951  #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
2952  #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
2953  #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
2954  #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
2955  #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
2956  #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
2957  #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
2958  #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
2959#define CIM_CFG_DSM_BIT 0
2960#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
2961  #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
2962  #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
2963  #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
2964  #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
2965
2966/* CIM Control Register (CIM_CTRL) */
2967
2968#define CIM_CTRL_MCLKDIV_BIT 24
2969#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
2970#define CIM_CTRL_FRC_BIT 16
2971#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
2972  #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
2973  #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
2974  #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
2975  #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
2976  #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
2977  #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
2978  #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
2979  #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
2980  #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
2981  #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
2982  #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
2983  #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
2984  #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
2985  #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
2986  #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
2987  #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
2988#define CIM_CTRL_VDDM (1 << 13)
2989#define CIM_CTRL_DMA_SOFM (1 << 12)
2990#define CIM_CTRL_DMA_EOFM (1 << 11)
2991#define CIM_CTRL_DMA_STOPM (1 << 10)
2992#define CIM_CTRL_RXF_TRIGM (1 << 9)
2993#define CIM_CTRL_RXF_OFM (1 << 8)
2994#define CIM_CTRL_RXF_TRIG_BIT 4
2995#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
2996  #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
2997  #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
2998  #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
2999  #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
3000  #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
3001  #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
3002  #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
3003  #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
3004#define CIM_CTRL_DMA_EN (1 << 2)
3005#define CIM_CTRL_RXF_RST (1 << 1)
3006#define CIM_CTRL_ENA (1 << 0)
3007
3008/* CIM State Register (CIM_STATE) */
3009
3010#define CIM_STATE_DMA_SOF (1 << 6)
3011#define CIM_STATE_DMA_EOF (1 << 5)
3012#define CIM_STATE_DMA_STOP (1 << 4)
3013#define CIM_STATE_RXF_OF (1 << 3)
3014#define CIM_STATE_RXF_TRIG (1 << 2)
3015#define CIM_STATE_RXF_EMPTY (1 << 1)
3016#define CIM_STATE_VDD (1 << 0)
3017
3018/* CIM DMA Command Register (CIM_CMD) */
3019
3020#define CIM_CMD_SOFINT (1 << 31)
3021#define CIM_CMD_EOFINT (1 << 30)
3022#define CIM_CMD_STOP (1 << 28)
3023#define CIM_CMD_LEN_BIT 0
3024#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
3025
3026
3027/*************************************************************************
3028 * SADC (Smart A/D Controller)
3029 *************************************************************************/
3030
3031#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
3032#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
3033#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
3034#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
3035#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
3036#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
3037#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
3038#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
3039#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
3040
3041#define REG_SADC_ENA REG8(SADC_ENA)
3042#define REG_SADC_CFG REG32(SADC_CFG)
3043#define REG_SADC_CTRL REG8(SADC_CTRL)
3044#define REG_SADC_STATE REG8(SADC_STATE)
3045#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
3046#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
3047#define REG_SADC_TSDAT REG32(SADC_TSDAT)
3048#define REG_SADC_BATDAT REG16(SADC_BATDAT)
3049#define REG_SADC_SADDAT REG16(SADC_SADDAT)
3050
3051/* ADC Enable Register */
3052#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
3053#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
3054#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
3055#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
3056
3057/* ADC Configure Register */
3058#define SADC_CFG_CLKOUT_NUM_BIT 16
3059#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
3060#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
3061#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
3062#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
3063  #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
3064  #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
3065  #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
3066#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
3067#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
3068  #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
3069  #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
3070  #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
3071  #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
3072  #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
3073  #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
3074  #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
3075  #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
3076#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
3077#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
3078#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
3079#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
3080#define SADC_CFG_CMD_BIT 0 /* ADC Command */
3081#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
3082  #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
3083  #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
3084  #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
3085  #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
3086  #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
3087  #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
3088  #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
3089  #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
3090  #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
3091  #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
3092  #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
3093  #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
3094  #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
3095
3096/* ADC Control Register */
3097#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
3098#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
3099#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
3100#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
3101#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
3102
3103/* ADC Status Register */
3104#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
3105#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
3106#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
3107#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
3108#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
3109#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
3110#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
3111#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
3112
3113/* ADC Touch Screen Data Register */
3114#define SADC_TSDAT_DATA0_BIT 0
3115#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
3116#define SADC_TSDAT_TYPE0 (1 << 15)
3117#define SADC_TSDAT_DATA1_BIT 16
3118#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
3119#define SADC_TSDAT_TYPE1 (1 << 31)
3120
3121
3122/*************************************************************************
3123 * SLCD (Smart LCD Controller)
3124 *************************************************************************/
3125
3126#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
3127#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
3128#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
3129#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
3130
3131#define REG_SLCD_CFG REG32(SLCD_CFG)
3132#define REG_SLCD_CTRL REG8(SLCD_CTRL)
3133#define REG_SLCD_STATE REG8(SLCD_STATE)
3134#define REG_SLCD_DATA REG32(SLCD_DATA)
3135
3136/* SLCD Configure Register */
3137#define SLCD_CFG_BURST_BIT 14
3138#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
3139  #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
3140  #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
3141#define SLCD_CFG_DWIDTH_BIT 10
3142#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
3143  #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
3144  #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
3145  #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
3146  #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
3147  #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
3148#define SLCD_CFG_CWIDTH_16BIT (0 << 8)
3149#define SLCD_CFG_CWIDTH_8BIT (1 << 8)
3150#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
3151#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
3152#define SLCD_CFG_RS_CMD_LOW (0 << 3)
3153#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
3154#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
3155#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
3156#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
3157#define SLCD_CFG_TYPE_SERIAL (1 << 0)
3158
3159/* SLCD Control Register */
3160#define SLCD_CTRL_DMA_EN (1 << 0)
3161
3162/* SLCD Status Register */
3163#define SLCD_STATE_BUSY (1 << 0)
3164
3165/* SLCD Data Register */
3166#define SLCD_DATA_RS_DATA (0 << 31)
3167#define SLCD_DATA_RS_COMMAND (1 << 31)
3168
3169/*************************************************************************
3170 * LCD (LCD Controller)
3171 *************************************************************************/
3172#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
3173#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
3174#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
3175
3176#define LCD_OSDC (LCD_BASE + 0x100) /* LCD OSD Configure Register */
3177#define LCD_OSDCTRL (LCD_BASE + 0x104) /* LCD OSD Control Register */
3178#define LCD_OSDS (LCD_BASE + 0x108) /* LCD OSD Status Register */
3179#define LCD_BGC (LCD_BASE + 0x10C) /* LCD Background Color Register */
3180#define LCD_KEY0 (LCD_BASE + 0x110) /* LCD Foreground Color Key Register 0 */
3181#define LCD_KEY1 (LCD_BASE + 0x114) /* LCD Foreground Color Key Register 1 */
3182#define LCD_ALPHA (LCD_BASE + 0x118) /* LCD ALPHA Register */
3183#define LCD_IPUR (LCD_BASE + 0x11C) /* LCD IPU Restart Register */
3184
3185#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
3186#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
3187#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
3188
3189#define LCD_XYP0 (LCD_BASE + 0x120) /* Foreground 0 XY Position Register */
3190#define LCD_XYP1 (LCD_BASE + 0x124) /* Foreground 1 XY Position Register */
3191#define LCD_SIZE0 (LCD_BASE + 0x128) /* Foreground 0 Size Register */
3192#define LCD_SIZE1 (LCD_BASE + 0x12C) /* Foreground 1 Size Register */
3193#define LCD_RGBC (LCD_BASE + 0x90) /* RGB Controll Register */
3194
3195#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
3196#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
3197#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
3198#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
3199#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
3200#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
3201#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
3202#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
3203#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
3204#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
3205#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
3206#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
3207#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
3208#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
3209#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
3210
3211#define LCD_OFFS0 (LCD_BASE + 0x60) /* DMA Offsize Register 0 */
3212#define LCD_PW0 (LCD_BASE + 0x64) /* DMA Page Width Register 0 */
3213#define LCD_CNUM0 (LCD_BASE + 0x68) /* DMA Command Counter Register 0 */
3214#define LCD_DESSIZE0 (LCD_BASE + 0x6C) /* Foreground Size in Descriptor 0 Register*/
3215#define LCD_OFFS1 (LCD_BASE + 0x70) /* DMA Offsize Register 1 */
3216#define LCD_PW1 (LCD_BASE + 0x74) /* DMA Page Width Register 1 */
3217#define LCD_CNUM1 (LCD_BASE + 0x78) /* DMA Command Counter Register 1 */
3218#define LCD_DESSIZE1 (LCD_BASE + 0x7C) /* Foreground Size in Descriptor 1 Register*/
3219
3220#define REG_LCD_CFG REG32(LCD_CFG)
3221#define REG_LCD_CTRL REG32(LCD_CTRL)
3222#define REG_LCD_STATE REG32(LCD_STATE)
3223
3224#define REG_LCD_OSDC REG16(LCD_OSDC)
3225#define REG_LCD_OSDCTRL REG16(LCD_OSDCTRL)
3226#define REG_LCD_OSDS REG16(LCD_OSDS)
3227#define REG_LCD_BGC REG32(LCD_BGC)
3228#define REG_LCD_KEY0 REG32(LCD_KEY0)
3229#define REG_LCD_KEY1 REG32(LCD_KEY1)
3230#define REG_LCD_ALPHA REG8(LCD_ALPHA)
3231#define REG_LCD_IPUR REG32(LCD_IPUR)
3232
3233#define REG_LCD_VAT REG32(LCD_VAT)
3234#define REG_LCD_DAH REG32(LCD_DAH)
3235#define REG_LCD_DAV REG32(LCD_DAV)
3236
3237#define REG_LCD_XYP0 REG32(LCD_XYP0)
3238#define REG_LCD_XYP1 REG32(LCD_XYP1)
3239#define REG_LCD_SIZE0 REG32(LCD_SIZE0)
3240#define REG_LCD_SIZE1 REG32(LCD_SIZE1)
3241#define REG_LCD_RGBC REG16(LCD_RGBC)
3242
3243#define REG_LCD_VSYNC REG32(LCD_VSYNC)
3244#define REG_LCD_HSYNC REG32(LCD_HSYNC)
3245#define REG_LCD_PS REG32(LCD_PS)
3246#define REG_LCD_CLS REG32(LCD_CLS)
3247#define REG_LCD_SPL REG32(LCD_SPL)
3248#define REG_LCD_REV REG32(LCD_REV)
3249#define REG_LCD_IID REG32(LCD_IID)
3250#define REG_LCD_DA0 REG32(LCD_DA0)
3251#define REG_LCD_SA0 REG32(LCD_SA0)
3252#define REG_LCD_FID0 REG32(LCD_FID0)
3253#define REG_LCD_CMD0 REG32(LCD_CMD0)
3254#define REG_LCD_DA1 REG32(LCD_DA1)
3255#define REG_LCD_SA1 REG32(LCD_SA1)
3256#define REG_LCD_FID1 REG32(LCD_FID1)
3257#define REG_LCD_CMD1 REG32(LCD_CMD1)
3258
3259#define REG_LCD_OFFS0 REG32(LCD_OFFS0)
3260#define REG_LCD_PW0 REG32(LCD_PW0)
3261#define REG_LCD_CNUM0 REG32(LCD_CNUM0)
3262#define REG_LCD_DESSIZE0 REG32(LCD_DESSIZE0)
3263#define REG_LCD_OFFS1 REG32(LCD_OFFS1)
3264#define REG_LCD_PW1 REG32(LCD_PW1)
3265#define REG_LCD_CNUM1 REG32(LCD_CNUM1)
3266#define REG_LCD_DESSIZE1 REG32(LCD_DESSIZE1)
3267
3268/* LCD Configure Register */
3269#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
3270#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
3271  #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
3272  #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
3273#define LCD_CFG_TVEPEH (1 << 30) /* TVE PAL enable extra halfline signal */
3274#define LCD_CFG_FUHOLD (1 << 29) /* hold pixel clock when outFIFO underrun */
3275#define LCD_CFG_NEWDES (1 << 28) /* use new descripter. old: 4words, new:8words */
3276#define LCD_CFG_PALBP (1 << 27) /* bypass data format and alpha blending */
3277#define LCD_CFG_TVEN (1 << 26) /* indicate the terminal is lcd or tv */
3278#define LCD_CFG_RECOVER (1 << 25) /* Auto recover when output fifo underrun */
3279#define LCD_CFG_DITHER (1 << 24) /* Dither function */
3280#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
3281#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
3282#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
3283#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
3284#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
3285#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
3286#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
3287#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
3288#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
3289#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
3290#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
3291#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
3292#define LCD_CFG_HSP (1 << 11) /* HSYNC polarity:0-active high,1-active low */
3293#define LCD_CFG_PCP (1 << 10) /* PCLK polarity:0-rising,1-falling */
3294#define LCD_CFG_DEP (1 << 9) /* DE polarity:0-active high,1-active low */
3295#define LCD_CFG_VSP (1 << 8) /* VSYNC polarity:0-rising,1-falling */
3296#define LCD_CFG_MODE_TFT_18BIT (1 << 7) /* 18bit TFT */
3297#define LCD_CFG_MODE_TFT_16BIT (0 << 7) /* 16bit TFT */
3298#define LCD_CFG_MODE_TFT_24BIT (1 << 6) /* 24bit TFT */
3299#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
3300#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
3301#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
3302  #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
3303  #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
3304  #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
3305#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
3306#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
3307  #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
3308  #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
3309  #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
3310  #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
3311  #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
3312  #define LCD_CFG_MODE_INTER_CCIR656 (6 << LCD_CFG_MODE_BIT)
3313  #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
3314  #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
3315  #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
3316  #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
3317  #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
3318  #define LCD_CFG_MODE_LCM (13 << LCD_CFG_MODE_BIT)
3319  #define LCD_CFG_MODE_SLCD LCD_CFG_MODE_LCM
3320
3321/* LCD Control Register */
3322#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
3323#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
3324  #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
3325  #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
3326  #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
3327  #define LCD_CTRL_BST_32 (3 << LCD_CTRL_BST_BIT) /* 32-word */
3328#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode(foreground 0 in OSD mode) */
3329#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode(foreground 0 in OSD mode) */
3330#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
3331#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
3332#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
3333  #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
3334  #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
3335  #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
3336#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
3337#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
3338#define LCD_CTRL_VGA (1 << 15) /* VGA interface enable */
3339#define LCD_CTRL_DACTE (1 << 14) /* DAC loop back test */
3340#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
3341#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
3342#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
3343#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
3344#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
3345#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
3346#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
3347#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
3348#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
3349#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
3350#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
3351#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
3352#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
3353  #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
3354  #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
3355  #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
3356  #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
3357  #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
3358  #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
3359  #define LCD_CTRL_BPP_CMPS_24 (6 << LCD_CTRL_BPP_BIT) /* 24 compress bpp */
3360
3361/* LCD Status Register */
3362#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
3363#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
3364#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
3365#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
3366#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
3367#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
3368#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
3369
3370/* OSD Configure Register */
3371#define LCD_OSDC_SOFM1 (1 << 15) /* Start of frame interrupt mask for foreground 1 */
3372#define LCD_OSDC_EOFM1 (1 << 14) /* End of frame interrupt mask for foreground 1 */
3373#define LCD_OSDC_SOFM0 (1 << 11) /* Start of frame interrupt mask for foreground 0 */
3374#define LCD_OSDC_EOFM0 (1 << 10) /* End of frame interrupt mask for foreground 0 */
3375#define LCD_OSDC_F1EN (1 << 4) /* enable foreground 1 */
3376#define LCD_OSDC_F0EN (1 << 3) /* enable foreground 0 */
3377#define LCD_OSDC_ALPHAEN (1 << 2) /* enable alpha blending */
3378#define LCD_OSDC_ALPHAMD (1 << 1) /* alpha blending mode */
3379#define LCD_OSDC_OSDEN (1 << 0) /* OSD mode enable */
3380
3381/* OSD Controll Register */
3382#define LCD_OSDCTRL_IPU (1 << 15) /* input data from IPU */
3383#define LCD_OSDCTRL_RGB565 (0 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
3384#define LCD_OSDCTRL_RGB555 (1 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */
3385#define LCD_OSDCTRL_CHANGES (1 << 3) /* Change size flag */
3386#define LCD_OSDCTRL_OSDBPP_BIT 0 /* Bits Per Pixel of OSD Channel 1 */
3387#define LCD_OSDCTRL_OSDBPP_MASK (0x7<<LCD_OSDCTRL_OSDBPP_BIT) /* Bits Per Pixel of OSD Channel 1's MASK */
3388  #define LCD_OSDCTRL_OSDBPP_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
3389  #define LCD_OSDCTRL_OSDBPP_15_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/
3390  #define LCD_OSDCTRL_OSDBPP_18_24 (5 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/
3391  #define LCD_OSDCTRL_OSDBPP_CMPS_24 (6 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/
3392
3393/* OSD State Register */
3394#define LCD_OSDS_SOF1 (1 << 15) /* Start of frame flag for foreground 1 */
3395#define LCD_OSDS_EOF1 (1 << 14) /* End of frame flag for foreground 1 */
3396#define LCD_OSDS_SOF0 (1 << 11) /* Start of frame flag for foreground 0 */
3397#define LCD_OSDS_EOF0 (1 << 10) /* End of frame flag for foreground 0 */
3398#define LCD_OSDS_READY (1 << 0) /* Read for accept the change */
3399
3400/* Background Color Register */
3401#define LCD_BGC_RED_OFFSET (1 << 16) /* Red color offset */
3402#define LCD_BGC_RED_MASK (0xFF<<LCD_BGC_RED_OFFSET)
3403#define LCD_BGC_GREEN_OFFSET (1 << 8) /* Green color offset */
3404#define LCD_BGC_GREEN_MASK (0xFF<<LCD_BGC_GREEN_OFFSET)
3405#define LCD_BGC_BLUE_OFFSET (1 << 0) /* Blue color offset */
3406#define LCD_BGC_BLUE_MASK (0xFF<<LCD_BGC_BLUE_OFFSET)
3407
3408/* Foreground Color Key Register 0,1(foreground 0, foreground 1) */
3409#define LCD_KEY_KEYEN (1 << 31) /* enable color key */
3410#define LCD_KEY_KEYMD (1 << 30) /* color key mode */
3411#define LCD_KEY_RED_OFFSET 16 /* Red color offset */
3412#define LCD_KEY_RED_MASK (0xFF<<LCD_KEY_RED_OFFSET)
3413#define LCD_KEY_GREEN_OFFSET 8 /* Green color offset */
3414#define LCD_KEY_GREEN_MASK (0xFF<<LCD_KEY_GREEN_OFFSET)
3415#define LCD_KEY_BLUE_OFFSET 0 /* Blue color offset */
3416#define LCD_KEY_BLUE_MASK (0xFF<<LCD_KEY_BLUE_OFFSET)
3417#define LCD_KEY_MASK (LCD_KEY_RED_MASK|LCD_KEY_GREEN_MASK|LCD_KEY_BLUE_MASK)
3418
3419/* IPU Restart Register */
3420#define LCD_IPUR_IPUREN (1 << 31) /* IPU restart function enable*/
3421#define LCD_IPUR_IPURMASK (0xFFFFFF) /* IPU restart value mask*/
3422
3423/* RGB Control Register */
3424#define LCD_RGBC_RGBDM (1 << 15) /* enable RGB Dummy data */
3425#define LCD_RGBC_DMM (1 << 14) /* RGB Dummy mode */
3426#define LCD_RGBC_YCC (1 << 8) /* RGB to YCC */
3427#define LCD_RGBC_ODDRGB_BIT 4 /* odd line serial RGB data arrangement */
3428#define LCD_RGBC_ODDRGB_MASK (0x7<<LCD_RGBC_ODDRGB_BIT)
3429  #define LCD_RGBC_ODD_RGB 0
3430  #define LCD_RGBC_ODD_RBG 1
3431  #define LCD_RGBC_ODD_GRB 2
3432  #define LCD_RGBC_ODD_GBR 3
3433  #define LCD_RGBC_ODD_BRG 4
3434  #define LCD_RGBC_ODD_BGR 5
3435#define LCD_RGBC_EVENRGB_BIT 0 /* even line serial RGB data arrangement */
3436#define LCD_RGBC_EVENRGB_MASK (0x7<<LCD_RGBC_EVENRGB_BIT)
3437  #define LCD_RGBC_EVEN_RGB 0
3438  #define LCD_RGBC_EVEN_RBG 1
3439  #define LCD_RGBC_EVEN_GRB 2
3440  #define LCD_RGBC_EVEN_GBR 3
3441  #define LCD_RGBC_EVEN_BRG 4
3442  #define LCD_RGBC_EVEN_BGR 5
3443
3444/* Vertical Synchronize Register */
3445#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
3446#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
3447#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
3448#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
3449
3450/* Horizontal Synchronize Register */
3451#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
3452#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
3453#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
3454#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
3455
3456/* Virtual Area Setting Register */
3457#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
3458#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
3459#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
3460#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
3461
3462/* Display Area Horizontal Start/End Point Register */
3463#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
3464#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
3465#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
3466#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
3467
3468/* Display Area Vertical Start/End Point Register */
3469#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
3470#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
3471#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
3472#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
3473
3474/* Foreground XY Position Register */
3475#define LCD_XYP_YPOS_BIT 16 /* Y position bit of foreground 0 or 1 */
3476#define LCD_XYP_YPOS_MASK (0xffff << LCD_XYP_YPOS_BIT)
3477#define LCD_XYP_XPOS_BIT 0 /* X position bit of foreground 0 or 1 */
3478#define LCD_XYP_XPOS_MASK (0xffff << LCD_XYP_XPOS_BIT)
3479
3480/* PS Signal Setting */
3481#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
3482#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
3483#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
3484#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
3485
3486/* CLS Signal Setting */
3487#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
3488#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
3489#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
3490#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
3491
3492/* SPL Signal Setting */
3493#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
3494#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
3495#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
3496#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
3497
3498/* REV Signal Setting */
3499#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
3500#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
3501
3502/* DMA Command Register */
3503#define LCD_CMD_SOFINT (1 << 31)
3504#define LCD_CMD_EOFINT (1 << 30)
3505#define LCD_CMD_CMD (1 << 29) /* indicate command in slcd mode */
3506#define LCD_CMD_PAL (1 << 28)
3507#define LCD_CMD_LEN_BIT 0
3508#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
3509
3510/* DMA Offsize Register 0,1 */
3511
3512/* DMA Page Width Register 0,1 */
3513
3514/* DMA Command Counter Register 0,1 */
3515
3516/* Foreground 0,1 Size Register */
3517#define LCD_DESSIZE_HEIGHT_BIT 16 /* height of foreground 1 */
3518#define LCD_DESSIZE_HEIGHT_MASK (0xffff << LCD_DESSIZE_HEIGHT_BIT)
3519#define LCD_DESSIZE_WIDTH_BIT 0 /* width of foreground 1 */
3520#define LCD_DESSIZE_WIDTH_MASK (0xffff << LCD_DESSIZE_WIDTH_BIT)
3521
3522/*************************************************************************
3523 * TVE (TV Encoder Controller)
3524 *************************************************************************/
3525#define TVE_CTRL (TVE_BASE + 0x40) /* TV Encoder Control register */
3526#define TVE_FRCFG (TVE_BASE + 0x44) /* Frame configure register */
3527#define TVE_SLCFG1 (TVE_BASE + 0x50) /* TV signal level configure register 1 */
3528#define TVE_SLCFG2 (TVE_BASE + 0x54) /* TV signal level configure register 2*/
3529#define TVE_SLCFG3 (TVE_BASE + 0x58) /* TV signal level configure register 3*/
3530#define TVE_LTCFG1 (TVE_BASE + 0x60) /* Line timing configure register 1 */
3531#define TVE_LTCFG2 (TVE_BASE + 0x64) /* Line timing configure register 2 */
3532#define TVE_CFREQ (TVE_BASE + 0x70) /* Chrominance sub-carrier frequency configure register */
3533#define TVE_CPHASE (TVE_BASE + 0x74) /* Chrominance sub-carrier phase configure register */
3534#define TVE_CBCRCFG (TVE_BASE + 0x78) /* Chrominance filter configure register */
3535#define TVE_WSSCR (TVE_BASE + 0x80) /* Wide screen signal control register */
3536#define TVE_WSSCFG1 (TVE_BASE + 0x84) /* Wide screen signal configure register 1 */
3537#define TVE_WSSCFG2 (TVE_BASE + 0x88) /* Wide screen signal configure register 2 */
3538#define TVE_WSSCFG3 (TVE_BASE + 0x8c) /* Wide screen signal configure register 3 */
3539
3540#define REG_TVE_CTRL REG32(TVE_CTRL)
3541#define REG_TVE_FRCFG REG32(TVE_FRCFG)
3542#define REG_TVE_SLCFG1 REG32(TVE_SLCFG1)
3543#define REG_TVE_SLCFG2 REG32(TVE_SLCFG2)
3544#define REG_TVE_SLCFG3 REG32(TVE_SLCFG3)
3545#define REG_TVE_LTCFG1 REG32(TVE_LTCFG1)
3546#define REG_TVE_LTCFG2 REG32(TVE_LTCFG2)
3547#define REG_TVE_CFREQ REG32(TVE_CFREQ)
3548#define REG_TVE_CPHASE REG32(TVE_CPHASE)
3549#define REG_TVE_CBCRCFG REG32(TVE_CBCRCFG)
3550#define REG_TVE_WSSCR REG32(TVE_WSSCR)
3551#define REG_TVE_WSSCFG1 REG32(TVE_WSSCFG1)
3552#define REG_TVE_WSSCFG2 REG32(TVE_WSSCFG2)
3553#define REG_TVE_WSSCFG3 REG32(TVE_WSSCFG3)
3554
3555/* TV Encoder Control register */
3556#define TVE_CTRL_EYCBCR (1 << 25) /* YCbCr_enable */
3557#define TVE_CTRL_ECVBS (1 << 24) /* cvbs_enable */
3558#define TVE_CTRL_DAPD3 (1 << 23) /* DAC 3 power down */
3559#define TVE_CTRL_DAPD2 (1 << 22) /* DAC 2 power down */
3560#define TVE_CTRL_DAPD1 (1 << 21) /* DAC 1 power down */
3561#define TVE_CTRL_DAPD (1 << 20) /* power down all DACs */
3562#define TVE_CTRL_YCDLY_BIT 16
3563#define TVE_CTRL_YCDLY_MASK (0x7 << TVE_CTRL_YCDLY_BIT)
3564#define TVE_CTRL_CGAIN_BIT 14
3565#define TVE_CTRL_CGAIN_MASK (0x3 << TVE_CTRL_CGAIN_BIT)
3566  #define TVE_CTRL_CGAIN_FULL (0 << TVE_CTRL_CGAIN_BIT) /* gain = 1 */
3567  #define TVE_CTRL_CGAIN_QUTR (1 << TVE_CTRL_CGAIN_BIT) /* gain = 1/4 */
3568  #define TVE_CTRL_CGAIN_HALF (2 << TVE_CTRL_CGAIN_BIT) /* gain = 1/2 */
3569  #define TVE_CTRL_CGAIN_THREE_QURT (3 << TVE_CTRL_CGAIN_BIT) /* gain = 3/4 */
3570#define TVE_CTRL_CBW_BIT 12
3571#define TVE_CTRL_CBW_MASK (0x3 << TVE_CTRL_CBW_BIT)
3572  #define TVE_CTRL_CBW_NARROW (0 << TVE_CTRL_CBW_BIT) /* Narrow band */
3573  #define TVE_CTRL_CBW_WIDE (1 << TVE_CTRL_CBW_BIT) /* Wide band */
3574  #define TVE_CTRL_CBW_EXTRA (2 << TVE_CTRL_CBW_BIT) /* Extra wide band */
3575  #define TVE_CTRL_CBW_ULTRA (3 << TVE_CTRL_CBW_BIT) /* Ultra wide band */
3576#define TVE_CTRL_SYNCT (1 << 9)
3577#define TVE_CTRL_PAL (1 << 8)
3578#define TVE_CTRL_FINV (1 << 7) /* invert_top:1-invert top and bottom fields. */
3579#define TVE_CTRL_ZBLACK (1 << 6) /* bypass_yclamp:1-Black of luminance (Y) input is 0.*/
3580#define TVE_CTRL_CR1ST (1 << 5) /* uv_order:0-Cb before Cr,1-Cr before Cb */
3581#define TVE_CTRL_CLBAR (1 << 4) /* Color bar mode:0-Output input video to TV,1-Output color bar to TV */
3582#define TVE_CTRL_SWRST (1 << 0) /* Software reset:1-TVE is reset */
3583
3584/* Signal level configure register 1 */
3585#define TVE_SLCFG1_BLACKL_BIT 0
3586#define TVE_SLCFG1_BLACKL_MASK (0x3ff << TVE_SLCFG1_BLACKL_BIT)
3587#define TVE_SLCFG1_WHITEL_BIT 16
3588#define TVE_SLCFG1_WHITEL_MASK (0x3ff << TVE_SLCFG1_WHITEL_BIT)
3589
3590/* Signal level configure register 2 */
3591#define TVE_SLCFG2_BLANKL_BIT 0
3592#define TVE_SLCFG2_BLANKL_MASK (0x3ff << TVE_SLCFG2_BLANKL_BIT)
3593#define TVE_SLCFG2_VBLANKL_BIT 16
3594#define TVE_SLCFG2_VBLANKL_MASK (0x3ff << TVE_SLCFG2_VBLANKL_BIT)
3595
3596/* Signal level configure register 3 */
3597#define TVE_SLCFG3_SYNCL_BIT 0
3598#define TVE_SLCFG3_SYNCL_MASK (0xff << TVE_SLCFG3_SYNCL_BIT)
3599
3600/* Line timing configure register 1 */
3601#define TVE_LTCFG1_BACKP_BIT 0
3602#define TVE_LTCFG1_BACKP_MASK (0x7f << TVE_LTCFG1_BACKP_BIT)
3603#define TVE_LTCFG1_HSYNCW_BIT 8
3604#define TVE_LTCFG1_HSYNCW_MASK (0x7f << TVE_LTCFG1_HSYNCW_BIT)
3605#define TVE_LTCFG1_FRONTP_BIT 16
3606#define TVE_LTCFG1_FRONTP_MASK (0x1f << TVE_LTCFG1_FRONTP_BIT)
3607
3608/* Line timing configure register 2 */
3609#define TVE_LTCFG2_BURSTW_BIT 0
3610#define TVE_LTCFG2_BURSTW_MASK (0x3f << TVE_LTCFG2_BURSTW_BIT)
3611#define TVE_LTCFG2_PREBW_BIT 8
3612#define TVE_LTCFG2_PREBW_MASK (0x1f << TVE_LTCFG2_PREBW_BIT)
3613#define TVE_LTCFG2_ACTLIN_BIT 16
3614#define TVE_LTCFG2_ACTLIN_MASK (0x7ff << TVE_LTCFG2_ACTLIN_BIT)
3615
3616/* Chrominance sub-carrier phase configure register */
3617#define TVE_CPHASE_CCRSTP_BIT 0
3618#define TVE_CPHASE_CCRSTP_MASK (0x3 << TVE_CPHASE_CCRSTP_BIT)
3619  #define TVE_CPHASE_CCRSTP_8 (0 << TVE_CPHASE_CCRSTP_BIT) /* Every 8 field */
3620  #define TVE_CPHASE_CCRSTP_4 (1 << TVE_CPHASE_CCRSTP_BIT) /* Every 4 field */
3621  #define TVE_CPHASE_CCRSTP_2 (2 << TVE_CPHASE_CCRSTP_BIT) /* Every 2 lines */
3622  #define TVE_CPHASE_CCRSTP_0 (3 << TVE_CPHASE_CCRSTP_BIT) /* Never */
3623#define TVE_CPHASE_ACTPH_BIT 16
3624#define TVE_CPHASE_ACTPH_MASK (0xff << TVE_CPHASE_ACTPH_BIT)
3625#define TVE_CPHASE_INITPH_BIT 24
3626#define TVE_CPHASE_INITPH_MASK (0xff << TVE_CPHASE_INITPH_BIT)
3627
3628/* Chrominance filter configure register */
3629#define TVE_CBCRCFG_CRGAIN_BIT 0
3630#define TVE_CBCRCFG_CRGAIN_MASK (0xff << TVE_CBCRCFG_CRGAIN_BIT)
3631#define TVE_CBCRCFG_CBGAIN_BIT 8
3632#define TVE_CBCRCFG_CBGAIN_MASK (0xff << TVE_CBCRCFG_CBGAIN_BIT)
3633#define TVE_CBCRCFG_CRBA_BIT 16
3634#define TVE_CBCRCFG_CRBA_MASK (0xff << TVE_CBCRCFG_CRBA_BIT)
3635#define TVE_CBCRCFG_CBBA_BIT 24
3636#define TVE_CBCRCFG_CBBA_MASK (0xff << TVE_CBCRCFG_CBBA_BIT)
3637
3638/* Frame configure register */
3639#define TVE_FRCFG_NLINE_BIT 0
3640#define TVE_FRCFG_NLINE_MASK (0x3ff << TVE_FRCFG_NLINE_BIT)
3641#define TVE_FRCFG_L1ST_BIT 16
3642#define TVE_FRCFG_L1ST_MASK (0xff << TVE_FRCFG_L1ST_BIT)
3643
3644/* Wide screen signal control register */
3645#define TVE_WSSCR_EWSS0_BIT 0
3646#define TVE_WSSCR_EWSS1_BIT 1
3647#define TVE_WSSCR_WSSTP_BIT 2
3648#define TVE_WSSCR_WSSCKBP_BIT 3
3649#define TVE_WSSCR_WSSEDGE_BIT 4
3650#define TVE_WSSCR_WSSEDGE_MASK (0x7 << TVE_WSSCR_WSSEDGE_BIT)
3651#define TVE_WSSCR_ENCH_BIT 8
3652#define TVE_WSSCR_NCHW_BIT 9
3653#define TVE_WSSCR_NCHFREQ_BIT 12
3654#define TVE_WSSCR_NCHFREQ_MASK (0x7 << TVE_WSSCR_NCHFREQ_BIT)
3655
3656
3657/*************************************************************************
3658 * USB Device
3659 *************************************************************************/
3660#define USB_BASE UDC_BASE
3661
3662#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
3663#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
3664#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
3665#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
3666#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
3667#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
3668#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
3669#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
3670#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
3671#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
3672#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
3673
3674#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
3675#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
3676#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
3677#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
3678#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
3679#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
3680#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
3681#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
3682
3683#define USB_FIFO_EP0 (USB_BASE + 0x20)
3684#define USB_FIFO_EP1 (USB_BASE + 0x24)
3685#define USB_FIFO_EP2 (USB_BASE + 0x28)
3686
3687#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
3688#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
3689
3690#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
3691#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
3692#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
3693#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
3694#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
3695#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
3696#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
3697
3698
3699/* Power register bit masks */
3700#define USB_POWER_SUSPENDM 0x01
3701#define USB_POWER_RESUME 0x04
3702#define USB_POWER_HSMODE 0x10
3703#define USB_POWER_HSENAB 0x20
3704#define USB_POWER_SOFTCONN 0x40
3705
3706/* Interrupt register bit masks */
3707#define USB_INTR_SUSPEND 0x01
3708#define USB_INTR_RESUME 0x02
3709#define USB_INTR_RESET 0x04
3710
3711#define USB_INTR_EP0 0x0001
3712#define USB_INTR_INEP1 0x0002
3713#define USB_INTR_INEP2 0x0004
3714#define USB_INTR_OUTEP1 0x0002
3715
3716/* CSR0 bit masks */
3717#define USB_CSR0_OUTPKTRDY 0x01
3718#define USB_CSR0_INPKTRDY 0x02
3719#define USB_CSR0_SENTSTALL 0x04
3720#define USB_CSR0_DATAEND 0x08
3721#define USB_CSR0_SETUPEND 0x10
3722#define USB_CSR0_SENDSTALL 0x20
3723#define USB_CSR0_SVDOUTPKTRDY 0x40
3724#define USB_CSR0_SVDSETUPEND 0x80
3725
3726/* Endpoint CSR register bits */
3727#define USB_INCSRH_AUTOSET 0x80
3728#define USB_INCSRH_ISO 0x40
3729#define USB_INCSRH_MODE 0x20
3730#define USB_INCSRH_DMAREQENAB 0x10
3731#define USB_INCSRH_DMAREQMODE 0x04
3732#define USB_INCSR_CDT 0x40
3733#define USB_INCSR_SENTSTALL 0x20
3734#define USB_INCSR_SENDSTALL 0x10
3735#define USB_INCSR_FF 0x08
3736#define USB_INCSR_UNDERRUN 0x04
3737#define USB_INCSR_FFNOTEMPT 0x02
3738#define USB_INCSR_INPKTRDY 0x01
3739#define USB_OUTCSRH_AUTOCLR 0x80
3740#define USB_OUTCSRH_ISO 0x40
3741#define USB_OUTCSRH_DMAREQENAB 0x20
3742#define USB_OUTCSRH_DNYT 0x10
3743#define USB_OUTCSRH_DMAREQMODE 0x08
3744#define USB_OUTCSR_CDT 0x80
3745#define USB_OUTCSR_SENTSTALL 0x40
3746#define USB_OUTCSR_SENDSTALL 0x20
3747#define USB_OUTCSR_FF 0x10
3748#define USB_OUTCSR_DATAERR 0x08
3749#define USB_OUTCSR_OVERRUN 0x04
3750#define USB_OUTCSR_FFFULL 0x02
3751#define USB_OUTCSR_OUTPKTRDY 0x01
3752
3753/* Testmode register bits */
3754#define USB_TEST_SE0NAK 0x01
3755#define USB_TEST_J 0x02
3756#define USB_TEST_K 0x04
3757#define USB_TEST_PACKET 0x08
3758
3759/* DMA control bits */
3760#define USB_CNTL_ENA 0x01
3761#define USB_CNTL_DIR_IN 0x02
3762#define USB_CNTL_MODE_1 0x04
3763#define USB_CNTL_INTR_EN 0x08
3764#define USB_CNTL_EP(n) ((n) << 4)
3765#define USB_CNTL_BURST_0 (0 << 9)
3766#define USB_CNTL_BURST_4 (1 << 9)
3767#define USB_CNTL_BURST_8 (2 << 9)
3768#define USB_CNTL_BURST_16 (3 << 9)
3769
3770/*************************************************************************
3771 * BCH
3772 *************************************************************************/
3773#define BCH_CR (BCH_BASE + 0x00) /* BCH Control register */
3774#define BCH_CRS (BCH_BASE + 0x04) /* BCH Control Set register */
3775#define BCH_CRC (BCH_BASE + 0x08) /* BCH Control Clear register */
3776#define BCH_CNT (BCH_BASE + 0x0C) /* BCH ENC/DEC Count register */
3777#define BCH_DR (BCH_BASE + 0x10) /* BCH data register */
3778#define BCH_PAR0 (BCH_BASE + 0x14) /* BCH Parity 0 register */
3779#define BCH_PAR1 (BCH_BASE + 0x18) /* BCH Parity 1 register */
3780#define BCH_PAR2 (BCH_BASE + 0x1C) /* BCH Parity 2 register */
3781#define BCH_PAR3 (BCH_BASE + 0x20) /* BCH Parity 3 register */
3782#define BCH_PAR4 (BCH_BASE + 0x24) /* BCH Parity 4 register */
3783#define BCH_PAR5 (BCH_BASE + 0x28) /* BCH Parity 5 register */
3784#define BCH_PAR6 (BCH_BASE + 0x2C) /* BCH Parity 6 register */
3785#define BCH_PAR7 (BCH_BASE + 0x30) /* BCH Parity 7 register */
3786#define BCH_PAR8 (BCH_BASE + 0x34) /* BCH Parity 8 register */
3787#define BCH_PAR9 (BCH_BASE + 0x38) /* BCH Parity 9 register */
3788#define BCH_ERR0 (BCH_BASE + 0x3C) /* BCH Error Report 0 register */
3789#define BCH_ERR1 (BCH_BASE + 0x40) /* BCH Error Report 1 register */
3790#define BCH_ERR2 (BCH_BASE + 0x44) /* BCH Error Report 2 register */
3791#define BCH_ERR3 (BCH_BASE + 0x48) /* BCH Error Report 3 register */
3792#define BCH_ERR4 (BCH_BASE + 0x4C) /* BCH Error Report 4 register */
3793#define BCH_ERR5 (BCH_BASE + 0x50) /* BCH Error Report 5 register */
3794#define BCH_ERR6 (BCH_BASE + 0x54) /* BCH Error Report 6 register */
3795#define BCH_ERR7 (BCH_BASE + 0x58) /* BCH Error Report 7 register */
3796#define BCH_ERR8 (BCH_BASE + 0x5C) /* BCH Error Report 8 register */
3797#define BCH_ERR9 (BCH_BASE + 0x60) /* BCH Error Report 9 register */
3798#define BCH_ERR10 (BCH_BASE + 0x64) /* BCH Error Report 10 register */
3799#define BCH_ERR11 (BCH_BASE + 0x68) /* BCH Error Report 11 register */
3800#define BCH_INTS (BCH_BASE + 0x6C) /* BCH Interrupt Status register */
3801#define BCH_INTE (BCH_BASE + 0x70) /* BCH Interrupt Enable register */
3802#define BCH_INTES (BCH_BASE + 0x74) /* BCH Interrupt Set register */
3803#define BCH_INTEC (BCH_BASE + 0x78) /* BCH Interrupt Clear register */
3804
3805#define REG_BCH_CR REG32(BCH_CR)
3806#define REG_BCH_CRS REG32(BCH_CRS)
3807#define REG_BCH_CRC REG32(BCH_CRC)
3808#define REG_BCH_CNT REG32(BCH_CNT)
3809#define REG_BCH_DR REG8(BCH_DR)
3810#define REG_BCH_PAR0 REG32(BCH_PAR0)
3811#define REG_BCH_PAR1 REG32(BCH_PAR1)
3812#define REG_BCH_PAR2 REG32(BCH_PAR2)
3813#define REG_BCH_PAR3 REG32(BCH_PAR3)
3814#define REG_BCH_PAR4 REG32(BCH_PAR4)
3815#define REG_BCH_PAR5 REG32(BCH_PAR5)
3816#define REG_BCH_PAR6 REG32(BCH_PAR6)
3817#define REG_BCH_PAR7 REG32(BCH_PAR7)
3818#define REG_BCH_PAR8 REG32(BCH_PAR8)
3819#define REG_BCH_PAR9 REG32(BCH_PAR9)
3820#define REG_BCH_ERR0 REG32(BCH_ERR0)
3821#define REG_BCH_ERR1 REG32(BCH_ERR1)
3822#define REG_BCH_ERR2 REG32(BCH_ERR2)
3823#define REG_BCH_ERR3 REG32(BCH_ERR3)
3824#define REG_BCH_ERR4 REG32(BCH_ERR4)
3825#define REG_BCH_ERR5 REG32(BCH_ERR5)
3826#define REG_BCH_ERR6 REG32(BCH_ERR6)
3827#define REG_BCH_ERR7 REG32(BCH_ERR7)
3828#define REG_BCH_ERR8 REG32(BCH_ERR8)
3829#define REG_BCH_ERR9 REG32(BCH_ERR9)
3830#define REG_BCH_ERR10 REG32(BCH_ERR10)
3831#define REG_BCH_ERR11 REG32(BCH_ERR11)
3832#define REG_BCH_INTS REG32(BCH_INTS)
3833#define REG_BCH_INTE REG32(BCH_INTE)
3834#define REG_BCH_INTEC REG32(BCH_INTEC)
3835#define REG_BCH_INTES REG32(BCH_INTES)
3836
3837/* BCH Control Register*/
3838#define BCH_CR_DMAE (1 << 7) /* BCH DMA Enable */
3839#define BCH_CR_BSEL_BIT 3
3840#define BCH_CR_BSEL_MASK (0x3 << BCH_CR_BSEL_BIT)
3841  #define BCH_CR_BSEL_4 (0x0 << BCH_CR_BSEL_BIT) /* 4 Bit BCH Select */
3842  #define BCH_CR_BSEL_8 (0x1 << BCH_CR_BSEL_BIT) /* 8 Bit BCH Select */
3843  #define BCH_CR_BSEL_12 (0x2 << BCH_CR_BSEL_BIT) /* 12 Bit BCH Select */
3844  #define BCH_CR_BSEL_16 (0x3 << BCH_CR_BSEL_BIT) /* 16 Bit BCH Select */
3845  #define BCH_CR_BSEL_20 (0x4 << BCH_CR_BSEL_BIT) /* 20 Bit BCH Select */
3846  #define BCH_CR_BSEL_24 (0x5 << BCH_CR_BSEL_BIT) /* 24 Bit BCH Select */
3847#define BCH_CR_ENCE (1 << 2) /* BCH Encoding Select */
3848#define BCH_CR_DECE (0 << 2) /* BCH Decoding Select */
3849#define BCH_CR_BRST (1 << 1) /* BCH Reset */
3850#define BCH_CR_BCHE (1 << 0) /* BCH Enable */
3851
3852/* BCH Interrupt Status Register */
3853#define BCH_INTS_ERRC_BIT 27
3854#define BCH_INTS_ERRC_MASK (0x1f << BCH_INTS_ERRC_BIT)
3855#define BCH_INTS_ALLf (1 << 4)
3856#define BCH_INTS_DECF (1 << 3)
3857#define BCH_INTS_ENCF (1 << 2)
3858#define BCH_INTS_UNCOR (1 << 1)
3859#define BCH_INTS_ERR (1 << 0)
3860
3861/* BCH ENC/DEC Count Register */
3862#define BCH_CNT_DEC_BIT 16
3863#define BCH_CNT_DEC_MASK (0x7ff << BCH_CNT_DEC_BIT)
3864#define BCH_CNT_ENC_BIT 0
3865#define BCH_CNT_ENC_MASK (0x7ff << BCH_CNT_ENC_BIT)
3866
3867/* BCH Error Report Register */
3868#define BCH_ERR_INDEX_ODD_BIT 0
3869#define BCH_ERR_INDEX_ODD_MASK (0x1fff << BCH_ERR_INDEX_ODD_BIT)
3870#define BCH_ERR_INDEX_EVEN_BIT 16
3871#define BCH_ERR_INDEX_EVEN_MASK (0x1fff << BCH_ERR_INDEX_EVEN_BIT)
3872
3873//----------------------------------------------------------------------
3874//
3875// Module Operation Definitions
3876//
3877//----------------------------------------------------------------------
3878#ifndef __ASSEMBLY__
3879
3880#define is_share_mode() (1)
3881
3882/***************************************************************************
3883 * GPIO
3884 ***************************************************************************/
3885
3886//------------------------------------------------------
3887// GPIO Pins Description
3888//
3889// PORT 0:
3890//
3891// PIN/BIT N FUNC0 FUNC1 FUNC2 NOTE
3892// 0 SD0 - -
3893// 1 SD1 - -
3894// 2 SD2 - -
3895// 3 SD3 - -
3896// 4 SD4 - -
3897// 5 SD5 - -
3898// 6 SD6 - -
3899// 7 SD7 - -
3900// 8 SD8 - -
3901// 9 SD9 - -
3902// 10 SD10 - -
3903// 11 SD11 - -
3904// 12 SD12 - -
3905// 13 SD13 - -
3906// 14 SD14 - -
3907// 15 SD15 - -
3908// 16 RD_ - -
3909// 17 WE_ - -
3910// 18 FRE_ MSC0_CLK SSI0_CLK
3911// 19 FWE_ MSC0_CMD SSI0_CE0_
3912// 20 MSC0_D0 SSI0_DR - 1
3913// 21 CS1_ MSC0_D1 SSI0_DT
3914// 22 CS2_ MSC0_D2 -
3915// 23 CS3_ - -
3916// 24 CS4_ - -
3917// 25 CS5_ - -
3918// 26 CS6_ - -
3919// 27 WAIT_ - -
3920// 28 DREQ0 - -
3921// 29 DACK0 OWI -
3922// 30 - - - 6
3923// 31 - - - 7
3924
3925//Note1. PA20: GPIO group A bit 20. If NAND flash is used, this pin must be used as NAND FRB. (NAND flash ready/busy)
3926//Note6. PA30: GPIO group A bit 30 can only be used as input and interrupt, no pull-up and pull-down.
3927//Note7. PA31: GPIO group A bit 31. No corresponding pin exists for this GPIO. It is only used to select the function between UART and JTAG, which share the same set of pins, by using register PASEL [31]
3928// When PASEL [31]=0, select JTAG function.
3929// When PASEL [31]=1, select UART function
3930
3931//------------------------------------------------------
3932// PORT 1:
3933//
3934// PIN/BIT N FUNC0 FUNC1 FUNC2 NOTE
3935// 0 SA0 - -
3936// 1 SA1 - -
3937// 2 SA2 - - CL
3938// 3 SA3 - - AL
3939// 4 SA4 - -
3940// 5 SA5 - -
3941// 6 CIM_PCLK TSCLK -
3942// 7 CIM_HSYN TSFRM -
3943// 8 CIM_VSYN TSSTR -
3944// 9 CIM_MCLK TSFAIL -
3945// 10 CIM_D0 TSDI0 -
3946// 11 CIM_D1 TSDI1 -
3947// 12 CIM_D2 TSDI2 -
3948// 13 CIM_D3 TSDI3 -
3949// 14 CIM_D4 TSDI4 -
3950// 15 CIM_D5 TSDI5 -
3951// 16 CIM_D6 TSDI6 -
3952// 17 CIM_D7 TSDI7 -
3953// 18 - - -
3954// 19 - - -
3955// 20 MSC2_D0 SSI2_DR TSDI0
3956// 21 MSC2_D1 SSI2_DT TSDI1
3957// 22 TSDI2 - -
3958// 23 TSDI3 - -
3959// 24 TSDI4 - -
3960// 25 TSDI5 - -
3961// 26 TSDI6 - -
3962// 27 TSDI7 - -
3963// 28 MSC2_CLK SSI2_CLK TSCLK
3964// 29 MSC2_CMD SSI2_CE0_ TSSTR
3965// 30 MSC2_D2 SSI2_GPC TSFAIL
3966// 31 MSC2_D3 SSI2_CE1_ TSFRM
3967
3968//------------------------------------------------------
3969// PORT 2:
3970// PIN/BIT N FUNC0 FUNC1 FUNC2 FUNC3 NOTE
3971// 0 LCD_B0 (O) LCD_REV (O) - -
3972// 1 LCD_B1 (O) LCD_PS (O) - -
3973// 2 LCD_B2 (O) - - -
3974// 3 LCD_B3 (O) - - -
3975// 4 LCD_B4 (O) - - -
3976// 5 LCD_B5 (O) - - -
3977// 6 LCD_B6 (O) - - -
3978// 7 LCD_B7 (O) - - -
3979// 8 LCD_PCLK (O) - - -
3980// 9 LCD_DE (O) - - -
3981// 10 LCD_G0 (O) LCD_SPL (O) - -
3982// 11 LCD_G1 (O) - - -
3983// 12 LCD_G2 (O) - - -
3984// 13 LCD_G3 (O) - - -
3985// 14 LCD_G4 (O) - - -
3986// 15 LCD_G5 (O) - - -
3987// 16 LCD_G6 (O) - - -
3988// 17 LCD_G7 (O) - - -
3989// 18 LCD_HSYN (IO) - - -
3990// 19 LCD_VSYN (IO) - - -
3991// 20 LCD_R0 (O) LCD_CLS (O) - -
3992// 21 LCD_R1 (O) - - -
3993// 22 LCD_R2 (O) - - -
3994// 23 LCD_R3 (O) - - -
3995// 24 LCD_R4 (O) - - -
3996// 25 LCD_R5 (O) - - -
3997// 26 LCD_R6 (O) - - -
3998// 27 LCD_R7 (O) - - -
3999// 28 UART2_RxD (I) - - -
4000// 29 UART2_CTS_ (I) - - -
4001// 30 UART2_TxD (O) - - -
4002// 31 UART2_RTS_ (O) - - -
4003
4004//------------------------------------------------------
4005// PORT 3:
4006//
4007// PIN/BIT N FUNC0 FUNC1 FUNC2 FUNC3 NOTE
4008// 0 MII_TXD0 - - -
4009// 1 MII_TXD1 - - -
4010// 2 MII_TXD2 - - -
4011// 3 MII_TXD3 - - -
4012// 4 MII_TXEN - - -
4013// 5 MII_TXCLK(RMII_CLK) - - -
4014// 6 MII_COL - - -
4015// 7 MII_RXER - - -
4016// 8 MII_RXDV - - -
4017// 9 MII_RXCLK - - -
4018// 10 MII_RXD0 - - -
4019// 11 MII_RXD1 - - -
4020// 12 MII_RXD2 - - -
4021// 13 MII_RXD3 - - -
4022// 14 MII_CRS - - -
4023// 15 MII_MDC - - -
4024// 16 MII_MDIO - - -
4025// 17 BOOT_SEL0 - - - Note2,5
4026// 18 BOOT_SEL1 - - - Note3,5
4027// 19 BOOT_SEL2 - - - Note4,5
4028// 20 MSC1_D0 SSI1_DR - -
4029// 21 MSC1_D1 SSI1_DT - -
4030// 22 MSC1_D2 SSI1_GPC - -
4031// 23 MSC1_D3 SSI1_CE1_ - -
4032// 24 MSC1_CLK SSI1_CLK - -
4033// 25 MSC1_CMD SSI1_CE0_ - -
4034// 26 UART1_RxD - - -
4035// 27 UART1_CTS_ - - -
4036// 28 UART1_TxD - - -
4037// 29 UART1_RTS_ - - -
4038// 30 I2C0_SDA - - -
4039// 31 I2C0_SCK - - -
4040//
4041// Note2. PD17: GPIO group D bit 17 is used as BOOT_SEL0 input during boot.
4042// Note3. PD18: GPIO group D bit 18 is used as BOOT_SEL1 input during boot.
4043// Note4. PD19: GPIO group D bit 19 is used as BOOT_SEL2 input during boot.
4044// Note5. BOOT_SEL2, BOOT_SEL1, BOOT_SEL0 are used to select boot source and function during the processor boot.
4045//
4046//------------------------------------------------------
4047// PORT 4:
4048//
4049// PIN/BIT N FUNC0 FUNC1 FUNC2 FUNC3 NOTE
4050// 0 PWM0 - - -
4051// 1 PWM1 - - -
4052// 2 PWM2 SYNC - -
4053// 3 PWM3 UART3_RxD BCLK -
4054// 4 PWM4 - - -
4055// 5 PWM5 UART3_TxD SCLK_RSTN -
4056// 6 SDATI - - -
4057// 7 SDATO - - -
4058// 8 UART3_CTS_ - - -
4059// 9 UART3_RTS_ - - -
4060// 10 - - - -
4061// 11 SDATO1 - - -
4062// 12 SDATO2 - - -
4063// 13 SDATO3 - - -
4064// 14 SSI0_DR SSI1_DR SSI2_DR -
4065// 15 SSI0_CLK SI1_CLK SSI2_CLK -
4066// 16 SSI0_CE0_ SI1_CE0_ SSI2_CE0_ -
4067// 17 SSI0_DT SSI1_DT SSI2_DT -
4068// 18 SSI0_CE1_ SSI1_CE1_ SSI2_CE1_ -
4069// 19 SSI0_GPC SSI1_GPC SSI2_GPC -
4070// 20 MSC0_D0 MSC1_D0 MSC2_D0 -
4071// 21 MSC0_D1 MSC1_D1 MSC2_D1 -
4072// 22 MSC0_D2 MSC1_D2 MSC2_D2 -
4073// 23 MSC0_D3 MSC1_D3 MSC2_D3 -
4074// 24 MSC0_CLK MSC1_CLK MSC2_CLK -
4075// 25 MSC0_CMD MSC1_CMD MSC2_CMD -
4076// 26 MSC0_D4 MSC0_D4 MSC0_D4 PS2_MCLK
4077// 27 MSC0_D5 MSC0_D5 MSC0_D5 PS2_MDATA
4078// 28 MSC0_D6 MSC0_D6 MSC0_D6 PS2_KCLK
4079// 29 MSC0_D7 MSC0_D7 MSC0_D7 PS2_KDATA
4080// 30 I2C1_SDA SCC_DATA - -
4081// 31 I2C1_SCK SCC_CLK - -
4082//
4083//------------------------------------------------------
4084// PORT 5:
4085//
4086// PIN/BIT N FUNC0 FUNC1 FUNC2 FUNC3 NOTE
4087// 0 UART0_RxD GPS_CLK - -
4088// 1 UART0_CTS_ GPS_MAG - -
4089// 2 UART0_TxD GPS_SIG - -
4090// 3 UART0_RTS_ - - -
4091//
4092//////////////////////////////////////////////////////////
4093
4094/*----------------------------------------------------------------
4095 * p is the port number (0,1,2,3,4,5)
4096 * o is the pin offset (0-31) inside the port
4097 * n is the absolute number of a pin (0-127), regardless of the port
4098 */
4099
4100//----------------------------------------------------------------
4101// Function Pins Mode
4102
4103#define __gpio_as_func0(n) \
4104do { \
4105    unsigned int p, o; \
4106    p = (n) / 32; \
4107    o = (n) % 32; \
4108    REG_GPIO_PXFUNS(p) = (1 << o); \
4109    REG_GPIO_PXTRGC(p) = (1 << o); \
4110    REG_GPIO_PXSELC(p) = (1 << o); \
4111} while (0)
4112
4113#define __gpio_as_func1(n) \
4114do { \
4115    unsigned int p, o; \
4116    p = (n) / 32; \
4117    o = (n) % 32; \
4118    REG_GPIO_PXFUNS(p) = (1 << o); \
4119    REG_GPIO_PXTRGC(p) = (1 << o); \
4120    REG_GPIO_PXSELS(p) = (1 << o); \
4121} while (0)
4122
4123#define __gpio_as_func2(n) \
4124do { \
4125    unsigned int p, o; \
4126    p = (n) / 32; \
4127    o = (n) % 32; \
4128    REG_GPIO_PXFUNS(p) = (1 << o); \
4129    REG_GPIO_PXTRGS(p) = (1 << o); \
4130    REG_GPIO_PXSELC(p) = (1 << o); \
4131} while (0)
4132
4133#define __gpio_as_func3(n) \
4134do { \
4135    unsigned int p, o; \
4136    p = (n) / 32; \
4137    o = (n) % 32; \
4138    REG_GPIO_PXFUNS(p) = (1 << o); \
4139    REG_GPIO_PXTRGS(p) = (1 << o); \
4140    REG_GPIO_PXSELS(p) = (1 << o); \
4141} while (0)
4142
4143
4144/*
4145 * MII_TXD0- D3 MII_TXEN MII_TXCLK MII_COL
4146 * MII_RXER MII_RXDV MII_RXCLK MII_RXD0 - D3
4147 * MII_CRS MII_MDC MII_MDIO
4148 */
4149
4150#define __gpio_as_eth() \
4151do { \
4152    REG_GPIO_PXFUNS(3) = 0x0001ffff; \
4153    REG_GPIO_PXTRGC(3) = 0x0001ffff; \
4154    REG_GPIO_PXSELC(3) = 0x0001ffff; \
4155    REG_GPIO_PXPES(3) = 0x0001ffff; \
4156} while (0)
4157
4158/*
4159 * UART0_TxD, UART0_RxD
4160 */
4161#define __gpio_as_uart0() \
4162do { \
4163    REG_GPIO_PXFUNS(5) = 0x00000005; \
4164    REG_GPIO_PXTRGC(5) = 0x00000005; \
4165    REG_GPIO_PXSELC(5) = 0x00000005; \
4166    REG_GPIO_PXPES(5) = 0x00000005; \
4167} while (0)
4168
4169
4170/*
4171 * UART0_TxD, UART0_RxD, UART0_CTS, UART0_RTS
4172 */
4173#define __gpio_as_uart0_ctsrts() \
4174do { \
4175    REG_GPIO_PXFUNS(5) = 0x0000000f; \
4176    REG_GPIO_PXTRGC(5) = 0x0000000f; \
4177    REG_GPIO_PXSELC(5) = 0x0000000f; \
4178    REG_GPIO_PXPES(5) = 0x0000000f; \
4179} while (0)
4180/*
4181 * GPS_CLK GPS_MAG GPS_SIG
4182 */
4183#define __gpio_as_gps() \
4184do { \
4185    REG_GPIO_PXFUNS(5) = 0x00000007; \
4186    REG_GPIO_PXTRGC(5) = 0x00000007; \
4187    REG_GPIO_PXSELS(5) = 0x00000007; \
4188    REG_GPIO_PXPES(5) = 0x00000007; \
4189} while (0)
4190
4191/*
4192 * UART1_TxD, UART1_RxD
4193 */
4194#define __gpio_as_uart1() \
4195do { \
4196    REG_GPIO_PXFUNS(3) = 0x14000000; \
4197    REG_GPIO_PXTRGC(3) = 0x14000000; \
4198    REG_GPIO_PXSELC(3) = 0x14000000; \
4199    REG_GPIO_PXPES(3) = 0x14000000; \
4200} while (0)
4201
4202/*
4203 * UART1_TxD, UART1_RxD, UART1_CTS, UART1_RTS
4204 */
4205#define __gpio_as_uart1_ctsrts() \
4206do { \
4207    REG_GPIO_PXFUNS(3) = 0x3c000000; \
4208    REG_GPIO_PXTRGC(3) = 0x3c000000; \
4209    REG_GPIO_PXSELC(3) = 0x3c000000; \
4210    REG_GPIO_PXPES(3) = 0x3c000000; \
4211} while (0)
4212
4213
4214/*
4215 * UART2_TxD, UART2_RxD
4216 */
4217#define __gpio_as_uart2() \
4218do { \
4219    REG_GPIO_PXFUNS(2) = 0x50000000; \
4220    REG_GPIO_PXTRGC(2) = 0x50000000; \
4221    REG_GPIO_PXSELC(2) = 0x50000000; \
4222    REG_GPIO_PXPES(2) = 0x50000000; \
4223} while (0)
4224
4225/*
4226 * UART2_TxD, UART2_RxD, UART2_CTS, UART2_RTS
4227 */
4228#define __gpio_as_uart2_ctsrts() \
4229do { \
4230    REG_GPIO_PXFUNS(2) = 0xf0000000; \
4231    REG_GPIO_PXTRGC(2) = 0xf0000000; \
4232    REG_GPIO_PXSELC(2) = 0xf0000000; \
4233    REG_GPIO_PXPES(2) = 0xf0000000; \
4234} while (0)
4235
4236/*
4237 * UART3_TxD, UART3_RxD
4238 */
4239#define __gpio_as_uart3() \
4240do { \
4241    REG_GPIO_PXFUNS(4) = 0x00000028; \
4242    REG_GPIO_PXTRGC(4) = 0x00000028; \
4243    REG_GPIO_PXSELS(4) = 0x00000028; \
4244    REG_GPIO_PXPES(4) = 0x00000028; \
4245} while (0)
4246
4247/*
4248 * UART3_TxD, UART3_RxD, UART3_CTS, UART3_RTS
4249 */
4250#define __gpio_as_uart3_ctsrts() \
4251do { \
4252    REG_GPIO_PXFUNS(4) = 0x00000028; \
4253    REG_GPIO_PXTRGC(4) = 0x00000028; \
4254    REG_GPIO_PXSELS(4) = 0x00000028; \
4255    REG_GPIO_PXFUNS(4) = 0x00000300; \
4256    REG_GPIO_PXTRGC(4) = 0x00000300; \
4257    REG_GPIO_PXSELC(4) = 0x00000300; \
4258    REG_GPIO_PXPES(4) = 0x00000328; \
4259}
4260
4261/*
4262 * SD0 ~ SD7, CS1#, CLE, ALE, FRE#, FWE#, FRB#
4263 * @n: chip select number(1 ~ 6)
4264 */
4265#define __gpio_as_nand_8bit(n) \
4266do { \
4267                                    \
4268    REG_GPIO_PXFUNS(0) = 0x002c00ff; /* SD0 ~ SD7, CS1#, FRE#, FWE# */ \
4269    REG_GPIO_PXSELC(0) = 0x002c00ff; \
4270    REG_GPIO_PXPES(0) = 0x002c00ff; \
4271    REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */ \
4272    REG_GPIO_PXSELC(1) = 0x00000003; \
4273    REG_GPIO_PXPES(1) = 0x00000003; \
4274                                    \
4275    REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */ \
4276    REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1); \
4277    REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1); \
4278                                    \
4279     REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */ \
4280    REG_GPIO_PXSELC(0) = 0x00100000; \
4281    REG_GPIO_PXDIRC(0) = 0x00100000; \
4282    REG_GPIO_PXPES(0) = 0x00100000; \
4283} while (0)
4284
4285/*
4286 * SD0 ~ SD15, CS1#, CLE, ALE, FRE#, FWE#, FRB#
4287 * @n: chip select number(1 ~ 6)
4288 */
4289#define __gpio_as_nand_16bit(n) \
4290do { \
4291                                    \
4292    REG_GPIO_PXFUNS(0) = 0x002cffff; /* SD0 ~ SD15, CS1#, FRE#, FWE# */ \
4293    REG_GPIO_PXSELC(0) = 0x002cffff; \
4294    REG_GPIO_PXPES(0) = 0x002cffff; \
4295    REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */ \
4296    REG_GPIO_PXSELC(1) = 0x00000003; \
4297    REG_GPIO_PXPES(1) = 0x00000003; \
4298                                    \
4299    REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */ \
4300    REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1); \
4301    REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1); \
4302                                    \
4303     REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */ \
4304    REG_GPIO_PXSELC(0) = 0x00100000; \
4305    REG_GPIO_PXDIRC(0) = 0x00100000; \
4306    REG_GPIO_PXPES(0) = 0x00100000; \
4307} while (0)
4308
4309/*
4310 * SD0 ~ SD7, SA0 ~ SA5, CS2#, RD#, WR#, WAIT#
4311 */
4312#define __gpio_as_nor() \
4313do { \
4314    /* SD0 ~ SD7, RD#, WR#, CS2#, WAIT# */ \
4315    REG_GPIO_PXFUNS(0) = 0x084300ff; \
4316    REG_GPIO_PXTRGC(0) = 0x084300ff; \
4317    REG_GPIO_PXSELC(0) = 0x084300ff; \
4318    REG_GPIO_PXPES(0) = 0x084300ff; \
4319    /* SA0 ~ SA5 */ \
4320    REG_GPIO_PXFUNS(1) = 0x0000003f; \
4321    REG_GPIO_PXTRGC(1) = 0x0000003f; \
4322    REG_GPIO_PXSELC(1) = 0x0000003f; \
4323    REG_GPIO_PXPES(1) = 0x0000003f; \
4324} while (0)
4325
4326/*
4327 * LCD_D0~LCD_D7, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
4328 */
4329#define __gpio_as_lcd_8bit() \
4330do { \
4331    REG_GPIO_PXFUNS(2) = 0x000c03ff; \
4332    REG_GPIO_PXTRGC(2) = 0x000c03ff; \
4333    REG_GPIO_PXSELC(2) = 0x000c03ff; \
4334    REG_GPIO_PXPES(2) = 0x000c03ff; \
4335} while (0)
4336
4337/*
4338 * LCD_R3~LCD_R7, LCD_G2~LCD_G7, LCD_B3~LCD_B7,
4339 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
4340 */
4341#define __gpio_as_lcd_16bit() \
4342do { \
4343    REG_GPIO_PXFUNS(2) = 0x0f8ff3f8; \
4344    REG_GPIO_PXTRGC(2) = 0x0f8ff3f8; \
4345    REG_GPIO_PXSELC(2) = 0x0f8ff3f8; \
4346    REG_GPIO_PXPES(2) = 0x0f8ff3f8; \
4347} while (0)
4348
4349/*
4350 * LCD_R2~LCD_R7, LCD_G2~LCD_G7, LCD_B2~LCD_B7,
4351 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
4352 */
4353#define __gpio_as_lcd_18bit() \
4354do { \
4355    REG_GPIO_PXFUNS(2) = 0x0fcff3fc; \
4356    REG_GPIO_PXTRGC(2) = 0x0fcff3fc; \
4357    REG_GPIO_PXSELC(2) = 0x0fcff3fc; \
4358    REG_GPIO_PXPES(2) = 0x0fcff3fc; \
4359} while (0)
4360
4361/*
4362 * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7,
4363 * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
4364 */
4365#define __gpio_as_lcd_24bit() \
4366do { \
4367    REG_GPIO_PXFUNS(2) = 0x0fffffff; \
4368    REG_GPIO_PXTRGC(2) = 0x0fffffff; \
4369    REG_GPIO_PXSELC(2) = 0x0fffffff; \
4370    REG_GPIO_PXPES(2) = 0x0fffffff; \
4371} while (0)
4372
4373/*
4374 * LCD_CLS, LCD_SPL, LCD_PS, LCD_REV
4375 */
4376#define __gpio_as_lcd_special() \
4377do { \
4378    REG_GPIO_PXFUNS(2) = 0x0fffffff; \
4379    REG_GPIO_PXTRGC(2) = 0x0fffffff; \
4380    REG_GPIO_PXSELC(2) = 0x0feffbfc; \
4381    REG_GPIO_PXSELS(2) = 0x00100403; \
4382    REG_GPIO_PXPES(2) = 0x0fffffff; \
4383} while (0)
4384
4385/*
4386 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
4387 */
4388#define __gpio_as_cim() \
4389do { \
4390    REG_GPIO_PXFUNS(1) = 0x0003ffc0; \
4391    REG_GPIO_PXTRGC(1) = 0x0003ffc0; \
4392    REG_GPIO_PXSELC(1) = 0x0003ffc0; \
4393    REG_GPIO_PXPES(1) = 0x0003ffc0; \
4394} while (0)
4395
4396/*
4397 * SDATO, SDATI, BCLK, SYNC, SCLK_RSTN(gpio sepc) or
4398 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET(aic spec)
4399 */
4400#define __gpio_as_aic() \
4401do { \
4402    REG_GPIO_PXFUNS(4) = 0x16c00000; \
4403    REG_GPIO_PXTRGC(4) = 0x02c00000; \
4404    REG_GPIO_PXTRGS(4) = 0x14000000; \
4405    REG_GPIO_PXSELC(4) = 0x14c00000; \
4406    REG_GPIO_PXSELS(4) = 0x02000000; \
4407    REG_GPIO_PXPES(4) = 0x16c00000; \
4408} while (0)
4409
4410/*
4411 * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3
4412 */
4413#define __gpio_as_msc0_4bit() \
4414do { \
4415    REG_GPIO_PXFUNS(2) = 0x38400300; \
4416    REG_GPIO_PXTRGC(2) = 0x38400300; \
4417    REG_GPIO_PXSELS(2) = 0x30400300; \
4418    REG_GPIO_PXSELC(2) = 0x08000000; \
4419    REG_GPIO_PXPES(2) = 0x38400300; \
4420} while (0)
4421
4422/*
4423 * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3
4424 */
4425#define __gpio_as_msc1_4bit() \
4426do { \
4427    REG_GPIO_PXFUNS(1) = 0xfc000000; \
4428    REG_GPIO_PXTRGC(1) = 0xfc000000; \
4429    REG_GPIO_PXSELC(1) = 0xfc000000; \
4430    REG_GPIO_PXPES(1) = 0xfc000000; \
4431} while (0)
4432
4433/* Port B
4434 * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3
4435 */
4436#define __gpio_as_msc2_4bit_1() \
4437do { \
4438    REG_GPIO_PXFUNS(1) = 0xf0300000; \
4439    REG_GPIO_PXTRGC(1) = 0xf0300000; \
4440    REG_GPIO_PXSELC(1) = 0xf0300000; \
4441    REG_GPIO_PXPES(1) = 0xf0300000; \
4442} while (0)
4443
4444#define __gpio_as_msc __gpio_as_msc0_4bit /* default as msc0 4bit */
4445#define __gpio_as_msc0 __gpio_as_msc0_4bit /* msc0 default as 4bit */
4446#define __gpio_as_msc1 __gpio_as_msc1_4bit /* msc1 only support 4bit */
4447
4448/*
4449 * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7
4450 */
4451#define __gpio_as_tssi_1() \
4452do { \
4453    REG_GPIO_PXFUNS(1) = 0x0003ffc0; \
4454    REG_GPIO_PXTRGC(1) = 0x0003ffc0; \
4455    REG_GPIO_PXSELS(1) = 0x0003ffc0; \
4456    REG_GPIO_PXPES(1) = 0x0003ffc0; \
4457} while (0)
4458
4459/*
4460 * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7
4461 */
4462#define __gpio_as_tssi_2() \
4463do { \
4464    REG_GPIO_PXFUNS(1) = 0xfff00000; \
4465    REG_GPIO_PXTRGC(1) = 0x0fc00000; \
4466    REG_GPIO_PXTRGS(1) = 0xf0300000; \
4467    REG_GPIO_PXSELC(1) = 0xfff00000; \
4468    REG_GPIO_PXPES(1) = 0xfff00000; \
4469} while (0)
4470
4471/*
4472 * SSI_CE0, SSI_CE1, SSI_GPC, SSI_CLK, SSI_DT, SSI_DR
4473 */
4474#define __gpio_as_ssi() \
4475do { \
4476    REG_GPIO_PXFUNS(0) = 0x002c0000; /* SSI0_CE0, SSI0_CLK, SSI0_DT */ \
4477    REG_GPIO_PXTRGS(0) = 0x002c0000; \
4478    REG_GPIO_PXSELC(0) = 0x002c0000; \
4479    REG_GPIO_PXPES(0) = 0x002c0000; \
4480                        \
4481    REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0_DR */ \
4482    REG_GPIO_PXTRGC(0) = 0x00100000; \
4483    REG_GPIO_PXSELS(0) = 0x00100000; \
4484    REG_GPIO_PXPES(0) = 0x00100000; \
4485} while (0)
4486
4487/*
4488 * SSI_CE0, SSI_CE2, SSI_GPC, SSI_CLK, SSI_DT, SSI1_DR
4489 */
4490#define __gpio_as_ssi_1() \
4491do { \
4492    REG_GPIO_PXFUNS(5) = 0x0000fc00; \
4493    REG_GPIO_PXTRGC(5) = 0x0000fc00; \
4494    REG_GPIO_PXSELC(5) = 0x0000fc00; \
4495    REG_GPIO_PXPES(5) = 0x0000fc00; \
4496} while (0)
4497
4498/* Port B
4499 * SSI2_CE0, SSI2_CE2, SSI2_GPC, SSI2_CLK, SSI2_DT, SSI12_DR
4500 */
4501#define __gpio_as_ssi2_1() \
4502do { \
4503    REG_GPIO_PXFUNS(5) = 0xf0300000; \
4504    REG_GPIO_PXTRGC(5) = 0xf0300000; \
4505    REG_GPIO_PXSELS(5) = 0xf0300000; \
4506    REG_GPIO_PXPES(5) = 0xf0300000; \
4507} while (0)
4508
4509/*
4510 * I2C_SCK, I2C_SDA
4511 */
4512#define __gpio_as_i2c() \
4513do { \
4514    REG_GPIO_PXFUNS(4) = 0x00003000; \
4515    REG_GPIO_PXSELC(4) = 0x00003000; \
4516    REG_GPIO_PXPES(4) = 0x00003000; \
4517} while (0)
4518
4519/*
4520 * PWM0
4521 */
4522#define __gpio_as_pwm0() \
4523do { \
4524    REG_GPIO_PXFUNS(4) = 0x00100000; \
4525    REG_GPIO_PXSELC(4) = 0x00100000; \
4526    REG_GPIO_PXPES(4) = 0x00100000; \
4527} while (0)
4528
4529/*
4530 * PWM1
4531 */
4532#define __gpio_as_pwm1() \
4533do { \
4534    REG_GPIO_PXFUNS(5) = 0x00000800; \
4535    REG_GPIO_PXSELC(5) = 0x00000800; \
4536    REG_GPIO_PXPES(5) = 0x00000800; \
4537} while (0)
4538
4539/*
4540 * PWM2
4541 */
4542#define __gpio_as_pwm2() \
4543do { \
4544    REG_GPIO_PXFUNS(4) = 0x00400000; \
4545    REG_GPIO_PXSELC(4) = 0x00400000; \
4546    REG_GPIO_PXPES(4) = 0x00400000; \
4547} while (0)
4548
4549/*
4550 * PWM3
4551 */
4552#define __gpio_as_pwm3() \
4553do { \
4554    REG_GPIO_PXFUNS(4) = 0x00800000; \
4555    REG_GPIO_PXSELC(4) = 0x00800000; \
4556    REG_GPIO_PXPES(4) = 0x00800000; \
4557} while (0)
4558
4559/*
4560 * PWM4
4561 */
4562#define __gpio_as_pwm4() \
4563do { \
4564    REG_GPIO_PXFUNS(4) = 0x01000000; \
4565    REG_GPIO_PXSELC(4) = 0x01000000; \
4566    REG_GPIO_PXPES(4) = 0x01000000; \
4567} while (0)
4568
4569/*
4570 * PWM5
4571 */
4572#define __gpio_as_pwm5() \
4573do { \
4574    REG_GPIO_PXFUNS(4) = 0x02000000; \
4575    REG_GPIO_PXSELC(4) = 0x02000000; \
4576    REG_GPIO_PXPES(4) = 0x02000000; \
4577} while (0)
4578
4579/*
4580 * n = 0 ~ 5
4581 */
4582#define __gpio_as_pwm(n) __gpio_as_pwm##n()
4583
4584
4585//-------------------------------------------
4586// GPIO or Interrupt Mode
4587
4588#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
4589
4590#define __gpio_port_as_output(p, o) \
4591do { \
4592    REG_GPIO_PXFUNC(p) = (1 << (o)); \
4593    REG_GPIO_PXSELC(p) = (1 << (o)); \
4594    REG_GPIO_PXDIRS(p) = (1 << (o)); \
4595} while (0)
4596
4597#define __gpio_port_as_input(p, o) \
4598do { \
4599    REG_GPIO_PXFUNC(p) = (1 << (o)); \
4600    REG_GPIO_PXSELC(p) = (1 << (o)); \
4601    REG_GPIO_PXDIRC(p) = (1 << (o)); \
4602} while (0)
4603
4604#define __gpio_as_output(n) \
4605do { \
4606    unsigned int p, o; \
4607    p = (n) / 32; \
4608    o = (n) % 32; \
4609    __gpio_port_as_output(p, o); \
4610} while (0)
4611
4612#define __gpio_as_input(n) \
4613do { \
4614    unsigned int p, o; \
4615    p = (n) / 32; \
4616    o = (n) % 32; \
4617    __gpio_port_as_input(p, o); \
4618} while (0)
4619
4620#define __gpio_set_pin(n) \
4621do { \
4622    unsigned int p, o; \
4623    p = (n) / 32; \
4624    o = (n) % 32; \
4625    REG_GPIO_PXDATS(p) = (1 << o); \
4626} while (0)
4627
4628#define __gpio_clear_pin(n) \
4629do { \
4630    unsigned int p, o; \
4631    p = (n) / 32; \
4632    o = (n) % 32; \
4633    REG_GPIO_PXDATC(p) = (1 << o); \
4634} while (0)
4635
4636#define __gpio_get_pin(n) \
4637({ \
4638    unsigned int p, o, v; \
4639    p = (n) / 32; \
4640    o = (n) % 32; \
4641    if (__gpio_get_port(p) & (1 << o)) \
4642        v = 1; \
4643    else \
4644        v = 0; \
4645    v; \
4646})
4647
4648#define __gpio_as_irq_high_level(n) \
4649do { \
4650    unsigned int p, o; \
4651    p = (n) / 32; \
4652    o = (n) % 32; \
4653    REG_GPIO_PXIMS(p) = (1 << o); \
4654    REG_GPIO_PXTRGC(p) = (1 << o); \
4655    REG_GPIO_PXFUNC(p) = (1 << o); \
4656    REG_GPIO_PXSELS(p) = (1 << o); \
4657    REG_GPIO_PXDIRS(p) = (1 << o); \
4658    REG_GPIO_PXFLGC(p) = (1 << o); \
4659    REG_GPIO_PXIMC(p) = (1 << o); \
4660} while (0)
4661
4662#define __gpio_as_irq_low_level(n) \
4663do { \
4664    unsigned int p, o; \
4665    p = (n) / 32; \
4666    o = (n) % 32; \
4667    REG_GPIO_PXIMS(p) = (1 << o); \
4668    REG_GPIO_PXTRGC(p) = (1 << o); \
4669    REG_GPIO_PXFUNC(p) = (1 << o); \
4670    REG_GPIO_PXSELS(p) = (1 << o); \
4671    REG_GPIO_PXDIRC(p) = (1 << o); \
4672    REG_GPIO_PXFLGC(p) = (1 << o); \
4673    REG_GPIO_PXIMC(p) = (1 << o); \
4674} while (0)
4675
4676#define __gpio_as_irq_rise_edge(n) \
4677do { \
4678    unsigned int p, o; \
4679    p = (n) / 32; \
4680    o = (n) % 32; \
4681    REG_GPIO_PXIMS(p) = (1 << o); \
4682    REG_GPIO_PXTRGS(p) = (1 << o); \
4683    REG_GPIO_PXFUNC(p) = (1 << o); \
4684    REG_GPIO_PXSELS(p) = (1 << o); \
4685    REG_GPIO_PXDIRS(p) = (1 << o); \
4686    REG_GPIO_PXFLGC(p) = (1 << o); \
4687    REG_GPIO_PXIMC(p) = (1 << o); \
4688} while (0)
4689
4690#define __gpio_as_irq_fall_edge(n) \
4691do { \
4692    unsigned int p, o; \
4693    p = (n) / 32; \
4694    o = (n) % 32; \
4695    REG_GPIO_PXIMS(p) = (1 << o); \
4696    REG_GPIO_PXTRGS(p) = (1 << o); \
4697    REG_GPIO_PXFUNC(p) = (1 << o); \
4698    REG_GPIO_PXSELS(p) = (1 << o); \
4699    REG_GPIO_PXDIRC(p) = (1 << o); \
4700    REG_GPIO_PXFLGC(p) = (1 << o); \
4701    REG_GPIO_PXIMC(p) = (1 << o); \
4702} while (0)
4703
4704#define __gpio_mask_irq(n) \
4705do { \
4706    unsigned int p, o; \
4707    p = (n) / 32; \
4708    o = (n) % 32; \
4709    REG_GPIO_PXIMS(p) = (1 << o); \
4710} while (0)
4711
4712#define __gpio_unmask_irq(n) \
4713do { \
4714    unsigned int p, o; \
4715    p = (n) / 32; \
4716    o = (n) % 32; \
4717    REG_GPIO_PXIMC(p) = (1 << o); \
4718} while (0)
4719
4720#define __gpio_ack_irq(n) \
4721do { \
4722    unsigned int p, o; \
4723    p = (n) / 32; \
4724    o = (n) % 32; \
4725    REG_GPIO_PXFLGC(p) = (1 << o); \
4726} while (0)
4727
4728#define __gpio_get_irq() \
4729({ \
4730    unsigned int p, i, tmp, v = 0; \
4731    for (p = 3; p >= 0; p--) { \
4732        tmp = REG_GPIO_PXFLG(p); \
4733        for (i = 0; i < 32; i++) \
4734            if (tmp & (1 << i)) \
4735                v = (32*p + i); \
4736    } \
4737    v; \
4738})
4739
4740#define __gpio_group_irq(n) \
4741({ \
4742    register int tmp, i; \
4743    tmp = REG_GPIO_PXFLG((n)); \
4744    for (i=31;i>=0;i--) \
4745        if (tmp & (1 << i)) \
4746            break; \
4747    i; \
4748})
4749
4750#define __gpio_enable_pull(n) \
4751do { \
4752    unsigned int p, o; \
4753    p = (n) / 32; \
4754    o = (n) % 32; \
4755    REG_GPIO_PXPEC(p) = (1 << o); \
4756} while (0)
4757
4758#define __gpio_disable_pull(n) \
4759do { \
4760    unsigned int p, o; \
4761    p = (n) / 32; \
4762    o = (n) % 32; \
4763    REG_GPIO_PXPES(p) = (1 << o); \
4764} while (0)
4765
4766
4767/***************************************************************************
4768 * CPM
4769 ***************************************************************************/
4770#define __cpm_get_pllm() \
4771    ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
4772#define __cpm_get_plln() \
4773    ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
4774#define __cpm_get_pllod() \
4775    ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
4776
4777#define __cpm_get_pll1m() \
4778    ((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1M_MASK) >> CPM_CPPCR1_PLL1M_BIT)
4779#define __cpm_get_pll1n() \
4780    ((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1N_MASK) >> CPM_CPPCR1_PLL1N_BIT)
4781#define __cpm_get_pll1od() \
4782    ((REG_CPM_CPPCR1 & CPM_CPPCR1_PLL1OD_MASK) >> CPM_CPPCR1_PLL1OD_BIT)
4783
4784#define __cpm_get_cdiv() \
4785    ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
4786#define __cpm_get_hdiv() \
4787    ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
4788#define __cpm_get_h2div() \
4789    ((REG_CPM_CPCCR & CPM_CPCCR_H2DIV_MASK) >> CPM_CPCCR_H2DIV_BIT)
4790#define __cpm_get_pdiv() \
4791    ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
4792#define __cpm_get_mdiv() \
4793    ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
4794#define __cpm_get_sdiv() \
4795    ((REG_CPM_CPCCR & CPM_CPCCR_SDIV_MASK) >> CPM_CPCCR_SDIV_BIT)
4796#define __cpm_get_i2sdiv() \
4797    ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
4798#define __cpm_get_pixdiv() \
4799    ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
4800#define __cpm_get_mscdiv(n) \
4801    ((REG_CPM_MSCCDR(n) & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
4802#define __cpm_get_ssidiv() \
4803    ((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
4804#define __cpm_get_pcmdiv() \
4805    ((REG_CPM_PCMCDR & CPM_PCMCDR_PCMCD_MASK) >> CPM_PCMCDR_PCMCD_BIT)
4806#define __cpm_get_pll1div() \
4807    ((REG_CPM_CPPCR1 & CPM_CPCCR1_P1SDIV_MASK) >> CPM_CPCCR1_P1SDIV_BIT)
4808
4809#define __cpm_set_cdiv(v) \
4810    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
4811#define __cpm_set_hdiv(v) \
4812    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
4813#define __cpm_set_pdiv(v) \
4814    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
4815#define __cpm_set_mdiv(v) \
4816    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
4817#define __cpm_set_h1div(v) \
4818    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_H1DIV_MASK) | ((v) << (CPM_CPCCR_H1DIV_BIT)))
4819#define __cpm_set_udiv(v) \
4820    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
4821#define __cpm_set_i2sdiv(v) \
4822    (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
4823#define __cpm_set_pixdiv(v) \
4824    (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
4825#define __cpm_set_mscdiv(v) \
4826    (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
4827#define __cpm_set_ssidiv(v) \
4828    (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))
4829#define __cpm_set_pcmdiv(v) \
4830    (REG_CPM_PCMCDR = (REG_CPM_PCMCDR & ~CPM_PCMCDR_PCMCD_MASK) | ((v) << (CPM_PCMCDR_PCMCD_BIT)))
4831#define __cpm_set_pll1div(v) \
4832    (REG_CPM_CPPCR1 = (REG_CPM_CPPCR1 & ~CPM_CPCCR1_P1SDIV_MASK) | ((v) << (CPM_CPCCR1_P1SDIV_BIT)))
4833
4834#define __cpm_select_i2sclk_pll1() (REG_CPM_I2SCDR |= CPM_I2SCDR_I2PCS)
4835#define __cpm_select_i2sclk_pll0() (REG_CPM_I2SCDR &= ~CPM_I2SCDR_I2PCS)
4836#define __cpm_select_otgclk_pll1() (REG_CPM_USBCDR |= CPM_USBCDR_UPCS)
4837#define __cpm_select_otgclk_pll0() (REG_CPM_USBCDR &= ~CPM_USBCDR_UPCS)
4838#define __cpm_select_lcdpclk_pll1() (REG_CPM_LPCDR |= CPM_LPCDR_LPCS)
4839#define __cpm_select_lcdpclk_pll0() (REG_CPM_LPCDR &= ~CPM_LPCDR_LPCS)
4840#define __cpm_select_uhcclk_pll1() (REG_CPM_UHCCDR |= CPM_UHCCDR_UHPCS)
4841#define __cpm_select_uhcclk_pll0() (REG_CPM_UHCCDR &= ~CPM_UHCCDR_UHPCS)
4842#define __cpm_select_gpsclk_pll1() (REG_CPM_GPSCDR |= CPM_GPSCDR_GPCS)
4843#define __cpm_select_gpsclk_pll0() (REG_CPM_GPSCDR &= ~CPM_GPSCDR_GPCS)
4844#define __cpm_select_pcmclk_pll1() (REG_CPM_PCMCDR |= CPM_PCMCDR_PCMPCS)
4845#define __cpm_select_pcmclk_pll0() (REG_CPM_PCMCDR &= ~CPM_PCMCDR_PCMPCS)
4846#define __cpm_select_gpuclk_pll1() (REG_CPM_GPUCDR |= CPM_GPUCDR_GPCS)
4847#define __cpm_select_gpuclk_pll0() (REG_CPM_GPUCDR &= ~CPM_GPUCDR_GPCS)
4848#define __cpm_select_clk_pll1() (REG_CPM_CDR |= CPM_CDR_PCS)
4849#define __cpm_select_clk_pll0() (REG_CPM_CDR &= ~CPM_CDR_PCS)
4850
4851
4852#define __cpm_select_pcmclk_pll() (REG_CPM_PCMCDR |= CPM_PCMCDR_PCMS)
4853#define __cpm_select_pcmclk_exclk() (REG_CPM_PCMCDR &= ~CPM_PCMCDR_PCMS)
4854#define __cpm_select_pixclk_ext() (REG_CPM_LPCDR |= CPM_LPCDR_LPCS)
4855#define __cpm_select_pixclk_pll() (REG_CPM_LPCDR &= ~CPM_LPCDR_LPCS)
4856#define __cpm_select_tveclk_exclk() (REG_CPM_LPCDR |= CPM_CPCCR_LSCS)
4857#define __cpm_select_tveclk_pll() (REG_CPM_LPCDR &= ~CPM_LPCDR_LSCS)
4858#define __cpm_select_pixclk_lcd() (REG_CPM_LPCDR &= ~CPM_LPCDR_LTCS)
4859#define __cpm_select_pixclk_tve() (REG_CPM_LPCDR |= CPM_LPCDR_LTCS)
4860#define __cpm_select_i2sclk_exclk() (REG_CPM_I2SCDR &= ~CPM_I2SCDR_I2CS)
4861#define __cpm_select_i2sclk_pll() (REG_CPM_I2SCDR |= CPM_I2SCDR_I2CS)
4862//#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
4863//#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
4864
4865#define __cpm_enable_cko()
4866#define __cpm_exclk_direct() (REG_CPM_CPCCR &= ~CPM_CPCCR_ECS)
4867#define __cpm_exclk_div2() (REG_CPM_CPCCR |= CPM_CPCCR_ECS)
4868#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
4869
4870#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
4871#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
4872
4873#define __cpm_pll1_enable() (REG_CPM_CPPCR1 |= CPM_CPPCR1_PLL1EN)
4874
4875#define __cpm_pll_is_off() (REG_CPM_CPPSR & CPM_CPPSR_PLLOFF)
4876#define __cpm_pll_is_on() (REG_CPM_CPPSR & CPM_CPPSR_PLLON)
4877#define __cpm_pll_bypass() (REG_CPM_CPPSR |= CPM_CPPSR_PLLBP)
4878
4879#define __cpm_get_cclk_doze_duty() \
4880    ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
4881#define __cpm_set_cclk_doze_duty(v) \
4882    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
4883
4884#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
4885#define __cpm_idle_mode() \
4886    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
4887#define __cpm_sleep_mode() \
4888    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
4889
4890#define __cpm_stop_all() \
4891    do {\
4892        (REG_CPM_CLKGR0 = 0xffffffff);\
4893        (REG_CPM_CLKGR1 = 0x3ff);\
4894    }while(0)
4895#define __cpm_stop_emc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_EMC)
4896#define __cpm_stop_ddr() (REG_CPM_CLKGR0 |= CPM_CLKGR0_DDR)
4897#define __cpm_stop_ipu() (REG_CPM_CLKGR0 |= CPM_CLKGR0_IPU)
4898#define __cpm_stop_lcd() (REG_CPM_CLKGR0 |= CPM_CLKGR0_LCD)
4899#define __cpm_stop_tve() (REG_CPM_CLKGR0 |= CPM_CLKGR0_TVE)
4900#define __cpm_stop_Cim() (REG_CPM_CLKGR0 |= CPM_CLKGR0_CIM)
4901#define __cpm_stop_mdma() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MDMA)
4902#define __cpm_stop_uhc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UHC)
4903#define __cpm_stop_mac() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MAC)
4904#define __cpm_stop_gps() (REG_CPM_CLKGR0 |= CPM_CLKGR0_GPS)
4905#define __cpm_stop_dmac() (REG_CPM_CLKGR0 |= CPM_CLKGR0_DMAC)
4906#define __cpm_stop_ssi2() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI2)
4907#define __cpm_stop_ssi1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI1)
4908#define __cpm_stop_uart3() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART3)
4909#define __cpm_stop_uart2() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART2)
4910#define __cpm_stop_uart1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART1)
4911#define __cpm_stop_uart0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_UART0)
4912#define __cpm_stop_sadc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SADC)
4913#define __cpm_stop_kbc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_KBC)
4914#define __cpm_stop_msc2() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC2)
4915#define __cpm_stop_msc1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC1)
4916#define __cpm_stop_owi() (REG_CPM_CLKGR0 |= CPM_CLKGR0_OWI)
4917#define __cpm_stop_tssi() (REG_CPM_CLKGR0 |= CPM_CLKGR0_TSSI)
4918#define __cpm_stop_aic() (REG_CPM_CLKGR0 |= CPM_CLKGR0_AIC)
4919#define __cpm_stop_scc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SCC)
4920#define __cpm_stop_i2c0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_I2C1)
4921#define __cpm_stop_i2c1() (REG_CPM_CLKGR0 |= CPM_CLKGR0_I2C0)
4922#define __cpm_stop_ssi0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_SSI0)
4923#define __cpm_stop_msc0() (REG_CPM_CLKGR0 |= CPM_CLKGR0_MSC0)
4924#define __cpm_stop_otg() (REG_CPM_CLKGR0 |= CPM_CLKGR0_OTG)
4925#define __cpm_stop_bch() (REG_CPM_CLKGR0 |= CPM_CLKGR0_BCH)
4926#define __cpm_stop_nemc() (REG_CPM_CLKGR0 |= CPM_CLKGR0_NEMC)
4927#define __cpm_stop_gpu() (REG_CPM_CLKGR1 |= CPM_CLKGR0_GPU)
4928#define __cpm_stop_pcm() (REG_CPM_CLKGR1 |= CPM_CLKGR0_PCM)
4929#define __cpm_stop_ahb1() (REG_CPM_CLKGR1 |= CPM_CLKGR0_AHB1)
4930#define __cpm_stop_cabac() (REG_CPM_CLKGR1 |= CPM_CLKGR0_CABAC)
4931#define __cpm_stop_sram() (REG_CPM_CLKGR1 |= CPM_CLKGR0_SRAM)
4932#define __cpm_stop_dct() (REG_CPM_CLKGR1 |= CPM_CLKGR0_DCT)
4933#define __cpm_stop_me() (REG_CPM_CLKGR1 |= CPM_CLKGR0_ME)
4934#define __cpm_stop_dblk() (REG_CPM_CLKGR1 |= CPM_CLKGR0_DBLK)
4935#define __cpm_stop_mc() (REG_CPM_CLKGR1 |= CPM_CLKGR0_MC)
4936#define __cpm_stop_bdma() (REG_CPM_CLKGR1 |= CPM_CLKGR0_BDMA)
4937
4938#define __cpm_start_all() \
4939    do {\
4940        REG_CPM_CLKGR0 = 0x0;\
4941        REG_CPM_CLKGR1 = 0x0;\
4942    } while(0)
4943#define __cpm_start_emc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_EMC)
4944#define __cpm_start_ddr() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_DDR)
4945#define __cpm_start_ipu() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_IPU)
4946#define __cpm_start_lcd() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_LCD)
4947#define __cpm_start_tve() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_TVE)
4948#define __cpm_start_Cim() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_CIM)
4949#define __cpm_start_mdma() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MDMA)
4950#define __cpm_start_uhc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UHC)
4951#define __cpm_start_mac() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MAC)
4952#define __cpm_start_gps() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_GPS)
4953#define __cpm_start_dmac() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_DMAC)
4954#define __cpm_start_ssi2() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI2)
4955#define __cpm_start_ssi1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI1)
4956#define __cpm_start_uart3() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART3)
4957#define __cpm_start_uart2() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART2)
4958#define __cpm_start_uart1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART1)
4959#define __cpm_start_uart0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_UART0)
4960#define __cpm_start_sadc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SADC)
4961#define __cpm_start_kbc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_KBC)
4962#define __cpm_start_msc2() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC2)
4963#define __cpm_start_msc1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC1)
4964#define __cpm_start_owi() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_OWI)
4965#define __cpm_start_tssi() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_TSSI)
4966#define __cpm_start_aic() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_AIC)
4967#define __cpm_start_scc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SCC)
4968#define __cpm_start_i2c0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_I2C1)
4969#define __cpm_start_i2c1() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_I2C0)
4970#define __cpm_start_ssi0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_SSI0)
4971#define __cpm_start_msc0() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_MSC0)
4972#define __cpm_start_otg() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_OTG)
4973#define __cpm_start_bch() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_BCH)
4974#define __cpm_start_nemc() (REG_CPM_CLKGR0 &= ~CPM_CLKGR0_NEMC)
4975#define __cpm_start_gpu() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_GPU)
4976#define __cpm_start_pcm() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_PCM)
4977#define __cpm_start_ahb1() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_AHB1)
4978#define __cpm_start_cabac() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_CABAC)
4979#define __cpm_start_sram() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_SRAM)
4980#define __cpm_start_dct() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_DCT)
4981#define __cpm_start_me() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_ME)
4982#define __cpm_start_dblk() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_DBLK)
4983#define __cpm_start_mc() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_MC)
4984#define __cpm_start_bdma() (REG_CPM_CLKGR1 &= ~CPM_CLKGR0_BDMA)
4985
4986#define __cpm_get_o1st() \
4987    ((REG_CPM_OPCR & CPM_OPCR_O1ST_MASK) >> CPM_OPCR_O1ST_BIT)
4988#define __cpm_set_o1st(v) \
4989    (REG_CPM_OPCR = (REG_CPM_OPCR & ~CPM_OPCR_O1ST_MASK) | ((v) << (CPM_OPCR_O1ST_BIT)))
4990#define __cpm_suspend_udcphy() (REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE)
4991#define __cpm_enable_osc_in_sleep() (REG_CPM_OPCR |= CPM_OPCR_OSC_ENABLE)
4992#define __cpm_select_rtcclk_rtc() (REG_CPM_OPCR |= CPM_OPCR_ERCS)
4993#define __cpm_select_rtcclk_exclk() (REG_CPM_OPCR &= ~CPM_OPCR_ERCS)
4994
4995#ifdef CFG_EXTAL
4996#define JZ_EXTAL CFG_EXTAL
4997#else
4998#define JZ_EXTAL 3686400
4999#endif
5000#define JZ_EXTAL2 32768 /* RTC clock */
5001
5002/* PLL output frequency */
5003static __inline__ unsigned int __cpm_get_pllout(void)
5004{
5005    unsigned long m, n, no, pllout;
5006    unsigned long cppcr = REG_CPM_CPPCR;
5007    unsigned long od[4] = {1, 2, 4, 8};
5008    if ((cppcr & CPM_CPPCR_PLLEN) && (!(cppcr & CPM_CPPCR_PLLBP))) {
5009        m = __cpm_get_pllm() * 2;
5010        n = __cpm_get_plln();
5011        no = od[__cpm_get_pllod()];
5012        pllout = ((JZ_EXTAL) * m / (n * no));
5013    } else
5014        pllout = JZ_EXTAL;
5015    return pllout;
5016}
5017
5018/* PLL output frequency */
5019static __inline__ unsigned int __cpm_get_pll1out(void)
5020{
5021    unsigned long m, n, no, pllout;
5022    unsigned long cppcr1 = REG_CPM_CPPCR1;
5023    unsigned long od[4] = {1, 2, 4, 8};
5024    if (cppcr1 & CPM_CPPCR1_PLL1EN)
5025    {
5026        m = __cpm_get_pll1m() * 2;
5027        n = __cpm_get_pll1n();
5028        no = od[__cpm_get_pll1od()];
5029        if (cppcr1 & CPM_CPPCR1_P1SCS)
5030            pllout = ((__cpm_get_pllout()) * m / (n * no));
5031        else
5032            pllout = ((JZ_EXTAL) * m / (n * no));
5033            
5034    } else
5035        pllout = JZ_EXTAL;
5036    return pllout;
5037}
5038
5039/* PLL output frequency for MSC/I2S/LCD/USB */
5040static __inline__ unsigned int __cpm_get_pllout2(void)
5041{
5042    if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
5043        return __cpm_get_pllout();
5044    else
5045        return __cpm_get_pllout()/2;
5046}
5047
5048/* CPU core clock */
5049static __inline__ unsigned int __cpm_get_cclk(void)
5050{
5051    int div[] = {1, 2, 3, 4, 6, 8};
5052
5053    return __cpm_get_pllout() / div[__cpm_get_cdiv()];
5054}
5055
5056/* AHB system bus clock */
5057static __inline__ unsigned int __cpm_get_hclk(void)
5058{
5059    int div[] = {1, 2, 3, 4, 6, 8};
5060
5061    return __cpm_get_pllout() / div[__cpm_get_hdiv()];
5062}
5063
5064/* Memory bus clock */
5065static __inline__ unsigned int __cpm_get_mclk(void)
5066{
5067    int div[] = {1, 2, 3, 4, 6, 8};
5068
5069    return __cpm_get_pllout() / div[__cpm_get_mdiv()];
5070}
5071
5072/* APB peripheral bus clock */
5073static __inline__ unsigned int __cpm_get_pclk(void)
5074{
5075    int div[] = {1, 2, 3, 4, 6, 8};
5076
5077    return __cpm_get_pllout() / div[__cpm_get_pdiv()];
5078}
5079
5080/* AHB1 module clock */
5081static __inline__ unsigned int __cpm_get_h2clk(void)
5082{
5083    int div[] = {1, 2, 3, 4, 6, 8};
5084
5085    return __cpm_get_pllout() / div[__cpm_get_h2div()];
5086}
5087
5088/* LCD pixel clock */
5089static __inline__ unsigned int __cpm_get_pixclk(void)
5090{
5091    return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
5092}
5093
5094/* I2S clock */
5095static __inline__ unsigned int __cpm_get_i2sclk(void)
5096{
5097    if (REG_CPM_I2SCDR & CPM_I2SCDR_I2CS) {
5098        return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
5099    }
5100    else {
5101        return JZ_EXTAL;
5102    }
5103}
5104
5105/* USB clock */
5106/*
5107static __inline__ unsigned int __cpm_get_usbclk(void)
5108{
5109    if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
5110        return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
5111    }
5112    else {
5113        return JZ_EXTAL;
5114    }
5115}
5116*/
5117/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
5118static __inline__ unsigned int __cpm_get_extalclk(void)
5119{
5120    return JZ_EXTAL;
5121}
5122
5123/* RTC clock for CPM,INTC,RTC,TCU,WDT */
5124static __inline__ unsigned int __cpm_get_rtcclk(void)
5125{
5126    return JZ_EXTAL2;
5127}
5128
5129/*
5130 * Output 24MHz for SD and 16MHz for MMC.
5131 */
5132#if 1
5133static inline void __cpm_select_msc_clk(int n, int sd)
5134{
5135    unsigned int pllout2 = __cpm_get_pllout2();
5136    unsigned int div = 0;
5137
5138    if (sd) {
5139        div = pllout2 / 24000000;
5140    }
5141    else {
5142        div = pllout2 / 16000000;
5143    }
5144
5145    REG_CPM_MSCCDR = div - 1;
5146    REG_CPM_CPCCR |= CPM_CPCCR_CE;
5147}
5148#endif
5149/***************************************************************************
5150 * TCU
5151 ***************************************************************************/
5152// where 'n' is the TCU channel
5153#define __tcu_select_extalclk(n) \
5154    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
5155#define __tcu_select_rtcclk(n) \
5156    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
5157#define __tcu_select_pclk(n) \
5158    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
5159
5160#define __tcu_select_clk_div1(n) \
5161    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
5162#define __tcu_select_clk_div4(n) \
5163    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
5164#define __tcu_select_clk_div16(n) \
5165    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
5166#define __tcu_select_clk_div64(n) \
5167    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
5168#define __tcu_select_clk_div256(n) \
5169    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
5170#define __tcu_select_clk_div1024(n) \
5171    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
5172
5173#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
5174#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
5175
5176#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
5177#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
5178
5179#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
5180#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
5181
5182#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
5183#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
5184
5185#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
5186#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
5187#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
5188#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
5189#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
5190#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
5191#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
5192#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
5193#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
5194#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
5195
5196#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
5197#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
5198
5199#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
5200#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
5201
5202#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
5203#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
5204
5205#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
5206#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
5207#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
5208#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
5209
5210
5211/***************************************************************************
5212 * WDT
5213 ***************************************************************************/
5214#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
5215#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
5216#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
5217#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
5218
5219#define __wdt_select_extalclk() \
5220    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
5221#define __wdt_select_rtcclk() \
5222    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
5223#define __wdt_select_pclk() \
5224    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
5225
5226#define __wdt_select_clk_div1() \
5227    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
5228#define __wdt_select_clk_div4() \
5229    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
5230#define __wdt_select_clk_div16() \
5231    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
5232#define __wdt_select_clk_div64() \
5233    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
5234#define __wdt_select_clk_div256() \
5235    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
5236#define __wdt_select_clk_div1024() \
5237    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
5238
5239
5240/***************************************************************************
5241 * UART
5242 ***************************************************************************/
5243
5244#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
5245#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
5246
5247#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
5248#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
5249
5250#define __uart_enable_receive_irq() \
5251  ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
5252#define __uart_disable_receive_irq() \
5253  ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
5254
5255#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
5256#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
5257
5258#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
5259
5260#define __uart_set_baud(devclk, baud) \
5261  do { \
5262    REG8(UART0_LCR) |= UARTLCR_DLAB; \
5263    REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
5264    REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
5265    REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
5266  } while (0)
5267
5268#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
5269#define __uart_clear_errors() \
5270  ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
5271
5272#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
5273#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
5274#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
5275#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
5276#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
5277#define __uart_receive_char() REG8(UART0_RDR)
5278#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
5279#define __uart_enable_irda() \
5280  /* Tx high pulse as 0, Rx low pulse as 0 */ \
5281  ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
5282
5283/***************************************************************************
5284 * Mem Copy DMAC
5285 ***************************************************************************/
5286
5287/* n is the DMA channel index (0 - 3) */
5288
5289#define __mdmac_enable_module \
5290    ( REG_MDMAC_DMACR |= DMAC_MDMACR_DMAE | DMAC_MDMACR_PR_012345 )
5291#define __mdmac_disable_module \
5292    ( REG_MDMAC_DMACR &= ~DMAC_MDMACR_DMAE )
5293
5294/* p=0,1,2,3 */
5295#define __mdmac_set_priority(p) \
5296do { \
5297    REG_MDMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
5298    REG_MDMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
5299} while (0)
5300
5301#define __mdmac_test_halt_error ( REG_MDMAC_DMACR & DMAC_MDMACR_HLT )
5302#define __mdmac_test_addr_error ( REG_MDMAC_DMACR & DMAC_MDMACR_AR )
5303
5304#define __mdmac_channel_enable_clk \
5305    REG_MDMAC_DMACKE |= 1 << (n);
5306
5307#define __mdmac_enable_descriptor(n) \
5308  ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
5309#define __mdmac_disable_descriptor(n) \
5310  ( REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
5311
5312#define __mdmac_enable_channel(n) \
5313do { \
5314    REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_EN; \
5315} while (0)
5316#define __mdmac_disable_channel(n) \
5317do { \
5318    REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN; \
5319} while (0)
5320#define __mdmac_channel_enabled(n) \
5321  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_EN )
5322
5323#define __mdmac_channel_enable_irq(n) \
5324  ( REG_MDMAC_DCMD((n)) |= DMAC_DCMD_TIE )
5325#define __mdmac_channel_disable_irq(n) \
5326  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
5327
5328#define __mdmac_channel_transmit_halt_detected(n) \
5329  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
5330#define __mdmac_channel_transmit_end_detected(n) \
5331  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_TT )
5332#define __mdmac_channel_address_error_detected(n) \
5333  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
5334#define __mdmac_channel_count_terminated_detected(n) \
5335  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_CT )
5336#define __mdmac_channel_descriptor_invalid_detected(n) \
5337  ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_INV )
5338
5339#define __mdmac_channel_clear_transmit_halt(n) \
5340    do { \
5341        /* clear both channel halt error and globle halt error */ \
5342        REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT; \
5343        REG_MDMAC_DMACR &= ~DMAC_DMACR_HLT; \
5344    } while (0)
5345#define __mdmac_channel_clear_transmit_end(n) \
5346  ( REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
5347#define __mdmac_channel_clear_address_error(n) \
5348    do { \
5349        REG_MDMAC_DDA(n) = 0; /* clear descriptor address register */ \
5350        REG_MDMAC_DSAR(n) = 0; /* clear source address register */ \
5351        REG_MDMAC_DTAR(n) = 0; /* clear target address register */ \
5352        /* clear both channel addr error and globle address error */ \
5353        REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_AR; \
5354        REG_MDMAC_DMACR &= ~DMAC_DMACR_AR; \
5355    } while (0)
5356#define __mdmac_channel_clear_count_terminated(n) \
5357  ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
5358#define __mdmac_channel_clear_descriptor_invalid(n) \
5359  ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
5360
5361#define __mdmac_channel_set_transfer_unit_32bit(n) \
5362do { \
5363    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5364    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
5365} while (0)
5366
5367#define __mdmac_channel_set_transfer_unit_16bit(n) \
5368do { \
5369    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5370    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
5371} while (0)
5372
5373#define __mdmac_channel_set_transfer_unit_8bit(n) \
5374do { \
5375    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5376    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
5377} while (0)
5378
5379#define __mdmac_channel_set_transfer_unit_16byte(n) \
5380do { \
5381    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5382    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
5383} while (0)
5384
5385#define __mdmac_channel_set_transfer_unit_32byte(n) \
5386do { \
5387    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5388    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
5389} while (0)
5390
5391/* w=8,16,32 */
5392#define __mdmac_channel_set_dest_port_width(n,w) \
5393do { \
5394    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
5395    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
5396} while (0)
5397
5398/* w=8,16,32 */
5399#define __mdmac_channel_set_src_port_width(n,w) \
5400do { \
5401    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
5402    REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
5403} while (0)
5404
5405/* v=0-15 */
5406#define __mdmac_channel_set_rdil(n,v) \
5407do { \
5408    REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
5409    REG_MDMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
5410} while (0)
5411
5412#define __mdmac_channel_dest_addr_fixed(n) \
5413    (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DAI)
5414#define __mdmac_channel_dest_addr_increment(n) \
5415    (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DAI)
5416
5417#define __mdmac_channel_src_addr_fixed(n) \
5418    (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SAI)
5419#define __mdmac_channel_src_addr_increment(n) \
5420    (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SAI)
5421
5422#define __mdmac_channel_set_doorbell(n) \
5423    (REG_MDMAC_DMADBSR = (1 << (n)))
5424
5425#define __mdmac_channel_irq_detected(n) (REG_MDMAC_DMAIPR & (1 << (n)))
5426#define __mdmac_channel_ack_irq(n) (REG_MDMAC_DMAIPR &= ~(1 <<(n)))
5427
5428static __inline__ int __mdmac_get_irq(void)
5429{
5430    int i;
5431    for (i = 0; i < MAX_MDMA_NUM; i++)
5432        if (__mdmac_channel_irq_detected(i))
5433            return i;
5434    return -1;
5435}
5436
5437
5438
5439/***************************************************************************
5440 * DMAC
5441 ***************************************************************************/
5442
5443/* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */
5444
5445#define __dmac_enable_module(m) \
5446    ( REG_DMAC_DMACR(m) |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_012345 )
5447#define __dmac_disable_module(m) \
5448    ( REG_DMAC_DMACR(m) &= ~DMAC_DMACR_DMAE )
5449
5450/* p=0,1,2,3 */
5451#define __dmac_set_priority(m,p) \
5452do { \
5453    REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK; \
5454    REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT); \
5455} while (0)
5456
5457#define __dmac_test_halt_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_HLT )
5458#define __dmac_test_addr_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_AR )
5459
5460#define __dmac_enable_descriptor(n) \
5461  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
5462#define __dmac_disable_descriptor(n) \
5463  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
5464
5465#define __dmac_enable_channel(n) \
5466  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
5467#define __dmac_disable_channel(n) \
5468  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
5469#define __dmac_channel_enabled(n) \
5470  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
5471
5472#define __dmac_channel_enable_irq(n) \
5473  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
5474#define __dmac_channel_disable_irq(n) \
5475  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
5476
5477#define __dmac_channel_transmit_halt_detected(n) \
5478  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
5479#define __dmac_channel_transmit_end_detected(n) \
5480  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
5481#define __dmac_channel_address_error_detected(n) \
5482  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
5483#define __dmac_channel_count_terminated_detected(n) \
5484  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
5485#define __dmac_channel_descriptor_invalid_detected(n) \
5486  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
5487
5488#define __dmac_channel_clear_transmit_halt(n) \
5489  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
5490#define __dmac_channel_clear_transmit_end(n) \
5491  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
5492#define __dmac_channel_clear_address_error(n) \
5493  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
5494#define __dmac_channel_clear_count_terminated(n) \
5495  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
5496#define __dmac_channel_clear_descriptor_invalid(n) \
5497  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
5498
5499#define __dmac_channel_set_transfer_unit_32bit(n) \
5500do { \
5501    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5502    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
5503} while (0)
5504
5505#define __dmac_channel_set_transfer_unit_16bit(n) \
5506do { \
5507    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5508    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
5509} while (0)
5510
5511#define __dmac_channel_set_transfer_unit_8bit(n) \
5512do { \
5513    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5514    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
5515} while (0)
5516
5517#define __dmac_channel_set_transfer_unit_16byte(n) \
5518do { \
5519    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5520    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
5521} while (0)
5522
5523#define __dmac_channel_set_transfer_unit_32byte(n) \
5524do { \
5525    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
5526    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
5527} while (0)
5528
5529/* w=8,16,32 */
5530#define __dmac_channel_set_dest_port_width(n,w) \
5531do { \
5532    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
5533    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
5534} while (0)
5535
5536/* w=8,16,32 */
5537#define __dmac_channel_set_src_port_width(n,w) \
5538do { \
5539    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
5540    REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
5541} while (0)
5542
5543/* v=0-15 */
5544#define __dmac_channel_set_rdil(n,v) \
5545do { \
5546    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
5547    REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
5548} while (0)
5549
5550#define __dmac_channel_dest_addr_fixed(n) \
5551  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
5552#define __dmac_channel_dest_addr_increment(n) \
5553  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
5554
5555#define __dmac_channel_src_addr_fixed(n) \
5556  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
5557#define __dmac_channel_src_addr_increment(n) \
5558  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
5559
5560#define __dmac_channel_set_doorbell(m,n) \
5561    ( REG_DMAC_DMADBSR(m) = (1 << (n)) )
5562
5563#define __dmac_channel_irq_detected(m,n) ( REG_DMAC_DMAIPR(m) & (1 << (n)) )
5564#define __dmac_channel_ack_irq(m,n) ( REG_DMAC_DMAIPR(m) &= ~(1 << (n)) )
5565
5566static __inline__ int __dmac_get_irq(void)
5567{
5568    int i;
5569    for (i = 0; i < MAX_DMA_NUM; i++)
5570        if (__dmac_channel_irq_detected(i/HALF_DMA_NUM, i-i/HALF_DMA_NUM*HALF_DMA_NUM))
5571            return i;
5572    return -1;
5573}
5574
5575
5576/***************************************************************************
5577 * AIC (AC'97 & I2S Controller)
5578 ***************************************************************************/
5579
5580#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
5581#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
5582
5583#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
5584#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
5585
5586#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
5587#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
5588#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
5589
5590#define __aic_reset() \
5591do { \
5592        REG_AIC_FR |= AIC_FR_RST; \
5593} while(0)
5594
5595
5596#define __aic_set_transmit_trigger(n) \
5597do { \
5598    REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
5599    REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
5600} while(0)
5601
5602#define __aic_set_receive_trigger(n) \
5603do { \
5604    REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
5605    REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
5606} while(0)
5607
5608#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
5609#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
5610#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
5611#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
5612#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
5613#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
5614
5615#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
5616#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
5617
5618#define __aic_enable_transmit_intr() \
5619  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
5620#define __aic_disable_transmit_intr() \
5621  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
5622#define __aic_enable_receive_intr() \
5623  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
5624#define __aic_disable_receive_intr() \
5625  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
5626
5627#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
5628#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
5629#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
5630#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
5631
5632#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
5633#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
5634#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
5635#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
5636#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
5637#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
5638
5639#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
5640#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
5641#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
5642#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
5643#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
5644#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
5645
5646#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
5647#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
5648#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
5649#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
5650#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
5651#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
5652
5653#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
5654#define __ac97_set_xs_mono() \
5655do { \
5656    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
5657    REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
5658} while(0)
5659#define __ac97_set_xs_stereo() \
5660do { \
5661    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
5662    REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
5663} while(0)
5664
5665/* In fact, only stereo is support now. */
5666#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
5667#define __ac97_set_rs_mono() \
5668do { \
5669    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
5670    REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
5671} while(0)
5672#define __ac97_set_rs_stereo() \
5673do { \
5674    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
5675    REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
5676} while(0)
5677
5678#define __ac97_warm_reset_codec() \
5679 do { \
5680    REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
5681    REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
5682    udelay(2); \
5683    REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
5684    REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
5685 } while (0)
5686
5687#define __ac97_cold_reset_codec() \
5688 do { \
5689    REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
5690    udelay(2); \
5691    REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
5692 } while (0)
5693
5694/* n=8,16,18,20 */
5695#define __ac97_set_iass(n) \
5696 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
5697#define __ac97_set_oass(n) \
5698 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
5699
5700#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
5701#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
5702
5703/* n=8,16,18,20,24 */
5704/*#define __i2s_set_sample_size(n) \
5705 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
5706
5707#define __i2s_set_oss_sample_size(n) \
5708 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
5709#define __i2s_set_iss_sample_size(n) \
5710 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
5711
5712#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
5713#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
5714
5715#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
5716#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
5717#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
5718#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
5719
5720#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
5721
5722#define __aic_get_transmit_resident() \
5723  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
5724#define __aic_get_receive_count() \
5725  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
5726
5727#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
5728#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
5729#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
5730#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
5731#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
5732#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
5733#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
5734
5735#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
5736
5737#define CODEC_READ_CMD (1 << 19)
5738#define CODEC_WRITE_CMD (0 << 19)
5739#define CODEC_REG_INDEX_BIT 12
5740#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
5741#define CODEC_REG_DATA_BIT 4
5742#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
5743
5744#define __ac97_out_rcmd_addr(reg) \
5745do { \
5746    REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
5747} while (0)
5748
5749#define __ac97_out_wcmd_addr(reg) \
5750do { \
5751    REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
5752} while (0)
5753
5754#define __ac97_out_data(value) \
5755do { \
5756    REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
5757} while (0)
5758
5759#define __ac97_in_data() \
5760 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
5761
5762#define __ac97_in_status_addr() \
5763 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
5764
5765#define __i2s_set_sample_rate(i2sclk, sync) \
5766  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
5767
5768#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
5769#define __aic_read_rfifo() ( REG_AIC_DR )
5770
5771#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
5772#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
5773
5774//
5775// Define next ops for AC97 compatible
5776//
5777
5778#define AC97_ACSR AIC_ACSR
5779
5780#define __ac97_enable() __aic_enable(); __aic_select_ac97()
5781#define __ac97_disable() __aic_disable()
5782#define __ac97_reset() __aic_reset()
5783
5784#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
5785#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
5786
5787#define __ac97_enable_record() __aic_enable_record()
5788#define __ac97_disable_record() __aic_disable_record()
5789#define __ac97_enable_replay() __aic_enable_replay()
5790#define __ac97_disable_replay() __aic_disable_replay()
5791#define __ac97_enable_loopback() __aic_enable_loopback()
5792#define __ac97_disable_loopback() __aic_disable_loopback()
5793
5794#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
5795#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
5796#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
5797#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
5798
5799#define __ac97_transmit_request() __aic_transmit_request()
5800#define __ac97_receive_request() __aic_receive_request()
5801#define __ac97_transmit_underrun() __aic_transmit_underrun()
5802#define __ac97_receive_overrun() __aic_receive_overrun()
5803
5804#define __ac97_clear_errors() __aic_clear_errors()
5805
5806#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
5807#define __ac97_get_receive_count() __aic_get_receive_count()
5808
5809#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
5810#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
5811#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
5812#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
5813
5814#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
5815#define __ac97_read_rfifo() __aic_read_rfifo()
5816
5817//
5818// Define next ops for I2S compatible
5819//
5820
5821#define I2S_ACSR AIC_I2SSR
5822
5823#define __i2s_enable() __aic_enable(); __aic_select_i2s()
5824#define __i2s_disable() __aic_disable()
5825#define __i2s_reset() __aic_reset()
5826
5827#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
5828#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
5829
5830#define __i2s_enable_record() __aic_enable_record()
5831#define __i2s_disable_record() __aic_disable_record()
5832#define __i2s_enable_replay() __aic_enable_replay()
5833#define __i2s_disable_replay() __aic_disable_replay()
5834#define __i2s_enable_loopback() __aic_enable_loopback()
5835#define __i2s_disable_loopback() __aic_disable_loopback()
5836
5837#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
5838#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
5839#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
5840#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
5841
5842#define __i2s_transmit_request() __aic_transmit_request()
5843#define __i2s_receive_request() __aic_receive_request()
5844#define __i2s_transmit_underrun() __aic_transmit_underrun()
5845#define __i2s_receive_overrun() __aic_receive_overrun()
5846
5847#define __i2s_clear_errors() __aic_clear_errors()
5848
5849#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
5850#define __i2s_get_receive_count() __aic_get_receive_count()
5851
5852#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
5853#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
5854#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
5855#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
5856
5857#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
5858#define __i2s_read_rfifo() __aic_read_rfifo()
5859
5860#define __i2s_reset_codec() \
5861 do { \
5862 } while (0)
5863
5864
5865/***************************************************************************
5866 * ICDC
5867 ***************************************************************************/
5868#define __i2s_internal_codec() __aic_internal_codec()
5869#define __i2s_external_codec() __aic_external_codec()
5870
5871/***************************************************************************
5872 * INTC
5873 ***************************************************************************/
5874#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
5875#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
5876#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
5877
5878/***************************************************************************
5879 * I2C
5880 ***************************************************************************/
5881
5882#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
5883#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
5884
5885#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
5886#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
5887#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
5888#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
5889
5890#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
5891#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
5892#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
5893
5894#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
5895#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
5896#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
5897
5898#define __i2c_set_clk(dev_clk, i2c_clk) \
5899  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
5900
5901#define __i2c_read() ( REG_I2C_DR )
5902#define __i2c_write(val) ( REG_I2C_DR = (val) )
5903
5904
5905/***************************************************************************
5906 * MSC
5907 ***************************************************************************/
5908
5909#define __msc_start_op() \
5910  ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
5911
5912#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
5913#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
5914#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
5915#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
5916#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
5917#define __msc_get_nob() ( REG_MSC_NOB )
5918#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
5919#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
5920#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
5921#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
5922
5923#define __msc_set_cmdat_bus_width1() \
5924do { \
5925    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
5926    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
5927} while(0)
5928
5929#define __msc_set_cmdat_bus_width4() \
5930do { \
5931    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
5932    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
5933} while(0)
5934
5935#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
5936#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
5937#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
5938#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
5939#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
5940#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
5941#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
5942#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
5943
5944/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
5945#define __msc_set_cmdat_res_format(r) \
5946do { \
5947    REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
5948    REG_MSC_CMDAT |= (r); \
5949} while(0)
5950
5951#define __msc_clear_cmdat() \
5952  REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
5953  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
5954  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
5955
5956#define __msc_get_imask() ( REG_MSC_IMASK )
5957#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
5958#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
5959#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
5960#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
5961#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
5962#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
5963#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
5964#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
5965#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
5966#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
5967#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
5968#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
5969
5970/* n=0,1,2,3,4,5,6,7 */
5971#define __msc_set_clkrt(n) \
5972do { \
5973    REG_MSC_CLKRT = n; \
5974} while(0)
5975
5976#define __msc_get_ireg() ( REG_MSC_IREG )
5977#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
5978#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
5979#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
5980#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
5981#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
5982#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
5983#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
5984#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
5985
5986#define __msc_get_stat() ( REG_MSC_STAT )
5987#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
5988#define __msc_stat_crc_err() \
5989  ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
5990#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
5991#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
5992#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
5993#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
5994#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
5995
5996#define __msc_rd_resfifo() ( REG_MSC_RES )
5997#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
5998#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
5999
6000#define __msc_reset() \
6001do { \
6002    REG_MSC_STRPCL = MSC_STRPCL_RESET; \
6003     while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
6004} while (0)
6005
6006#define __msc_start_clk() \
6007do { \
6008    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
6009} while (0)
6010
6011#define __msc_stop_clk() \
6012do { \
6013    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
6014} while (0)
6015
6016#define MMC_CLK 19169200
6017#define SD_CLK 24576000
6018
6019/* msc_clk should little than pclk and little than clk retrieve from card */
6020#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
6021do { \
6022    unsigned int rate, pclk, i; \
6023    pclk = dev_clk; \
6024    rate = type?SD_CLK:MMC_CLK; \
6025      if (msc_clk && msc_clk < pclk) \
6026            pclk = msc_clk; \
6027    i = 0; \
6028      while (pclk < rate) \
6029        { \
6030              i ++; \
6031              rate >>= 1; \
6032        } \
6033      lv = i; \
6034} while(0)
6035
6036/* divide rate to little than or equal to 400kHz */
6037#define __msc_calc_slow_clk_divisor(type, lv) \
6038do { \
6039    unsigned int rate, i; \
6040    rate = (type?SD_CLK:MMC_CLK)/1000/400; \
6041    i = 0; \
6042    while (rate > 0) \
6043        { \
6044              rate >>= 1; \
6045              i ++; \
6046        } \
6047      lv = i; \
6048} while(0)
6049
6050
6051/***************************************************************************
6052 * SSI (Synchronous Serial Interface)
6053 ***************************************************************************/
6054/* n = 0, 1 (SSI0, SSI1) */
6055#define __ssi_enable(n) ( REG_SSI_CR0(n) |= SSI_CR0_SSIE )
6056#define __ssi_disable(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_SSIE )
6057#define __ssi_select_ce(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_FSEL )
6058
6059#define __ssi_normal_mode(n) ( REG_SSI_ITR(n) &= ~SSI_ITR_IVLTM_MASK )
6060
6061#define __ssi_select_ce2(n) \
6062do { \
6063    REG_SSI_CR0(n) |= SSI_CR0_FSEL; \
6064    REG_SSI_CR1(n) &= ~SSI_CR1_MULTS; \
6065} while (0)
6066
6067#define __ssi_select_gpc(n) \
6068do { \
6069    REG_SSI_CR0(n) &= ~SSI_CR0_FSEL; \
6070    REG_SSI_CR1(n) |= SSI_CR1_MULTS; \
6071} while (0)
6072
6073#define __ssi_underrun_auto_clear(n) \
6074do { \
6075    REG_SSI_CR0(n) |= SSI_CR0_EACLRUN; \
6076} while (0)
6077
6078#define __ssi_underrun_clear_manually(n) \
6079do { \
6080    REG_SSI_CR0(n) &= ~SSI_CR0_EACLRUN; \
6081} while (0)
6082
6083#define __ssi_enable_tx_intr(n) \
6084    ( REG_SSI_CR0(n) |= SSI_CR0_TIE | SSI_CR0_TEIE )
6085
6086#define __ssi_disable_tx_intr(n) \
6087    ( REG_SSI_CR0(n) &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
6088
6089#define __ssi_enable_rx_intr(n) \
6090    ( REG_SSI_CR0(n) |= SSI_CR0_RIE | SSI_CR0_REIE )
6091
6092#define __ssi_disable_rx_intr(n) \
6093    ( REG_SSI_CR0(n) &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
6094
6095#define __ssi_enable_txfifo_half_empty_intr(n) \
6096    ( REG_SSI_CR0(n) |= SSI_CR0_TIE )
6097#define __ssi_disable_txfifo_half_empty_intr(n) \
6098    ( REG_SSI_CR0(n) &= ~SSI_CR0_TIE )
6099#define __ssi_enable_tx_error_intr(n) \
6100    ( REG_SSI_CR0(n) |= SSI_CR0_TEIE )
6101#define __ssi_disable_tx_error_intr(n) \
6102    ( REG_SSI_CR0(n) &= ~SSI_CR0_TEIE )
6103#define __ssi_enable_rxfifo_half_full_intr(n) \
6104    ( REG_SSI_CR0(n) |= SSI_CR0_RIE )
6105#define __ssi_disable_rxfifo_half_full_intr(n) \
6106    ( REG_SSI_CR0(n) &= ~SSI_CR0_RIE )
6107#define __ssi_enable_rx_error_intr(n) \
6108    ( REG_SSI_CR0(n) |= SSI_CR0_REIE )
6109#define __ssi_disable_rx_error_intr(n) \
6110    ( REG_SSI_CR0(n) &= ~SSI_CR0_REIE )
6111
6112#define __ssi_enable_loopback(n) ( REG_SSI_CR0(n) |= SSI_CR0_LOOP )
6113#define __ssi_disable_loopback(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_LOOP )
6114
6115#define __ssi_enable_receive(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_DISREV )
6116#define __ssi_disable_receive(n) ( REG_SSI_CR0(n) |= SSI_CR0_DISREV )
6117
6118#define __ssi_finish_receive(n) \
6119    ( REG_SSI_CR0(n) |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
6120
6121#define __ssi_disable_recvfinish(n) \
6122    ( REG_SSI_CR0(n) &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
6123
6124#define __ssi_flush_txfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH )
6125#define __ssi_flush_rxfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_RFLUSH )
6126
6127#define __ssi_flush_fifo(n) \
6128    ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
6129
6130#define __ssi_finish_transmit(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_UNFIN )
6131#define __ssi_wait_transmit(n) ( REG_SSI_CR1(n) |= SSI_CR1_UNFIN )
6132#define __ssi_use_busy_wait_mode(n) __ssi_wait_transmit(n)
6133#define __ssi_unset_busy_wait_mode(n) __ssi_finish_transmit(n)
6134
6135#define __ssi_spi_format(n) \
6136    do { \
6137        REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \
6138        REG_SSI_CR1(n) |= SSI_CR1_FMAT_SPI; \
6139        REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
6140        REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
6141    } while (0)
6142
6143/* TI's SSP format, must clear SSI_CR1.UNFIN */
6144#define __ssi_ssp_format(n) \
6145    do { \
6146        REG_SSI_CR1(n) &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
6147        REG_SSI_CR1(n) |= SSI_CR1_FMAT_SSP; \
6148    } while (0)
6149
6150/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
6151#define __ssi_microwire_format(n) \
6152    do { \
6153        REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \
6154        REG_SSI_CR1(n) |= SSI_CR1_FMAT_MW1; \
6155        REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \
6156        REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
6157        REG_SSI_CR0(n) &= ~SSI_CR0_RFINE; \
6158    } while (0)
6159
6160/* CE# level (FRMHL), CE# in interval time (ITFRM),
6161   clock phase and polarity (PHA POL),
6162   interval time (SSIITR), interval characters/frame (SSIICR) */
6163
6164/* frmhl,endian,mcom,flen,pha,pol MASK */
6165#define SSICR1_MISC_MASK \
6166    ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
6167      | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )
6168
6169#define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol) \
6170    do { \
6171        REG_SSI_CR1(n) &= ~SSICR1_MISC_MASK; \
6172        REG_SSI_CR1(n) |= ((frmhl) << 30) | ((endian) << 25) | \
6173            (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
6174            ((pha) << 1) | (pol); \
6175    } while(0)
6176
6177/* Transfer with MSB or LSB first */
6178#define __ssi_set_msb(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_LFST )
6179#define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST )
6180
6181#define __ssi_set_frame_length(n, m) \
6182    REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4)
6183
6184/* m = 1 - 16 */
6185#define __ssi_set_microwire_command_length(n,m) \
6186    ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##m##BIT) )
6187
6188/* Set the clock phase for SPI */
6189#define __ssi_set_spi_clock_phase(n, m) \
6190    ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_PHA) | (((m)&0x1)<< 1)))
6191
6192/* Set the clock polarity for SPI */
6193#define __ssi_set_spi_clock_polarity(n, p) \
6194    ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_POL) | ((p)&0x1)) )
6195
6196/* SSI tx trigger, m = i x 8 */
6197#define __ssi_set_tx_trigger(n, m) \
6198    do { \
6199        REG_SSI_CR1(n) &= ~SSI_CR1_TTRG_MASK; \
6200        REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_TTRG_BIT; \
6201    } while (0)
6202
6203/* SSI rx trigger, m = i x 8 */
6204#define __ssi_set_rx_trigger(n, m) \
6205    do { \
6206        REG_SSI_CR1(n) &= ~SSI_CR1_RTRG_MASK; \
6207        REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_RTRG_BIT; \
6208    } while (0)
6209
6210#define __ssi_get_txfifo_count(n) \
6211    ( (REG_SSI_SR(n) & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
6212
6213#define __ssi_get_rxfifo_count(n) \
6214    ( (REG_SSI_SR(n) & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
6215
6216#define __ssi_transfer_end(n) ( REG_SSI_SR(n) & SSI_SR_END )
6217#define __ssi_is_busy(n) ( REG_SSI_SR(n) & SSI_SR_BUSY )
6218
6219#define __ssi_txfifo_full(n) ( REG_SSI_SR(n) & SSI_SR_TFF )
6220#define __ssi_rxfifo_empty(n) ( REG_SSI_SR(n) & SSI_SR_RFE )
6221#define __ssi_rxfifo_half_full(n) ( REG_SSI_SR(n) & SSI_SR_RFHF )
6222#define __ssi_txfifo_half_empty(n) ( REG_SSI_SR(n) & SSI_SR_TFHE )
6223#define __ssi_underrun(n) ( REG_SSI_SR(n) & SSI_SR_UNDR )
6224#define __ssi_overrun(n) ( REG_SSI_SR(n) & SSI_SR_OVER )
6225#define __ssi_clear_underrun(n) ( REG_SSI_SR(n) = ~SSI_SR_UNDR )
6226#define __ssi_clear_overrun(n) ( REG_SSI_SR(n) = ~SSI_SR_OVER )
6227#define __ssi_clear_errors(n) ( REG_SSI_SR(n) &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
6228
6229#define __ssi_set_clk(n, dev_clk, ssi_clk) \
6230    ( REG_SSI_GR(n) = (dev_clk) / (2*(ssi_clk)) - 1 )
6231
6232#define __ssi_receive_data(n) REG_SSI_DR(n)
6233#define __ssi_transmit_data(n, v) (REG_SSI_DR(n) = (v))
6234
6235
6236/***************************************************************************
6237 * CIM
6238 ***************************************************************************/
6239
6240#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
6241#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
6242
6243#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
6244#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
6245
6246#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
6247#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
6248
6249#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
6250#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
6251
6252#define __cim_sample_data_at_pclk_falling_edge() \
6253  ( REG_CIM_CFG |= CIM_CFG_PCP )
6254#define __cim_sample_data_at_pclk_rising_edge() \
6255  ( REG_CIM_CFG &= ~CIM_CFG_PCP )
6256
6257#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
6258#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
6259
6260#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
6261#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
6262
6263/* n=0-7 */
6264#define __cim_set_data_packing_mode(n) \
6265do { \
6266    REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
6267    REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
6268} while (0)
6269
6270#define __cim_enable_ccir656_progressive_mode() \
6271do { \
6272    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
6273    REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
6274} while (0)
6275
6276#define __cim_enable_ccir656_interlace_mode() \
6277do { \
6278    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
6279    REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
6280} while (0)
6281
6282#define __cim_enable_gated_clock_mode() \
6283do { \
6284    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
6285    REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
6286} while (0)
6287
6288#define __cim_enable_nongated_clock_mode() \
6289do { \
6290    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
6291    REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
6292} while (0)
6293
6294/* sclk:system bus clock
6295 * mclk: CIM master clock
6296 */
6297#define __cim_set_master_clk(sclk, mclk) \
6298do { \
6299    REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
6300    REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
6301} while (0)
6302
6303#define __cim_enable_sof_intr() \
6304  ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
6305#define __cim_disable_sof_intr() \
6306  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
6307
6308#define __cim_enable_eof_intr() \
6309  ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
6310#define __cim_disable_eof_intr() \
6311  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
6312
6313#define __cim_enable_stop_intr() \
6314  ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
6315#define __cim_disable_stop_intr() \
6316  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
6317
6318#define __cim_enable_trig_intr() \
6319  ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
6320#define __cim_disable_trig_intr() \
6321  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
6322
6323#define __cim_enable_rxfifo_overflow_intr() \
6324  ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
6325#define __cim_disable_rxfifo_overflow_intr() \
6326  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
6327
6328/* n=1-16 */
6329#define __cim_set_frame_rate(n) \
6330do { \
6331    REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
6332    REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
6333} while (0)
6334
6335#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
6336#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
6337
6338#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
6339#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
6340
6341/* n=4,8,12,16,20,24,28,32 */
6342#define __cim_set_rxfifo_trigger(n) \
6343do { \
6344    REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
6345    REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
6346} while (0)
6347
6348#define __cim_clear_state() ( REG_CIM_STATE = 0 )
6349
6350#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
6351#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
6352#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
6353#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
6354#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
6355#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
6356#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
6357#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
6358
6359#define __cim_get_iid() ( REG_CIM_IID )
6360#define __cim_get_image_data() ( REG_CIM_RXFIFO )
6361#define __cim_get_dam_cmd() ( REG_CIM_CMD )
6362
6363#define __cim_set_da(a) ( REG_CIM_DA = (a) )
6364
6365/***************************************************************************
6366 * LCD
6367 ***************************************************************************/
6368#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
6369#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
6370
6371#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
6372#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
6373
6374#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
6375#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
6376
6377/* n=1,2,4,8,16 */
6378#define __lcd_set_bpp(n) \
6379  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
6380
6381/* n=4,8,16 */
6382#define __lcd_set_burst_length(n) \
6383do { \
6384    REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
6385    REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
6386} while (0)
6387
6388#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
6389#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
6390
6391#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
6392#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
6393
6394/* n=2,4,16 */
6395#define __lcd_set_stn_frc(n) \
6396do { \
6397    REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
6398    REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
6399} while (0)
6400
6401
6402#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
6403#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
6404
6405#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
6406#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
6407
6408#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
6409#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
6410
6411#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
6412#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
6413
6414#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
6415#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
6416
6417#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
6418#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
6419
6420#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
6421#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
6422
6423#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
6424#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
6425
6426#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
6427#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
6428
6429
6430/* LCD status register indication */
6431
6432#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
6433#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
6434#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
6435#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
6436#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
6437#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
6438#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
6439
6440#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
6441#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
6442#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
6443
6444#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
6445#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
6446
6447/* n=1,2,4,8 for single mono-STN
6448 * n=4,8 for dual mono-STN
6449 */
6450#define __lcd_set_panel_datawidth(n) \
6451do { \
6452    REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
6453    REG_LCD_CFG |= LCD_CFG_PDW_n##; \
6454} while (0)
6455
6456/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
6457#define __lcd_set_panel_mode(m) \
6458do { \
6459    REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
6460    REG_LCD_CFG |= (m); \
6461} while(0)
6462
6463/* n = 0-255 */
6464#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
6465#define __lcd_set_ac_bias(n) \
6466do { \
6467    REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
6468    REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
6469} while(0)
6470
6471#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
6472#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
6473
6474#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
6475#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
6476
6477#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
6478#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
6479
6480#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
6481#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
6482
6483#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
6484#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
6485
6486#define __lcd_vsync_get_vps() \
6487  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
6488
6489#define __lcd_vsync_get_vpe() \
6490  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
6491#define __lcd_vsync_set_vpe(n) \
6492do { \
6493    REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
6494    REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
6495} while (0)
6496
6497#define __lcd_hsync_get_hps() \
6498  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
6499#define __lcd_hsync_set_hps(n) \
6500do { \
6501    REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
6502    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
6503} while (0)
6504
6505#define __lcd_hsync_get_hpe() \
6506  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
6507#define __lcd_hsync_set_hpe(n) \
6508do { \
6509    REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
6510    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
6511} while (0)
6512
6513#define __lcd_vat_get_ht() \
6514  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
6515#define __lcd_vat_set_ht(n) \
6516do { \
6517    REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
6518    REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
6519} while (0)
6520
6521#define __lcd_vat_get_vt() \
6522  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
6523#define __lcd_vat_set_vt(n) \
6524do { \
6525    REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
6526    REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
6527} while (0)
6528
6529#define __lcd_dah_get_hds() \
6530  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
6531#define __lcd_dah_set_hds(n) \
6532do { \
6533    REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
6534    REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
6535} while (0)
6536
6537#define __lcd_dah_get_hde() \
6538  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
6539#define __lcd_dah_set_hde(n) \
6540do { \
6541    REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
6542    REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
6543} while (0)
6544
6545#define __lcd_dav_get_vds() \
6546  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
6547#define __lcd_dav_set_vds(n) \
6548do { \
6549    REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
6550    REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
6551} while (0)
6552
6553#define __lcd_dav_get_vde() \
6554  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
6555#define __lcd_dav_set_vde(n) \
6556do { \
6557    REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
6558    REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
6559} while (0)
6560
6561#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
6562#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
6563#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
6564#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
6565
6566#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
6567#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
6568#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
6569#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
6570
6571#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
6572#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
6573
6574#define __lcd_cmd0_get_len() \
6575  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
6576#define __lcd_cmd1_get_len() \
6577  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
6578
6579/***************************************************************************
6580 * RTC ops
6581 ***************************************************************************/
6582
6583#define __rtc_write_ready() (REG_RTC_RCR & RTC_RCR_WRDY)
6584#define __rtc_write_enabled() (REG_RTC_WENR & RTC_WENR_WEN)
6585#define __rtc_write_enable() (REG_RTC_WENR |= (0xA55A << RTC_WENR_WENPAT_BIT))
6586#define __rtc_write_disable() (REG_RTC_WENR &= ~RTC_WENR_WENPAT_MASK)
6587
6588#define __rtc_enabled() \
6589do{ \
6590      while(!__rtc_write_ready()); \
6591      REG_RTC_RCR |= RTC_RCR_RTCE ; \
6592}while(0) \
6593
6594#define __rtc_disabled() \
6595do{ \
6596      while(!__rtc_write_ready()); \
6597      REG_RTC_RCR &= ~RTC_RCR_RTCE; \
6598}while(0)
6599#define __rtc_enable_alarm() \
6600do{ \
6601      while(!__rtc_write_ready()); \
6602      REG_RTC_RCR |= RTC_RCR_AE; \
6603}while(0)
6604
6605#define __rtc_disable_alarm() \
6606do{ \
6607      while(!__rtc_write_ready()); \
6608      REG_RTC_RCR &= ~RTC_RCR_AE; \
6609}while(0)
6610
6611#define __rtc_enable_alarm_irq() \
6612do{ \
6613      while(!__rtc_write_ready()); \
6614      REG_RTC_RCR |= RTC_RCR_AIE; \
6615}while(0)
6616
6617#define __rtc_disable_alarm_irq() \
6618do{ \
6619      while(!__rtc_write_ready()); \
6620      REG_RTC_RCR &= ~RTC_RCR_AIE; \
6621}while(0)
6622#define __rtc_enable_Hz_irq() \
6623do{ \
6624      while(!__rtc_write_ready()); \
6625      REG_RTC_RCR |= RTC_RCR_HZIE; \
6626}while(0)
6627
6628#define __rtc_disable_Hz_irq() \
6629do{ \
6630      while(!__rtc_write_ready()); \
6631      REG_RTC_RCR &= ~RTC_RCR_HZIE; \
6632}while(0)
6633#define __rtc_get_1Hz_flag() \
6634do{ \
6635      while(!__rtc_write_ready()); \
6636      ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
6637}while(0)
6638#define __rtc_clear_1Hz_flag() \
6639do{ \
6640      while(!__rtc_write_ready()); \
6641      REG_RTC_RCR &= ~RTC_RCR_HZ; \
6642}while(0)
6643#define __rtc_get_alarm_flag() \
6644do{ \
6645       while(!__rtc_write_ready()); \
6646      ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \
6647while(0)
6648#define __rtc_clear_alarm_flag() \
6649do{ \
6650      while(!__rtc_write_ready()); \
6651      REG_RTC_RCR &= ~RTC_RCR_AF; \
6652}while(0)
6653#define __rtc_get_second() \
6654do{ \
6655       while(!__rtc_write_ready());\
6656       REG_RTC_RSR; \
6657}while(0)
6658 
6659#define __rtc_set_second(v) \
6660do{ \
6661      while(!__rtc_write_ready()); \
6662      REG_RTC_RSR = v; \
6663}while(0)
6664
6665#define __rtc_get_alarm_second() \
6666do{ \
6667      while(!__rtc_write_ready()); \
6668      REG_RTC_RSAR; \
6669}while(0)
6670
6671      
6672#define __rtc_set_alarm_second(v) \
6673do{ \
6674      while(!__rtc_write_ready()); \
6675      REG_RTC_RSAR = v; \
6676}while(0)
6677
6678#define __rtc_RGR_is_locked() \
6679do{ \
6680      while(!__rtc_write_ready()); \
6681      REG_RTC_RGR >> RTC_RGR_LOCK; \
6682}while(0)
6683#define __rtc_lock_RGR() \
6684do{ \
6685      while(!__rtc_write_ready()); \
6686      REG_RTC_RGR |= RTC_RGR_LOCK; \
6687}while(0)
6688
6689#define __rtc_unlock_RGR() \
6690do{ \
6691      while(!__rtc_write_ready()); \
6692      REG_RTC_RGR &= ~RTC_RGR_LOCK; \
6693}while(0)
6694
6695#define __rtc_get_adjc_val() \
6696do{ \
6697      while(!__rtc_write_ready()); \
6698      ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
6699}while(0)
6700#define __rtc_set_adjc_val(v) \
6701do{ \
6702      while(!__rtc_write_ready()); \
6703      ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \
6704}while(0)
6705
6706#define __rtc_get_nc1Hz_val() \
6707      while(!__rtc_write_ready()); \
6708      ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
6709      
6710#define __rtc_set_nc1Hz_val(v) \
6711do{ \
6712      while(!__rtc_write_ready()); \
6713      ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \
6714}while(0)
6715#define __rtc_power_down() \
6716do{ \
6717      while(!__rtc_write_ready()); \
6718      REG_RTC_HCR |= RTC_HCR_PD; \
6719}while(0)
6720
6721#define __rtc_get_hwfcr_val() \
6722do{ \
6723      while(!__rtc_write_ready()); \
6724      REG_RTC_HWFCR & RTC_HWFCR_MASK; \
6725}while(0)
6726#define __rtc_set_hwfcr_val(v) \
6727do{ \
6728      while(!__rtc_write_ready()); \
6729      REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \
6730}while(0)
6731
6732#define __rtc_get_hrcr_val() \
6733do{ \
6734      while(!__rtc_write_ready()); \
6735      ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
6736}while(0)
6737#define __rtc_set_hrcr_val(v) \
6738do{ \
6739      while(!__rtc_write_ready()); \
6740      ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \
6741}while(0)
6742
6743#define __rtc_enable_alarm_wakeup() \
6744do{ \
6745      while(!__rtc_write_ready()); \
6746      ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \
6747}while(0)
6748
6749#define __rtc_disable_alarm_wakeup() \
6750do{ \
6751      while(!__rtc_write_ready()); \
6752      ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \
6753}while(0)
6754
6755#define __rtc_status_hib_reset_occur() \
6756do{ \
6757      while(!__rtc_write_ready()); \
6758    ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \
6759}while(0)
6760#define __rtc_status_ppr_reset_occur() \
6761do{ \
6762      while(!__rtc_write_ready()); \
6763   ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \
6764}while(0)
6765#define __rtc_status_wakeup_pin_waken_up() \
6766do{ \
6767      while(!__rtc_write_ready()); \
6768   ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
6769}while(0)
6770#define __rtc_status_alarm_waken_up() \
6771do{ \
6772      while(!__rtc_write_ready()); \
6773  ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
6774}while(0)
6775#define __rtc_clear_hib_stat_all() \
6776do{ \
6777      while(!__rtc_write_ready()); \
6778      ( REG_RTC_HWRSR = 0 ); \
6779}while(0)
6780
6781#define __rtc_get_scratch_pattern() \
6782      while(!__rtc_write_ready()); \
6783          (REG_RTC_HSPR)
6784#define __rtc_set_scratch_pattern(n) \
6785do{ \
6786      while(!__rtc_write_ready()); \
6787      (REG_RTC_HSPR = n ); \
6788}while(0)
6789
6790/*************************************************************************
6791 * BCH
6792 *************************************************************************/
6793#define __ecc_encoding_4bit() \
6794do { \
6795    REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6796    REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6797} while(0)
6798#define __ecc_decoding_4bit() \
6799do { \
6800    REG_BCH_CRS = BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6801    REG_BCH_CRC = ~(BCH_CR_BSEL_4 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6802} while(0)
6803#define __ecc_encoding_8bit() \
6804do { \
6805    REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6806    REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6807} while(0)
6808#define __ecc_decoding_8bit() \
6809do { \
6810    REG_BCH_CRS = BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6811    REG_BCH_CRC = ~(BCH_CR_BSEL_8 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6812} while(0)
6813#define __ecc_encoding_12bit() \
6814do { \
6815    REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6816    REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6817} while(0)
6818#define __ecc_decoding_12bit() \
6819do { \
6820    REG_BCH_CRS = BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6821    REG_BCH_CRC = ~(BCH_CR_BSEL_12 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6822} while(0)
6823#define __ecc_encoding_16bit() \
6824do { \
6825    REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6826    REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6827} while(0)
6828#define __ecc_decoding_16bit() \
6829do { \
6830    REG_BCH_CRS = BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6831    REG_BCH_CRC = ~(BCH_CR_BSEL_16 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6832} while(0)
6833#define __ecc_encoding_20bit() \
6834do { \
6835    REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6836    REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6837} while(0)
6838#define __ecc_decoding_20bit() \
6839do { \
6840    REG_BCH_CRS = BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6841    REG_BCH_CRC = ~(BCH_CR_BSEL_20 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6842} while(0)
6843#define __ecc_encoding_24bit() \
6844do { \
6845    REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE; \
6846    REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_ENCE | BCH_CR_BRST | BCH_CR_BCHE); \
6847} while(0)
6848#define __ecc_decoding_24bit() \
6849do { \
6850    REG_BCH_CRS = BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE; \
6851    REG_BCH_CRC = ~(BCH_CR_BSEL_24 | BCH_CR_DECE | BCH_CR_BRST | BCH_CR_BCHE); \
6852} while(0)
6853
6854#define __ecc_dma_enable() ( REG_BCH_CRS = BCH_CR_DMAE )
6855#define __ecc_dma_disable() ( REG_BCH_CRC = BCH_CR_DMAE )
6856#define __ecc_disable() ( REG_BCH_CRC = BCH_CR_BCHE )
6857#define __ecc_encode_sync() while (!(REG_BCH_INTS & BCH_INTS_ENCF))
6858#define __ecc_decode_sync() while (!(REG_BCH_INTS & BCH_INTS_DECF))
6859
6860#define __ecc_cnt_dec(n) \
6861do { \
6862        REG_BCH_CNT &= ~BCH_CNT_DEC_MASK; \
6863        REG_BCH_CNT |= (n) << BCH_CNT_DEC_BIT; \
6864} while(0)
6865#define __ecc_cnt_enc(n) \
6866do { \
6867        REG_BCH_CNT &= ~BCH_CNT_ENC_MASK; \
6868        REG_BCH_CNT |= (n) << BCH_CNT_ENC_BIT; \
6869} while(0)
6870
6871#endif /* !__ASSEMBLY__ */
6872
6873#endif /* __JZ4760_H__ */
6874

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