Xué video camera

Xué video camera Commit Details

Date:	2010-12-31 16:38:16 (12 years 9 months ago)
Author:	Andrés Calderón
Commit:	eea70b29e40ee2a3cda0d272e590718f148b9beb
Message:	power jack has been added
Files:	BOOKSHELF (1 diff) components/pasives-connectors.lib (3 diffs) xue-rnc/ether.sch (2 diffs) xue-rnc/expansion.sch (2 diffs) xue-rnc/flash.sch (7 diffs) xue-rnc/fpga1.sch (18 diffs) xue-rnc/fpga2.sch (4 diffs) xue-rnc/psu.sch (28 diffs) xue-rnc/sdram.sch (9 diffs) xue-rnc/usb.sch (10 diffs) xue-rnc/xue-rnc.brd (287 diffs) xue-rnc/xue-rnc.cmp (3 diffs) xue-rnc/xue-rnc.net (56 diffs) xue-rnc/xue-rnc.pro (3 diffs) xue-rnc/xue-rnc.sch (2 diffs)

Change Details

BOOKSHELF
95	95	A: U13
96	96	D: http://focus.ti.com/lit/ds/symlink/bq24071.pdf
97	97
	98	N: PJ-031CH
	99	A: J8
	100	D: http://products.cui.com/getPDF.aspx?filename=PJ-031CH.pdf

components/pasives-connectors.lib
1		EESchema-LIBRARY Version 2.3 Date: Tue 10 Aug 2010 04:58:24 PM COT
	1	EESchema-LIBRARY Version 2.3 Date: Fri 31 Dec 2010 09:39:59 AM COT
2	2	#
3		# C
	3	# Cap
4	4	#
5		DEF C C 0 10 N Y 1 F N
	5	DEF Cap C 0 10 N Y 1 F N
6	6	F0 "C" 50 100 50 H V L CNN
7	7	F1 "Cap" 50 -100 50 H V L CNN
8	8	$FPLIST
...	...
19	19	ENDDRAW
20	20	ENDDEF
21	21	#
22		#
23	22	# FAN4010
24	23	#
25	24	DEF FAN4010 U 0 40 Y Y 1 F N
...	...
36	35	ENDDRAW
37	36	ENDDEF
38	37	#
	38	# PJ
	39	#
	40	DEF PJ J 0 20 Y Y 1 F N
	41	F0 "J" -200 -100 60 H V C CNN
	42	F1 "PJ" -200 300 60 H V C CNN
	43	DRAW
	44	A 300 175 25 -899 899 0 1 0 f 300 150 300 200
	45	P 5 0 1 0 -150 0 150 0 200 50 250 0 250 0 N
	46	P 5 0 1 0 300 150 -150 150 -150 200 300 200 300 200 f
	47	P 6 0 1 0 -250 250 -250 -50 -150 -50 -150 250 -250 250 -250 250 f
	48	P 6 0 1 0 -150 100 50 100 100 0 100 100 50 100 50 100 N
	49	X 1 1 -550 200 300 R 50 50 1 1 w
	50	X 2 2 -550 100 300 R 50 50 1 1 w
	51	X 3 3 -550 0 300 R 50 50 1 1 w
	52	ENDDRAW
	53	ENDDEF
	54	#
39	55	#End Library

xue-rnc/ether.sch
1		EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT
	1	EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT
2	2	LIBS:power
3	3	LIBS:r_pack2
4	4	LIBS:v0402mhs03
...	...
53	53	LIBS:fxo-hc536r
54	54	LIBS:zx62d-b-5p8
55	55	LIBS:a7130
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57	56	EELAYER 24 0
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60	59	Sheet 7 9
61	60	Title ""
62		Date "29 dec 2010"
	61	Date "31 dec 2010"
63	62	Rev ""
64	63	Comp ""
65	64	Comment1 ""

xue-rnc/expansion.sch
1		EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT
	1	EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT
2	2	LIBS:power
3	3	LIBS:r_pack2
4	4	LIBS:v0402mhs03
...	...
53	53	LIBS:fxo-hc536r
54	54	LIBS:zx62d-b-5p8
55	55	LIBS:a7130
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	61	Date "31 dec 2010"
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64	63	Comp ""
65	64	Comment1 ""

xue-rnc/flash.sch
1		EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT
	1	EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT
2	2	LIBS:power
3	3	LIBS:r_pack2
4	4	LIBS:v0402mhs03
...	...
53	53	LIBS:fxo-hc536r
54	54	LIBS:zx62d-b-5p8
55	55	LIBS:a7130
56		LIBS:xue-rnc-cache
57	56	EELAYER 24 0
58	57	EELAYER END
59	58	$Descr A4 11700 8267
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63	62	Rev ""
64	63	Comp ""
65	64	Comment1 ""
...	...
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...	...
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...	...
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369	368	P 7950 2900
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372	371	1 7950 2900
373	372	1 0 0 -1
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381	380	1 7950 3000
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	431	F 0 "#PWR18" H 3950 5800 30 0001 C CNN
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434	433	1 3950 5800
435	434	1 0 0 -1
...	...
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444		L GND #PWR057
	443	L GND #PWR20
445	444	U 1 1 4C438ADC
446	445	P 5800 6200
447		F 0 "#PWR057" H 5800 6200 30 0001 C CNN
	446	F 0 "#PWR20" H 5800 6200 30 0001 C CNN
448	447	F 1 "GND" H 5800 6130 30 0001 C CNN
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455	454	P 5350 6550
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458	457	1 5350 6550
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xue-rnc/fpga1.sch
1		EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT
	1	EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT
2	2	LIBS:power
3	3	LIBS:r_pack2
4	4	LIBS:v0402mhs03
...	...
53	53	LIBS:fxo-hc536r
54	54	LIBS:zx62d-b-5p8
55	55	LIBS:a7130
56		LIBS:xue-rnc-cache
57	56	EELAYER 24 0
58	57	EELAYER END
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60	59	Sheet 3 9
61	60	Title ""
62		Date "29 dec 2010"
	61	Date "31 dec 2010"
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64	63	Comp ""
65	64	Comment1 ""
...	...
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	1269	L GND #PWR95
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1276	1275	1 0 0 -1
...	...
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...	...
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	1294	L GND #PWR98
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	1297	F 0 "#PWR98" H 13750 7450 30 0001 C CNN
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1300	1299	1 13750 7450
1301	1300	1 0 0 -1
1302	1301	$EndComp
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	1303	L GND #PWR99
1305	1304	U 1 1 4CD34DC9
1306	1305	P 15050 6700
1307		F 0 "#PWR028" H 15050 6700 30 0001 C CNN
	1306	F 0 "#PWR99" H 15050 6700 30 0001 C CNN
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1309	1308	1 15050 6700
1310	1309	-1 0 0 1
...	...
1603	1602	Text Label 9250 7050 0 60 ~ 0
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	1605	L GND #PWR89
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1608	1607	P 4750 8950
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	1608	F 0 "#PWR89" H 4750 8950 30 0001 C CNN
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1611	1610	1 4750 8950
1612	1611	1 0 0 -1
...	...
1948	1947	1 0 0 -1
1949	1948	$EndComp
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1951		L +3.3V #PWR030
	1950	L +3.3V #PWR77
1952	1951	U 1 1 4C7168D5
1953	1952	P 650 6250
1954		F 0 "#PWR030" H 650 6210 30 0001 C CNN
	1953	F 0 "#PWR77" H 650 6210 30 0001 C CNN
1955	1954	F 1 "+3.3V" H 650 6360 30 0000 C CNN
1956	1955	1 650 6250
1957	1956	1 0 0 -1
1958	1957	$EndComp
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1965	1964	1 8450 6600
1966	1965	1 0 0 -1
...	...
1976	1975	1 0 0 -1
1977	1976	$EndComp
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1979		L GND #PWR032
	1978	L GND #PWR96
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1981	1980	P 8050 7350
1982		F 0 "#PWR032" H 8050 7350 30 0001 C CNN
	1981	F 0 "#PWR96" H 8050 7350 30 0001 C CNN
1983	1982	F 1 "GND" H 8050 7280 30 0001 C CNN
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1985	1984	1 0 0 -1
...	...
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2042		L +3.3V #PWR033
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2043	2042	U 1 1 4C65CF66
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	2044	F 0 "#PWR78" H 1100 9460 30 0001 C CNN
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2047	2046	1 1100 9500
2048	2047	1 0 0 -1
2049	2048	$EndComp
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	2050	L +2.5V #PWR85
2052	2051	U 1 1 4C65C84B
2053	2052	P 3550 10450
2054		F 0 "#PWR034" H 3550 10400 20 0001 C CNN
	2053	F 0 "#PWR85" H 3550 10400 20 0001 C CNN
2055	2054	F 1 "+2.5V" H 3550 10550 30 0000 C CNN
2056	2055	1 3550 10450
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2066	2065	1 0 0 -1
...	...
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2109	2108	$EndComp
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	2110	L GND #PWR81
2112	2111	U 1 1 4C656D9B
2113	2112	P 1100 11000
2114		F 0 "#PWR036" H 1100 11000 30 0001 C CNN
	2113	F 0 "#PWR81" H 1100 11000 30 0001 C CNN
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2116	2115	1 1100 11000
2117	2116	1 0 0 -1
...	...
2179	2178	1 0 0 -1
2180	2179	$EndComp
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	2181	L GND #PWR84
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2184	2183	P 3550 10100
2185		F 0 "#PWR037" H 3550 10100 30 0001 C CNN
	2184	F 0 "#PWR84" H 3550 10100 30 0001 C CNN
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2187	2186	1 3550 10100
2188	2187	1 0 0 -1
...	...
2240	2239	1 0 0 -1
2241	2240	$EndComp
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2248	2247	1 3550 11050
2249	2248	1 0 0 -1
...	...
2291	2290	1 0 0 -1
2292	2291	$EndComp
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2294		L GND #PWR039
	2293	L GND #PWR79
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2296	2295	P 1100 10100
2297		F 0 "#PWR039" H 1100 10100 30 0001 C CNN
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...	...
2344	2343	Text Notes 6050 10450 0 30 ~ 0
2345	2344	VCC_AUX Decoupling Capacitors (7)
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2347		L GND #PWR040
	2346	L GND #PWR94
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2349	2348	P 5950 11050
2350		F 0 "#PWR040" H 5950 11050 30 0001 C CNN
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2353	2352	1 0 0 -1
...	...
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2424	2423	$EndComp
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	2425	L +2.5V #PWR93
2427	2426	U 1 1 4C656BBA
2428	2427	P 5950 10450
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2431	2430	1 5950 10450
2432	2431	1 0 0 -1
2433	2432	$EndComp
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	2434	L GND #PWR92
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2437	2436	P 5950 10050
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2440	2439	1 5950 10050
2441	2440	1 0 0 -1
...	...
2473	2472	1 0 0 -1
2474	2473	$EndComp
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2476		L +1.2V #PWR043
	2475	L +1.2V #PWR91
2477	2476	U 1 1 4C656AA1
2478	2477	P 5950 9450
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...	...
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	2531	F 0 "#PWR87" H 3850 1760 30 0001 C CNN
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2534	2533	1 3850 1800
2535	2534	1 0 0 -1
2536	2535	$EndComp
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	2537	L +1.2V #PWR90
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	2540	F 0 "#PWR90" H 4850 6290 20 0001 C CNN
2542	2541	F 1 "+1.2V" H 4850 6260 30 0000 C CNN
2543	2542	1 4850 6150
2544	2543	1 0 0 -1
2545	2544	$EndComp
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2547		L +2.5V #PWR046
	2546	L +2.5V #PWR83
2548	2547	U 1 1 4C61E577
2549	2548	P 3350 6150
2550		F 0 "#PWR046" H 3350 6100 20 0001 C CNN
	2549	F 0 "#PWR83" H 3350 6100 20 0001 C CNN
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2552	2551	1 3350 6150
2553	2552	1 0 0 -1
...	...
2625	2624	Text HLabel 2150 4450 0 60 BiDi ~ 0
2626	2625	ETH_INT
2627	2626	$Comp
2628		L GND #PWR047
	2627	L GND #PWR88
2629	2628	U 1 1 4C439B7E
2630	2629	P 4000 8000
2631		F 0 "#PWR047" H 4000 8000 30 0001 C CNN
	2630	F 0 "#PWR88" H 4000 8000 30 0001 C CNN
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2633	2632	1 4000 8000
2634	2633	-1 0 0 -1

xue-rnc/fpga2.sch
1		EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT
	1	EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT
2	2	LIBS:power
3	3	LIBS:r_pack2
4	4	LIBS:v0402mhs03
...	...
53	53	LIBS:fxo-hc536r
54	54	LIBS:zx62d-b-5p8
55	55	LIBS:a7130
56		LIBS:xue-rnc-cache
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61	60	Title ""
62		Date "29 dec 2010"
	61	Date "31 dec 2010"
63	62	Rev ""
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65	64	Comment1 ""
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1568	1567	P 9200 6250
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	1568	F 0 "#PWR75" H 9200 6200 20 0001 C CNN
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1571	1570	1 9200 6250
1572	1571	1 0 0 -1
1573	1572	$EndComp
1574	1573	$Comp
1575		L +2.5V #PWR049
	1574	L +2.5V #PWR76
1576	1575	U 1 1 4C61E51F
1577	1576	P 9800 850
1578		F 0 "#PWR049" H 9800 800 20 0001 C CNN
	1577	F 0 "#PWR76" H 9800 800 20 0001 C CNN
1579	1578	F 1 "+2.5V" H 9800 950 30 0000 C CNN
1580	1579	1 9800 850
1581	1580	1 0 0 -1
...	...
1593	1592	Text HLabel 4700 9500 0 60 Output ~ 0
1594	1593	M1_CS#
1595	1594	$Comp
1596		L GND #PWR050
	1595	L GND #PWR74
1597	1596	U 1 1 4C60C21D
1598	1597	P 6250 5650
1599		F 0 "#PWR050" H 6250 5650 30 0001 C CNN
	1598	F 0 "#PWR74" H 6250 5650 30 0001 C CNN
1600	1599	F 1 "GND" H 6250 5580 30 0001 C CNN
1601	1600	1 6250 5650
1602	1601	-1 0 0 -1

xue-rnc/psu.sch
1		EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT
	1	EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT
2	2	LIBS:power
3	3	LIBS:r_pack2
4	4	LIBS:v0402mhs03
...	...
53	53	LIBS:fxo-hc536r
54	54	LIBS:zx62d-b-5p8
55	55	LIBS:a7130
56		LIBS:xue-rnc-cache
57	56	EELAYER 24 0
58	57	EELAYER END
59	58	$Descr A3 16535 11700
60	59	Sheet 2 9
61	60	Title ""
62		Date "29 dec 2010"
	61	Date "31 dec 2010"
63	62	Rev ""
64	63	Comp ""
65	64	Comment1 ""
...	...
67	66	Comment3 ""
68	67	Comment4 ""
69	68	$EndDescr
70		Text Notes 6800 3850 0 120 Italic 24
71		Design in progress!!!
72		Text Notes 6800 750 0 60 ~ 0
73		BQ24070\nLiPo Charger\nSingle-Cell Li-Ion- or Li-Polymer- battery \nSupports Up to 2 Amps Total Current
74	69	Wire Wire Line
75		11800 1850 14450 1850
	70	7150 4900 7150 5100
	71	Wire Wire Line
	72	7800 5100 7800 4800
	73	Connection ~ 7800 4900
	74	Wire Wire Line
	75	7950 4900 7800 4900
	76	Wire Wire Line
	77	14450 1850 11800 1850
76	78	Connection ~ 8400 1600
77	79	Wire Wire Line
78	80	8400 1450 8400 1700
...	...
84	86	12200 2600 11800 2600
85	87	Connection ~ 12050 3350
86	88	Wire Wire Line
87		12050 3350 12050 3450
	89	12050 3450 12050 3350
88	90	Connection ~ 10850 3250
89	91	Wire Wire Line
90	92	10850 3350 10850 3250
...	...
150	152	4850 9100 4850 10150
151	153	Connection ~ 2750 10150
152	154	Wire Wire Line
153		2750 10100 2750 10250
	155	2750 10250 2750 10100
154	156	Wire Wire Line
155	157	2500 10100 2500 10150
156	158	Wire Wire Line
...	...
158	160	Wire Wire Line
159	161	2400 10150 2400 10100
160	162	Wire Wire Line
161		1300 9100 850 9100
	163	850 9100 1300 9100
162	164	Connection ~ 3450 9400
163	165	Wire Wire Line
164	166	3450 9400 3450 9300
...	...
206	208	Connection ~ 4800 7250
207	209	Connection ~ 4800 7150
208	210	Wire Wire Line
209		4800 7250 4800 7150
	211	4800 7150 4800 7250
210	212	Wire Wire Line
211	213	4600 7300 4600 7250
212	214	Wire Wire Line
...	...
266	268	Wire Wire Line
267	269	2250 5050 2250 4950
268	270	Wire Wire Line
269		4300 4350 3300 4350
	271	3300 4350 4300 4350
270	272	Wire Wire Line
271	273	3300 3750 4200 3750
272	274	Connection ~ 3900 3650
...	...
442	444	1050 9200 1050 9100
443	445	Connection ~ 1050 9100
444	446	Wire Wire Line
445		1900 9100 2000 9100
	447	2000 9100 1900 9100
446	448	Wire Wire Line
447	449	2450 10250 2450 10150
448	450	Connection ~ 2450 10150
...	...
455	457	Wire Wire Line
456	458	3350 9700 3400 9700
457	459	Wire Wire Line
458		4150 9400 3350 9400
	460	3350 9400 4150 9400
459	461	Connection ~ 3950 9400
460	462	Wire Wire Line
461	463	4100 9650 4100 9850
...	...
474	476	Wire Wire Line
475	477	4850 10150 3750 10150
476	478	Wire Wire Line
477		3250 10150 2750 10150
	479	2750 10150 3250 10150
478	480	Wire Wire Line
479	481	4300 7300 4450 7150
480	482	Wire Wire Line
...	...
482	484	Wire Wire Line
483	485	12000 2050 11800 2050
484	486	Wire Wire Line
485		13100 2250 11800 2250
	487	11800 2250 13100 2250
486	488	Wire Wire Line
487	489	12950 2300 12950 2250
488	490	Connection ~ 12950 2250
...	...
533	535	13850 2550 13850 2400
534	536	Wire Wire Line
535	537	13850 1850 13850 2100
	538	Wire Wire Line
	539	7800 4800 7950 4800
	540	Wire Wire Line
	541	7800 4600 7800 4700
	542	Wire Wire Line
	543	7800 4700 7950 4700
	544	Wire Wire Line
	545	7150 4600 7150 4700
	546	Text GLabel 7150 4600 1 40 Input ~ 8
	547	Vin
	548	$Comp
	549	L GND #PWR66
	550	U 1 1 4D1DF63C
	551	P 7150 5100
	552	F 0 "#PWR66" H 7150 5100 30 0001 C CNN
	553	F 1 "GND" H 7150 5030 30 0001 C CNN
	554	1 7150 5100
	555	1 0 0 -1
	556	$EndComp
	557	$Comp
	558	L CAP C180
	559	U 1 1 4D1DF629
	560	P 7150 4800
	561	F 0 "C180" H 7200 4900 50 0000 L CNN
	562	F 1 "100nF" H 7200 4700 50 0000 L CNN
	563	F 2 "0402" H 7150 4800 60 0001 C CNN
	564	1 7150 4800
	565	1 0 0 -1
	566	$EndComp
	567	$Comp
	568	L GND #PWR67
	569	U 1 1 4D1DF611
	570	P 7800 5100
	571	F 0 "#PWR67" H 7800 5100 30 0001 C CNN
	572	F 1 "GND" H 7800 5030 30 0001 C CNN
	573	1 7800 5100
	574	1 0 0 -1
	575	$EndComp
	576	Text GLabel 7800 4600 1 40 Input ~ 8
	577	Vin
	578	$Comp
	579	L PJ J8
	580	U 1 1 4D1DF550
	581	P 8500 4900
	582	F 0 "J8" H 8300 4800 60 0000 C CNN
	583	F 1 "PJ" H 8300 5200 60 0000 C CNN
	584	F 2 "PJ-CUI-TH" H 8500 4900 60 0001 C CNN
	585	1 8500 4900
	586	1 0 0 -1
	587	$EndComp
	588	Text Notes 6800 3850 0 120 Italic 24
	589	Design in progress!!!
	590	Text Notes 6800 750 0 60 ~ 0
	591	BQ24070\nLiPo Charger\nSingle-Cell Li-Ion- or Li-Polymer- battery \nSupports Up to 2 Amps Total Current
536	592	$Comp
537	593	L CAP C178
538	594	U 1 1 4D1A14C5
...	...
554	610	1 0 0 -1
555	611	$EndComp
556	612	$Comp
557		L GND #PWR01
	613	L GND #PWR73
558	614	U 1 1 4D1A14C3
559	615	P 13850 2550
560		F 0 "#PWR01" H 13850 2550 30 0001 C CNN
	616	F 0 "#PWR73" H 13850 2550 30 0001 C CNN
561	617	F 1 "GND" H 13850 2480 30 0001 C CNN
562	618	1 13850 2550
563	619	1 0 0 -1
...	...
567	623	Text Notes 14250 3900 0 40 ~ 0
568	624	http://focus.ti.com/lit/ds/symlink/bq24071.pdf
569	625	$Comp
570		L GND #PWR02
	626	L GND #PWR69
571	627	U 1 1 4D1A13BE
572	628	P 9000 2700
573		F 0 "#PWR02" H 9000 2700 30 0001 C CNN
	629	F 0 "#PWR69" H 9000 2700 30 0001 C CNN
574	630	F 1 "GND" H 9000 2630 30 0001 C CNN
575	631	1 9000 2700
576	632	1 0 0 -1
...	...
586	642	1 0 0 -1
587	643	$EndComp
588	644	$Comp
589		L GND #PWR03
	645	L GND #PWR72
590	646	U 1 1 4D1A12B6
591	647	P 12950 2700
592		F 0 "#PWR03" H 12950 2700 30 0001 C CNN
	648	F 0 "#PWR72" H 12950 2700 30 0001 C CNN
593	649	F 1 "GND" H 12950 2630 30 0001 C CNN
594	650	1 12950 2700
595	651	1 0 0 -1
...	...
615	671	1 0 0 -1
616	672	$EndComp
617	673	$Comp
618		L GND #PWR04
	674	L GND #PWR71
619	675	U 1 1 4D1A120A
620	676	P 12050 3450
621		F 0 "#PWR04" H 12050 3450 30 0001 C CNN
	677	F 0 "#PWR71" H 12050 3450 30 0001 C CNN
622	678	F 1 "GND" H 12050 3380 30 0001 C CNN
623	679	1 12050 3450
624	680	1 0 0 -1
625	681	$EndComp
626	682	$Comp
627		L GND #PWR05
	683	L GND #PWR70
628	684	U 1 1 4D1A1204
629	685	P 10850 3350
630		F 0 "#PWR05" H 10850 3350 30 0001 C CNN
	686	F 0 "#PWR70" H 10850 3350 30 0001 C CNN
631	687	F 1 "GND" H 10850 3280 30 0001 C CNN
632	688	1 10850 3350
633	689	1 0 0 -1
...	...
643	699	1 0 0 -1
644	700	$EndComp
645	701	$Comp
646		L GND #PWR06
	702	L GND #PWR68
647	703	U 1 1 4D1A0FF8
648	704	P 8400 2150
649		F 0 "#PWR06" H 8400 2150 30 0001 C CNN
	705	F 0 "#PWR68" H 8400 2150 30 0001 C CNN
650	706	F 1 "GND" H 8400 2080 30 0001 C CNN
651	707	1 8400 2150
652	708	1 0 0 -1
...	...
698	754	Text Notes 5100 11100 0 40 Italic 0
699	755	http://www.national.com/ds/LM/LM2621.pdf
700	756	$Comp
701		L GND #PWR07
	757	L GND #PWR64
702	758	U 1 1 4D1409D1
703	759	P 5300 9650
704		F 0 "#PWR07" H 5300 9650 30 0001 C CNN
	760	F 0 "#PWR64" H 5300 9650 30 0001 C CNN
705	761	F 1 "GND" H 5300 9580 30 0001 C CNN
706	762	1 5300 9650
707	763	1 0 0 -1
708	764	$EndComp
709	765	$Comp
710		L GND #PWR08
	766	L GND #PWR61
711	767	U 1 1 4D14097D
712	768	P 4100 9850
713		F 0 "#PWR08" H 4100 9850 30 0001 C CNN
	769	F 0 "#PWR61" H 4100 9850 30 0001 C CNN
714	770	F 1 "GND" H 4100 9780 30 0001 C CNN
715	771	1 4100 9850
716	772	1 0 0 -1
...	...
726	782	1 0 0 -1
727	783	$EndComp
728	784	$Comp
729		L GND #PWR09
	785	L GND #PWR57
730	786	U 1 1 4D14083D
731	787	P 2750 10850
732		F 0 "#PWR09" H 2750 10850 30 0001 C CNN
	788	F 0 "#PWR57" H 2750 10850 30 0001 C CNN
733	789	F 1 "GND" H 2750 10780 30 0001 C CNN
734	790	1 2750 10850
735	791	1 0 0 -1
736	792	$EndComp
737	793	$Comp
738		L GND #PWR010
	794	L GND #PWR55
739	795	U 1 1 4D140715
740	796	P 2450 10250
741		F 0 "#PWR010" H 2450 10250 30 0001 C CNN
	797	F 0 "#PWR55" H 2450 10250 30 0001 C CNN
742	798	F 1 "GND" H 2450 10180 30 0001 C CNN
743	799	1 2450 10250
744	800	1 0 0 -1
745	801	$EndComp
746	802	$Comp
747		L GND #PWR011
	803	L GND #PWR49
748	804	U 1 1 4D140708
749	805	P 1050 9650
750		F 0 "#PWR011" H 1050 9650 30 0001 C CNN
	806	F 0 "#PWR49" H 1050 9650 30 0001 C CNN
751	807	F 1 "GND" H 1050 9580 30 0001 C CNN
752	808	1 1050 9650
753	809	1 0 0 -1
...	...
843	899	0 1 1 0
844	900	$EndComp
845	901	$Comp
846		L GND #PWR012
	902	L GND #PWR54
847	903	U 1 1 4D140270
848	904	P 2100 7600
849		F 0 "#PWR012" H 2100 7600 30 0001 C CNN
	905	F 0 "#PWR54" H 2100 7600 30 0001 C CNN
850	906	F 1 "GND" H 2100 7530 30 0001 C CNN
851	907	1 2100 7600
852	908	1 0 0 -1
...	...
862	918	0 1 1 0
863	919	$EndComp
864	920	$Comp
865		L GND #PWR013
	921	L GND #PWR51
866	922	U 1 1 4D14016E
867	923	P 1300 7550
868		F 0 "#PWR013" H 1300 7550 30 0001 C CNN
	924	F 0 "#PWR51" H 1300 7550 30 0001 C CNN
869	925	F 1 "GND" H 1300 7480 30 0001 C CNN
870	926	1 1300 7550
871	927	1 0 0 -1
...	...
901	957	1 0 0 -1
902	958	$EndComp
903	959	$Comp
904		L GND #PWR014
	960	L GND #PWR62
905	961	U 1 1 4D140161
906	962	P 4800 7700
907		F 0 "#PWR014" H 4800 7700 30 0001 C CNN
	963	F 0 "#PWR62" H 4800 7700 30 0001 C CNN
908	964	F 1 "GND" H 4800 7630 30 0001 C CNN
909	965	1 4800 7700
910	966	1 0 0 -1
...	...
912	968	Text Notes 4550 8200 0 40 ~ 0
913	969	http://www.onsemi.com/pub_link/Collateral/NCP1529-D.PDF
914	970	$Comp
915		L GND #PWR015
	971	L GND #PWR65
916	972	U 1 1 4D13FF19
917	973	P 5450 4900
918		F 0 "#PWR015" H 5450 4900 30 0001 C CNN
	974	F 0 "#PWR65" H 5450 4900 30 0001 C CNN
919	975	F 1 "GND" H 5450 4830 30 0001 C CNN
920	976	1 5450 4900
921	977	1 0 0 -1
...	...
941	997	1 0 0 -1
942	998	$EndComp
943	999	$Comp
944		L GND #PWR016
	1000	L GND #PWR63
945	1001	U 1 1 4D13FF2E
946	1002	P 5050 2100
947		F 0 "#PWR016" H 5050 2100 30 0001 C CNN
	1003	F 0 "#PWR63" H 5050 2100 30 0001 C CNN
948	1004	F 1 "GND" H 5050 2030 30 0001 C CNN
949	1005	1 5050 2100
950	1006	1 0 0 -1
...	...
960	1016	1 0 0 -1
961	1017	$EndComp
962	1018	$Comp
963		L GND #PWR017
	1019	L GND #PWR59
964	1020	U 1 1 4D13FEDF
965	1021	P 3050 3400
966		F 0 "#PWR017" H 3050 3400 30 0001 C CNN
	1022	F 0 "#PWR59" H 3050 3400 30 0001 C CNN
967	1023	F 1 "GND" H 3050 3330 30 0001 C CNN
968	1024	1 3050 3400
969	1025	1 0 0 -1
970	1026	$EndComp
971	1027	$Comp
972		L GND #PWR018
	1028	L GND #PWR56
973	1029	U 1 1 4D13FECF
974	1030	P 2650 5900
975		F 0 "#PWR018" H 2650 5900 30 0001 C CNN
	1031	F 0 "#PWR56" H 2650 5900 30 0001 C CNN
976	1032	F 1 "GND" H 2650 5830 30 0001 C CNN
977	1033	1 2650 5900
978	1034	1 0 0 -1
979	1035	$EndComp
980	1036	$Comp
981		L GND #PWR019
	1037	L GND #PWR58
982	1038	U 1 1 4D13FEC8
983	1039	P 2850 5650
984		F 0 "#PWR019" H 2850 5650 30 0001 C CNN
	1040	F 0 "#PWR58" H 2850 5650 30 0001 C CNN
985	1041	F 1 "GND" H 2850 5580 30 0001 C CNN
986	1042	1 2850 5650
987	1043	1 0 0 -1
...	...
997	1053	1 0 0 -1
998	1054	$EndComp
999	1055	$Comp
1000		L GND #PWR020
	1056	L GND #PWR50
1001	1057	U 1 1 4D13FEB5
1002	1058	P 1100 4600
1003		F 0 "#PWR020" H 1100 4600 30 0001 C CNN
	1059	F 0 "#PWR50" H 1100 4600 30 0001 C CNN
1004	1060	F 1 "GND" H 1100 4530 30 0001 C CNN
1005	1061	1 1100 4600
1006	1062	1 0 0 -1
...	...
1117	1173	Text Notes 1900 1100 0 40 ~ 0
1118	1174	???\n
1119	1175	$Comp
1120		L GND #PWR021
	1176	L GND #PWR53
1121	1177	U 1 1 4D13F926
1122	1178	P 1950 2000
1123		F 0 "#PWR021" H 1950 2000 30 0001 C CNN
	1179	F 0 "#PWR53" H 1950 2000 30 0001 C CNN
1124	1180	F 1 "GND" H 1950 1930 30 0001 C CNN
1125	1181	1 1950 2000
1126	1182	1 0 0 -1
1127	1183	$EndComp
1128	1184	$Comp
1129		L GND #PWR022
	1185	L GND #PWR52
1130	1186	U 1 1 4D13F8E2
1131	1187	P 1700 2550
1132		F 0 "#PWR022" H 1700 2550 30 0001 C CNN
	1188	F 0 "#PWR52" H 1700 2550 30 0001 C CNN
1133	1189	F 1 "GND" H 1700 2480 30 0001 C CNN
1134	1190	1 1700 2550
1135	1191	1 0 0 -1
1136	1192	$EndComp
1137	1193	$Comp
1138		L GND #PWR023
	1194	L GND #PWR48
1139	1195	U 1 1 4D13F81E
1140	1196	P 1050 1900
1141		F 0 "#PWR023" H 1050 1900 30 0001 C CNN
	1197	F 0 "#PWR48" H 1050 1900 30 0001 C CNN
1142	1198	F 1 "GND" H 1050 1830 30 0001 C CNN
1143	1199	1 1050 1900
1144	1200	1 0 0 -1
1145	1201	$EndComp
1146	1202	$Comp
1147		L GND #PWR024
	1203	L GND #PWR60
1148	1204	U 1 1 4D13F818
1149	1205	P 3700 2400
1150		F 0 "#PWR024" H 3700 2400 30 0001 C CNN
	1206	F 0 "#PWR60" H 3700 2400 30 0001 C CNN
1151	1207	F 1 "GND" H 3700 2330 30 0001 C CNN
1152	1208	1 3700 2400
1153	1209	1 0 0 -1

xue-rnc/sdram.sch
1		EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT
	1	EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT
2	2	LIBS:power
3	3	LIBS:r_pack2
4	4	LIBS:v0402mhs03
...	...
53	53	LIBS:fxo-hc536r
54	54	LIBS:zx62d-b-5p8
55	55	LIBS:a7130
56		LIBS:xue-rnc-cache
57	56	EELAYER 24 0
58	57	EELAYER END
59	58	$Descr A4 11700 8267
60	59	Sheet 6 9
61	60	Title ""
62		Date "29 dec 2010"
	61	Date "31 dec 2010"
63	62	Rev ""
64	63	Comp ""
65	64	Comment1 ""
...	...
543	542	Entry Wire Line
544	543	10100 4400 10200 4500
545	544	$Comp
546		L GND #PWR059
	545	L GND #PWR16
547	546	U 1 1 4C699C4D
548	547	P 9950 2100
549		F 0 "#PWR059" H 9950 2100 30 0001 C CNN
	548	F 0 "#PWR16" H 9950 2100 30 0001 C CNN
550	549	F 1 "GND" H 9950 2030 30 0001 C CNN
551	550	1 9950 2100
552	551	1 0 0 -1
553	552	$EndComp
554	553	$Comp
555		L GND #PWR060
	554	L GND #PWR8
556	555	U 1 1 4C699C48
557	556	P 4550 2150
558		F 0 "#PWR060" H 4550 2150 30 0001 C CNN
	557	F 0 "#PWR8" H 4550 2150 30 0001 C CNN
559	558	F 1 "GND" H 4550 2080 30 0001 C CNN
560	559	1 4550 2150
561	560	1 0 0 -1
...	...
613	612	1 0 0 -1
614	613	$EndComp
615	614	$Comp
616		L GND #PWR061
	615	L GND #PWR10
617	616	U 1 1 4C61D1D3
618	617	P 6900 6200
619		F 0 "#PWR061" H 6900 6200 30 0001 C CNN
	618	F 0 "#PWR10" H 6900 6200 30 0001 C CNN
620	619	F 1 "GND" H 6900 6130 30 0001 C CNN
621	620	1 6900 6200
622	621	1 0 0 -1
623	622	$EndComp
624	623	$Comp
625		L +2.5V #PWR062
	624	L +2.5V #PWR9
626	625	U 1 1 4C61D1D2
627	626	P 6900 5800
628		F 0 "#PWR062" H 6900 5750 20 0001 C CNN
	627	F 0 "#PWR9" H 6900 5750 20 0001 C CNN
629	628	F 1 "+2.5V" H 6900 5900 30 0000 C CNN
630	629	1 6900 5800
631	630	1 0 0 -1
632	631	$EndComp
633	632	$Comp
634		L +2.5V #PWR063
	633	L +2.5V #PWR1
635	634	U 1 1 4C61D192
636	635	P 1700 5800
637		F 0 "#PWR063" H 1700 5750 20 0001 C CNN
	636	F 0 "#PWR1" H 1700 5750 20 0001 C CNN
638	637	F 1 "+2.5V" H 1700 5900 30 0000 C CNN
639	638	1 1700 5800
640	639	1 0 0 -1
641	640	$EndComp
642	641	$Comp
643		L GND #PWR064
	642	L GND #PWR2
644	643	U 1 1 4C61D17F
645	644	P 1700 6200
646		F 0 "#PWR064" H 1700 6200 30 0001 C CNN
	645	F 0 "#PWR2" H 1700 6200 30 0001 C CNN
647	646	F 1 "GND" H 1700 6130 30 0001 C CNN
648	647	1 1700 6200
649	648	1 0 0 -1
...	...
659	658	1 0 0 -1
660	659	$EndComp
661	660	$Comp
662		L +2.5V #PWR065
	661	L +2.5V #PWR4
663	662	U 1 1 4C61CFCF
664	663	P 3050 1750
665		F 0 "#PWR065" H 3050 1700 20 0001 C CNN
	664	F 0 "#PWR4" H 3050 1700 20 0001 C CNN
666	665	F 1 "+2.5V" H 3050 1850 30 0000 C CNN
667	666	1 3050 1750
668	667	1 0 0 -1
669	668	$EndComp
670	669	$Comp
671		L +2.5V #PWR066
	670	L +2.5V #PWR14
672	671	U 1 1 4C61CFC6
673	672	P 8400 1700
674		F 0 "#PWR066" H 8400 1650 20 0001 C CNN
	673	F 0 "#PWR14" H 8400 1650 20 0001 C CNN
675	674	F 1 "+2.5V" H 8400 1800 30 0000 C CNN
676	675	1 8400 1700
677	676	1 0 0 -1
...	...
737	736	1 0 0 -1
738	737	$EndComp
739	738	$Comp
740		L +2.5V #PWR067
	739	L +2.5V #PWR11
741	740	U 1 1 4C61CF9F
742	741	P 8300 5750
743		F 0 "#PWR067" H 8300 5700 20 0001 C CNN
	742	F 0 "#PWR11" H 8300 5700 20 0001 C CNN
744	743	F 1 "+2.5V" H 8300 5850 30 0000 C CNN
745	744	1 8300 5750
746	745	1 0 0 -1
747	746	$EndComp
748	747	$Comp
749		L GND #PWR068
	748	L GND #PWR12
750	749	U 1 1 4C61CF9E
751	750	P 8300 6350
752		F 0 "#PWR068" H 8300 6350 30 0001 C CNN
	751	F 0 "#PWR12" H 8300 6350 30 0001 C CNN
753	752	F 1 "GND" H 8300 6280 30 0001 C CNN
754	753	1 8300 6350
755	754	1 0 0 -1
756	755	$EndComp
757	756	$Comp
758		L GND #PWR069
	757	L GND #PWR6
759	758	U 1 1 4C61CF90
760	759	P 3050 6350
761		F 0 "#PWR069" H 3050 6350 30 0001 C CNN
	760	F 0 "#PWR6" H 3050 6350 30 0001 C CNN
762	761	F 1 "GND" H 3050 6280 30 0001 C CNN
763	762	1 3050 6350
764	763	1 0 0 -1
765	764	$EndComp
766	765	$Comp
767		L +2.5V #PWR070
	766	L +2.5V #PWR5
768	767	U 1 1 4C61CF89
769	768	P 3050 5750
770		F 0 "#PWR070" H 3050 5700 20 0001 C CNN
	769	F 0 "#PWR5" H 3050 5700 20 0001 C CNN
771	770	F 1 "+2.5V" H 3050 5850 30 0000 C CNN
772	771	1 3050 5750
773	772	1 0 0 -1
...	...
853	852	1 0 0 -1
854	853	$EndComp
855	854	$Comp
856		L +2.5V #PWR071
	855	L +2.5V #PWR15
857	856	U 1 1 4C61CE2F
858	857	P 9950 800
859		F 0 "#PWR071" H 9950 750 20 0001 C CNN
	858	F 0 "#PWR15" H 9950 750 20 0001 C CNN
860	859	F 1 "+2.5V" H 9950 900 30 0000 C CNN
861	860	1 9950 800
862	861	1 0 0 -1
863	862	$EndComp
864	863	$Comp
865		L +2.5V #PWR072
	864	L +2.5V #PWR7
866	865	U 1 1 4C61CDF1
867	866	P 4550 850
868		F 0 "#PWR072" H 4550 800 20 0001 C CNN
	867	F 0 "#PWR7" H 4550 800 20 0001 C CNN
869	868	F 1 "+2.5V" H 4550 950 30 0000 C CNN
870	869	1 4550 850
871	870	1 0 0 -1
...	...
948	947	Text HLabel 5000 5350 2 60 BiDi ~ 0
949	948	M0_DQ[0..15]
950	949	$Comp
951		L GND #PWR073
	950	L GND #PWR3
952	951	U 1 1 4C58A712
953	952	P 3000 5200
954		F 0 "#PWR073" H 3000 5200 30 0001 C CNN
	953	F 0 "#PWR3" H 3000 5200 30 0001 C CNN
955	954	F 1 "GND" H 3000 5130 30 0001 C CNN
956	955	1 3000 5200
957	956	1 0 0 -1
...	...
1227	1226	Entry Wire Line
1228	1227	10100 3600 10200 3700
1229	1228	$Comp
1230		L GND #PWR074
	1229	L GND #PWR13
1231	1230	U 1 1 4C437C3F
1232	1231	P 8350 5150
1233		F 0 "#PWR074" H 8350 5150 30 0001 C CNN
	1232	F 0 "#PWR13" H 8350 5150 30 0001 C CNN
1234	1233	F 1 "GND" H 8350 5080 30 0001 C CNN
1235	1234	1 8350 5150
1236	1235	1 0 0 -1

xue-rnc/usb.sch
1		EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT
	1	EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT
2	2	LIBS:power
3	3	LIBS:r_pack2
4	4	LIBS:v0402mhs03
...	...
53	53	LIBS:fxo-hc536r
54	54	LIBS:zx62d-b-5p8
55	55	LIBS:a7130
56		LIBS:xue-rnc-cache
57	56	EELAYER 24 0
58	57	EELAYER END
59	58	$Descr A4 11700 8267
60	59	Sheet 8 9
61	60	Title ""
62		Date "29 dec 2010"
	61	Date "31 dec 2010"
63	62	Rev ""
64	63	Comp ""
65	64	Comment1 ""
...	...
379	378	1 0 0 -1
380	379	$EndComp
381	380	$Comp
382		L +3.3V #PWR075
	381	L +3.3V #PWR41
383	382	U 1 1 4C7D365E
384	383	P 3975 5750
385		F 0 "#PWR075" H 3975 5710 30 0001 C CNN
	384	F 0 "#PWR41" H 3975 5710 30 0001 C CNN
386	385	F 1 "+3.3V" H 3975 5860 30 0000 C CNN
387	386	1 3975 5750
388	387	1 0 0 -1
...	...
394	393	Text Label 4125 6550 0 40 ~ 0
395	394	USBD_D-
396	395	$Comp
397		L GND #PWR076
	396	L GND #PWR27
398	397	U 1 1 4C7D3584
399	398	P 1750 7150
400		F 0 "#PWR076" H 1750 7150 30 0001 C CNN
	399	F 0 "#PWR27" H 1750 7150 30 0001 C CNN
401	400	F 1 "GND" H 1750 7080 30 0001 C CNN
402	401	1 1750 7150
403	402	1 0 0 -1
...	...
422	421	0 1 1 0
423	422	$EndComp
424	423	$Comp
425		L GND #PWR077
	424	L GND #PWR28
426	425	U 1 1 4C7D353A
427	426	P 1850 3450
428		F 0 "#PWR077" H 1850 3450 30 0001 C CNN
	427	F 0 "#PWR28" H 1850 3450 30 0001 C CNN
429	428	F 1 "GND" H 1850 3380 30 0001 C CNN
430	429	1 1850 3450
431	430	1 0 0 -1
...	...
455	454	Text Label 5850 2950 0 40 ~ 0
456	455	USB_CASE_HOST
457	456	$Comp
458		L +3.3V #PWR078
	457	L +3.3V #PWR42
459	458	U 1 1 4C7D32BA
460	459	P 4350 2050
461		F 0 "#PWR078" H 4350 2010 30 0001 C CNN
	460	F 0 "#PWR42" H 4350 2010 30 0001 C CNN
462	461	F 1 "+3.3V" H 4350 2160 30 0000 C CNN
463	462	1 4350 2050
464	463	1 0 0 -1
...	...
526	525	1 0 0 -1
527	526	$EndComp
528	527	$Comp
529		L +3.3V #PWR079
	528	L +3.3V #PWR34
530	529	U 1 1 4C695F50
531	530	P 2700 4600
532		F 0 "#PWR079" H 2700 4560 30 0001 C CNN
	531	F 0 "#PWR34" H 2700 4560 30 0001 C CNN
533	532	F 1 "+3.3V" H 2700 4710 30 0000 C CNN
534	533	1 2700 4600
535	534	1 0 0 -1
536	535	$EndComp
537	536	$Comp
538		L +3.3V #PWR080
	537	L +3.3V #PWR29
539	538	U 1 1 4C695F4B
540	539	P 2100 6100
541		F 0 "#PWR080" H 2100 6060 30 0001 C CNN
	540	F 0 "#PWR29" H 2100 6060 30 0001 C CNN
542	541	F 1 "+3.3V" H 2100 6210 30 0000 C CNN
543	542	1 2100 6100
544	543	1 0 0 -1
545	544	$EndComp
546	545	$Comp
547		L +3.3V #PWR081
	546	L +3.3V #PWR32
548	547	U 1 1 4C695F43
549	548	P 2650 1100
550		F 0 "#PWR081" H 2650 1060 30 0001 C CNN
	549	F 0 "#PWR32" H 2650 1060 30 0001 C CNN
551	550	F 1 "+3.3V" H 2650 1210 30 0000 C CNN
552	551	1 2650 1100
553	552	1 0 0 -1
554	553	$EndComp
555	554	$Comp
556		L +3.3V #PWR082
	555	L +3.3V #PWR30
557	556	U 1 1 4C695F3B
558	557	P 2200 2400
559		F 0 "#PWR082" H 2200 2360 30 0001 C CNN
	558	F 0 "#PWR30" H 2200 2360 30 0001 C CNN
560	559	F 1 "+3.3V" H 2200 2510 30 0000 C CNN
561	560	1 2200 2400
562	561	1 0 0 -1
563	562	$EndComp
564	563	$Comp
565		L +2.5V #PWR083
	564	L +2.5V #PWR39
566	565	U 1 1 4C695DCD
567	566	P 3200 4550
568		F 0 "#PWR083" H 3200 4500 20 0001 C CNN
	567	F 0 "#PWR39" H 3200 4500 20 0001 C CNN
569	568	F 1 "+2.5V" H 3200 4650 30 0000 C CNN
570	569	1 3200 4550
571	570	1 0 0 -1
572	571	$EndComp
573	572	$Comp
574		L GND #PWR084
	573	L GND #PWR40
575	574	U 1 1 4C695F0A
576	575	P 3200 5550
577		F 0 "#PWR084" H 3200 5550 30 0001 C CNN
	576	F 0 "#PWR40" H 3200 5550 30 0001 C CNN
578	577	F 1 "GND" H 3200 5480 30 0001 C CNN
579	578	1 3200 5550
580	579	1 0 0 -1
581	580	$EndComp
582	581	$Comp
583		L GND #PWR085
	582	L GND #PWR33
584	583	U 1 1 4C695F09
585	584	P 2650 5550
586		F 0 "#PWR085" H 2650 5550 30 0001 C CNN
	585	F 0 "#PWR33" H 2650 5550 30 0001 C CNN
587	586	F 1 "GND" H 2650 5480 30 0001 C CNN
588	587	1 2650 5550
589	588	1 0 0 -1
590	589	$EndComp
591	590	$Comp
592		L GND #PWR086
	591	L GND #PWR37
593	592	U 1 1 4C695DFE
594	593	P 3150 1850
595		F 0 "#PWR086" H 3150 1850 30 0001 C CNN
	594	F 0 "#PWR37" H 3150 1850 30 0001 C CNN
596	595	F 1 "GND" H 3150 1780 30 0001 C CNN
597	596	1 3150 1850
598	597	1 0 0 -1
599	598	$EndComp
600	599	$Comp
601		L GND #PWR087
	600	L GND #PWR31
602	601	U 1 1 4C695DF8
603	602	P 2600 1850
604		F 0 "#PWR087" H 2600 1850 30 0001 C CNN
	603	F 0 "#PWR31" H 2600 1850 30 0001 C CNN
605	604	F 1 "GND" H 2600 1780 30 0001 C CNN
606	605	1 2600 1850
607	606	1 0 0 -1
608	607	$EndComp
609	608	$Comp
610		L +2.5V #PWR088
	609	L +2.5V #PWR36
611	610	U 1 1 4C695DA7
612	611	P 3150 1100
613		F 0 "#PWR088" H 3150 1050 20 0001 C CNN
	612	F 0 "#PWR36" H 3150 1050 20 0001 C CNN
614	613	F 1 "+2.5V" H 3150 1200 30 0000 C CNN
615	614	1 3150 1100
616	615	1 0 0 -1
...	...
695	694	Text HLabel 1200 6750 0 40 BiDi ~ 0
696	695	USBD_VM
697	696	$Comp
698		L GND #PWR089
	697	L GND #PWR46
699	698	U 1 1 4C6552B5
700	699	P 5500 7400
701		F 0 "#PWR089" H 5500 7400 30 0001 C CNN
	700	F 0 "#PWR46" H 5500 7400 30 0001 C CNN
702	701	F 1 "GND" H 5500 7330 30 0001 C CNN
703	702	1 5500 7400
704	703	1 0 0 -1
705	704	$EndComp
706	705	$Comp
707		L GND #PWR090
	706	L GND #PWR38
708	707	U 1 1 4C6552B4
709	708	P 3150 7500
710		F 0 "#PWR090" H 3150 7500 30 0001 C CNN
	709	F 0 "#PWR38" H 3150 7500 30 0001 C CNN
711	710	F 1 "GND" H 3150 7430 30 0001 C CNN
712	711	1 3150 7500
713	712	1 0 0 -1
714	713	$EndComp
715	714	$Comp
716		L +2.5V #PWR091
	715	L +2.5V #PWR25
717	716	U 1 1 4C6552B2
718	717	P 1150 6150
719		F 0 "#PWR091" H 1150 6100 20 0001 C CNN
	718	F 0 "#PWR25" H 1150 6100 20 0001 C CNN
720	719	F 1 "+2.5V" H 1150 6250 30 0000 C CNN
721	720	1 1150 6150
722	721	1 0 0 -1
...	...
732	731	1 0 0 -1
733	732	$EndComp
734	733	$Comp
735		L GND #PWR092
	734	L GND #PWR43
736	735	U 1 1 4C6552AE
737	736	P 4650 7350
738		F 0 "#PWR092" H 4650 7350 30 0001 C CNN
	737	F 0 "#PWR43" H 4650 7350 30 0001 C CNN
739	738	F 1 "GND" H 4650 7280 30 0001 C CNN
740	739	1 4650 7350
741	740	1 0 0 -1
742	741	$EndComp
743	742	$Comp
744		L GND #PWR093
	743	L GND #PWR45
745	744	U 1 1 4C63F2B5
746	745	P 4900 3700
747		F 0 "#PWR093" H 4900 3700 30 0001 C CNN
	746	F 0 "#PWR45" H 4900 3700 30 0001 C CNN
748	747	F 1 "GND" H 4900 3630 30 0001 C CNN
749	748	1 4900 3700
750	749	1 0 0 -1
751	750	$EndComp
752	751	$Comp
753		L +5V #PWR094
	752	L +5V #PWR44
754	753	U 1 1 4C63F295
755	754	P 4700 1350
756		F 0 "#PWR094" H 4700 1440 20 0001 C CNN
	755	F 0 "#PWR44" H 4700 1440 20 0001 C CNN
757	756	F 1 "+5V" H 4700 1440 30 0000 C CNN
758	757	1 4700 1350
759	758	1 0 0 -1
...	...
779	778	1 0 0 -1
780	779	$EndComp
781	780	$Comp
782		L +2.5V #PWR095
	781	L +2.5V #PWR26
783	782	U 1 1 4C63EC16
784	783	P 1250 2450
785		F 0 "#PWR095" H 1250 2400 20 0001 C CNN
	784	F 0 "#PWR26" H 1250 2400 20 0001 C CNN
786	785	F 1 "+2.5V" H 1250 2550 30 0000 C CNN
787	786	1 1250 2450
788	787	1 0 0 -1
789	788	$EndComp
790	789	$Comp
791		L GND #PWR096
	790	L GND #PWR35
792	791	U 1 1 4C63EA1B
793	792	P 3100 3800
794		F 0 "#PWR096" H 3100 3800 30 0001 C CNN
	793	F 0 "#PWR35" H 3100 3800 30 0001 C CNN
795	794	F 1 "GND" H 3100 3730 30 0001 C CNN
796	795	1 3100 3800
797	796	1 0 0 -1
798	797	$EndComp
799	798	$Comp
800		L GND #PWR097
	799	L GND #PWR47
801	800	U 1 1 4C63E9FA
802	801	P 5950 3750
803		F 0 "#PWR097" H 5950 3750 30 0001 C CNN
	802	F 0 "#PWR47" H 5950 3750 30 0001 C CNN
804	803	F 1 "GND" H 5950 3680 30 0001 C CNN
805	804	1 5950 3750
806	805	1 0 0 -1

xue-rnc/xue-rnc.brd
1		PCBNEW-BOARD Version 1 date Wed 29 Dec 2010 01:38:30 PM COT
	1	PCBNEW-BOARD Version 1 date Fri 31 Dec 2010 10:32:51 AM COT
2	2
3	3	# Created by Pcbnew(2010-10-01 BZR 2513)-testing
4	4
...	...
6	6	LayerCount 6
7	7	Ly 1FFF801F
8	8	EnabledLayers 13FF801F
9		Links 835
10		NoConn 155
11		Di 45633 12844 80041 52832
	9	Links 839
	10	NoConn 159
	11	Di 45633 7776 80041 52832
12	12	Ndraw 6
13	13	Ntrack 4940
14	14	Nzone 0
15	15	BoardThickness 630
16		Nmodule 215
17		Nnets 337
	16	Nmodule 217
	17	Nnets 338
18	18	$EndGENERAL
19	19
20	20	$SHEETDESCR
21	21	Sheet A4 11700 8267
22	22	Title ""
23		Date "29 dec 2010"
	23	Date "31 dec 2010"
24	24	Rev ""
25	25	Comp ""
26	26	Comment1 ""
...	...
68	68	EdgeModWidth 59
69	69	TextModSize 600 600
70	70	TextModWidth 120
71		PadSize 196 393
72		PadDrill 0
	71	PadSize 984 551
	72	PadDrill 748
73	73	Pad2MaskClearance 100
74	74	AuxiliaryAxisOrg 0 0
75	75	$EndSETUP
...	...
107	107	St ~
108	108	$EndEQUIPOT
109	109	$EQUIPOT
110		Na 8 "/ether/ETH_CLK"
	110	Na 8 "/ether/ETH_COL"
111	111	St ~
112	112	$EndEQUIPOT
113	113	$EQUIPOT
114		Na 9 "/ether/ETH_COL"
	114	Na 9 "/ether/ETH_INT"
115	115	St ~
116	116	$EndEQUIPOT
117	117	$EQUIPOT
118		Na 10 "/ether/ETH_CRS"
	118	Na 10 "/ether/ETH_LED0"
119	119	St ~
120	120	$EndEQUIPOT
121	121	$EQUIPOT
122		Na 11 "/ether/ETH_INT"
	122	Na 11 "/ether/ETH_LED1"
123	123	St ~
124	124	$EndEQUIPOT
125	125	$EQUIPOT
126		Na 12 "/ether/ETH_LED0"
	126	Na 12 "/ether/ETH_MDIO"
127	127	St ~
128	128	$EndEQUIPOT
129	129	$EQUIPOT
130		Na 13 "/ether/ETH_LED1"
	130	Na 13 "/ether/ETH_PLL1.8V"
131	131	St ~
132	132	$EndEQUIPOT
133	133	$EQUIPOT
134		Na 14 "/ether/ETH_MDC"
	134	Na 14 "/ether/ETH_RXDV"
135	135	St ~
136	136	$EndEQUIPOT
137	137	$EQUIPOT
138		Na 15 "/ether/ETH_MDIO"
	138	Na 15 "/ether/ETH_RXER"
139	139	St ~
140	140	$EndEQUIPOT
141	141	$EQUIPOT
142		Na 16 "/ether/ETH_PLL1.8V"
	142	Na 16 "/ether/ETH_TXD2"
143	143	St ~
144	144	$EndEQUIPOT
145	145	$EQUIPOT
146		Na 17 "/ether/ETH_RXC"
	146	Na 17 "/ether/ETH_TXER"
147	147	St ~
148	148	$EndEQUIPOT
149	149	$EQUIPOT
150		Na 18 "/ether/ETH_RXDV"
	150	Na 18 "/ether/MAG_RX+"
151	151	St ~
152	152	$EndEQUIPOT
153	153	$EQUIPOT
154		Na 19 "/ether/ETH_TXD0"
	154	Na 19 "/ether/MAG_RX-"
155	155	St ~
156	156	$EndEQUIPOT
157	157	$EQUIPOT
158		Na 20 "/ether/ETH_TXD3"
	158	Na 20 "/ether/MAG_SHIELD"
159	159	St ~
160	160	$EndEQUIPOT
161	161	$EQUIPOT
162		Na 21 "/ether/ETH_TXER"
	162	Na 21 "/ether/MAG_TX+"
163	163	St ~
164	164	$EndEQUIPOT
165	165	$EQUIPOT
166		Na 22 "/ether/MAG_RX+"
	166	Na 22 "/ether/MAG_TX-"
167	167	St ~
168	168	$EndEQUIPOT
169	169	$EQUIPOT
170		Na 23 "/ether/MAG_RX-"
	170	Na 23 "/expansion/FPGA_BANK0_IO_11"
171	171	St ~
172	172	$EndEQUIPOT
173	173	$EQUIPOT
174		Na 24 "/ether/MAG_SHIELD"
	174	Na 24 "/expansion/FPGA_BANK0_IO_12"
175	175	St ~
176	176	$EndEQUIPOT
177	177	$EQUIPOT
178		Na 25 "/ether/MAG_TX+"
	178	Na 25 "/expansion/FPGA_BANK0_IO_14"
179	179	St ~
180	180	$EndEQUIPOT
181	181	$EQUIPOT
182		Na 26 "/ether/MAG_TX-"
	182	Na 26 "/expansion/FPGA_BANK0_IO_15"
183	183	St ~
184	184	$EndEQUIPOT
185	185	$EQUIPOT
186		Na 27 "/expansion/FPGA_BANK0_IO_1"
	186	Na 27 "/expansion/FPGA_BANK0_IO_22"
187	187	St ~
188	188	$EndEQUIPOT
189	189	$EQUIPOT
190		Na 28 "/expansion/FPGA_BANK0_IO_10"
	190	Na 28 "/expansion/FPGA_BANK0_IO_24"
191	191	St ~
192	192	$EndEQUIPOT
193	193	$EQUIPOT
194		Na 29 "/expansion/FPGA_BANK0_IO_11"
	194	Na 29 "/expansion/FPGA_BANK0_IO_28"
195	195	St ~
196	196	$EndEQUIPOT
197	197	$EQUIPOT
198		Na 30 "/expansion/FPGA_BANK0_IO_15"
	198	Na 30 "/expansion/FPGA_BANK0_IO_3"
199	199	St ~
200	200	$EndEQUIPOT
201	201	$EQUIPOT
202		Na 31 "/expansion/FPGA_BANK0_IO_17"
	202	Na 31 "/expansion/FPGA_BANK0_IO_33"
203	203	St ~
204	204	$EndEQUIPOT
205	205	$EQUIPOT
206		Na 32 "/expansion/FPGA_BANK0_IO_2"
	206	Na 32 "/expansion/FPGA_BANK0_IO_34"
207	207	St ~
208	208	$EndEQUIPOT
209	209	$EQUIPOT
210		Na 33 "/expansion/FPGA_BANK0_IO_20"
	210	Na 33 "/expansion/FPGA_BANK0_IO_36"
211	211	St ~
212	212	$EndEQUIPOT
213	213	$EQUIPOT
214		Na 34 "/expansion/FPGA_BANK0_IO_21"
	214	Na 34 "/expansion/FPGA_BANK0_IO_38"
215	215	St ~
216	216	$EndEQUIPOT
217	217	$EQUIPOT
218		Na 35 "/expansion/FPGA_BANK0_IO_29"
	218	Na 35 "/expansion/FPGA_BANK0_IO_39"
219	219	St ~
220	220	$EndEQUIPOT
221	221	$EQUIPOT
222		Na 36 "/expansion/FPGA_BANK0_IO_3"
	222	Na 36 "/expansion/FPGA_BANK0_IO_40"
223	223	St ~
224	224	$EndEQUIPOT
225	225	$EQUIPOT
226		Na 37 "/expansion/FPGA_BANK0_IO_32"
	226	Na 37 "/expansion/FPGA_BANK0_IO_43"
227	227	St ~
228	228	$EndEQUIPOT
229	229	$EQUIPOT
230		Na 38 "/expansion/FPGA_BANK0_IO_34"
	230	Na 38 "/expansion/FPGA_BANK0_IO_44"
231	231	St ~
232	232	$EndEQUIPOT
233	233	$EQUIPOT
234		Na 39 "/expansion/FPGA_BANK0_IO_38"
	234	Na 39 "/expansion/FPGA_BANK0_IO_45"
235	235	St ~
236	236	$EndEQUIPOT
237	237	$EQUIPOT
238		Na 40 "/expansion/FPGA_BANK0_IO_39"
	238	Na 40 "/expansion/FPGA_BANK0_IO_46"
239	239	St ~
240	240	$EndEQUIPOT
241	241	$EQUIPOT
242		Na 41 "/expansion/FPGA_BANK0_IO_40"
	242	Na 41 "/expansion/FPGA_BANK0_IO_47"
243	243	St ~
244	244	$EndEQUIPOT
245	245	$EQUIPOT
246		Na 42 "/expansion/FPGA_BANK0_IO_43"
	246	Na 42 "/expansion/FPGA_BANK0_IO_48"
247	247	St ~
248	248	$EndEQUIPOT
249	249	$EQUIPOT
250		Na 43 "/expansion/FPGA_BANK0_IO_46"
	250	Na 43 "/expansion/FPGA_BANK0_IO_5"
251	251	St ~
252	252	$EndEQUIPOT
253	253	$EQUIPOT
254		Na 44 "/expansion/FPGA_BANK0_IO_47"
	254	Na 44 "/expansion/FPGA_BANK0_IO_51"
255	255	St ~
256	256	$EndEQUIPOT
257	257	$EQUIPOT
258		Na 45 "/expansion/FPGA_BANK0_IO_5"
	258	Na 45 "/expansion/FPGA_BANK0_IO_62"
259	259	St ~
260	260	$EndEQUIPOT
261	261	$EQUIPOT
262		Na 46 "/expansion/FPGA_BANK0_IO_50"
	262	Na 46 "/expansion/FPGA_BANK0_IO_7"
263	263	St ~
264	264	$EndEQUIPOT
265	265	$EQUIPOT
266		Na 47 "/expansion/FPGA_BANK0_IO_54"
	266	Na 47 "/expansion/FPGA_BANK0_IO_9"
267	267	St ~
268	268	$EndEQUIPOT
269	269	$EQUIPOT
270		Na 48 "/expansion/FPGA_BANK0_IO_6"
	270	Na 48 "/flash/NF_D2"
271	271	St ~
272	272	$EndEQUIPOT
273	273	$EQUIPOT
274		Na 49 "/expansion/FPGA_BANK0_IO_7"
	274	Na 49 "/flash/NF_RNB"
275	275	St ~
276	276	$EndEQUIPOT
277	277	$EQUIPOT
278		Na 50 "/expansion/FPGA_BANK0_IO_9"
	278	Na 50 "/flash/NF_WE_N"
279	279	St ~
280	280	$EndEQUIPOT
281	281	$EQUIPOT
282		Na 51 "/flash/NF_ALE"
	282	Na 51 "/flash/SD_CLK"
283	283	St ~
284	284	$EndEQUIPOT
285	285	$EQUIPOT
286		Na 52 "/flash/NF_CLE"
	286	Na 52 "/flash/SD_DAT1"
287	287	St ~
288	288	$EndEQUIPOT
289	289	$EQUIPOT
290		Na 53 "/flash/NF_CS1_N"
	290	Na 53 "/flash/SD_DAT3"
291	291	St ~
292	292	$EndEQUIPOT
293	293	$EQUIPOT
294		Na 54 "/flash/NF_D0"
	294	Na 54 "/fpga1/ETH_CLK"
295	295	St ~
296	296	$EndEQUIPOT
297	297	$EQUIPOT
298		Na 55 "/flash/NF_D1"
	298	Na 55 "/fpga1/ETH_CRS"
299	299	St ~
300	300	$EndEQUIPOT
301	301	$EQUIPOT
302		Na 56 "/flash/NF_D3"
	302	Na 56 "/fpga1/ETH_MDC"
303	303	St ~
304	304	$EndEQUIPOT
305	305	$EQUIPOT
306		Na 57 "/flash/NF_D5"
	306	Na 57 "/fpga1/ETH_RESET_N"
307	307	St ~
308	308	$EndEQUIPOT
309	309	$EQUIPOT
310		Na 58 "/flash/NF_D7"
	310	Na 58 "/fpga1/ETH_RXC"
311	311	St ~
312	312	$EndEQUIPOT
313	313	$EQUIPOT
314		Na 59 "/flash/NF_RE_N"
	314	Na 59 "/fpga1/ETH_RXD0"
315	315	St ~
316	316	$EndEQUIPOT
317	317	$EQUIPOT
318		Na 60 "/flash/SD_DAT2"
	318	Na 60 "/fpga1/ETH_RXD1"
319	319	St ~
320	320	$EndEQUIPOT
321	321	$EQUIPOT
322		Na 61 "/fpga1/ETH_RESET_N"
	322	Na 61 "/fpga1/ETH_RXD2"
323	323	St ~
324	324	$EndEQUIPOT
325	325	$EQUIPOT
326		Na 62 "/fpga1/ETH_RXD0"
	326	Na 62 "/fpga1/ETH_RXD3"
327	327	St ~
328	328	$EndEQUIPOT
329	329	$EQUIPOT
330		Na 63 "/fpga1/ETH_RXD1"
	330	Na 63 "/fpga1/ETH_TXC"
331	331	St ~
332	332	$EndEQUIPOT
333	333	$EQUIPOT
334		Na 64 "/fpga1/ETH_RXD2"
	334	Na 64 "/fpga1/ETH_TXD0"
335	335	St ~
336	336	$EndEQUIPOT
337	337	$EQUIPOT
338		Na 65 "/fpga1/ETH_RXD3"
	338	Na 65 "/fpga1/ETH_TXD1"
339	339	St ~
340	340	$EndEQUIPOT
341	341	$EQUIPOT
342		Na 66 "/fpga1/ETH_RXER"
	342	Na 66 "/fpga1/ETH_TXD3"
343	343	St ~
344	344	$EndEQUIPOT
345	345	$EQUIPOT
346		Na 67 "/fpga1/ETH_TXC"
	346	Na 67 "/fpga1/ETH_TXEN"
347	347	St ~
348	348	$EndEQUIPOT
349	349	$EQUIPOT
350		Na 68 "/fpga1/ETH_TXD1"
	350	Na 68 "/fpga1/FPGA_BANK0_IO_1"
351	351	St ~
352	352	$EndEQUIPOT
353	353	$EQUIPOT
354		Na 69 "/fpga1/ETH_TXD2"
	354	Na 69 "/fpga1/FPGA_BANK0_IO_10"
355	355	St ~
356	356	$EndEQUIPOT
357	357	$EQUIPOT
358		Na 70 "/fpga1/ETH_TXEN"
	358	Na 70 "/fpga1/FPGA_BANK0_IO_17"
359	359	St ~
360	360	$EndEQUIPOT
361	361	$EQUIPOT
362		Na 71 "/fpga1/FPGA_BANK0_IO_12"
	362	Na 71 "/fpga1/FPGA_BANK0_IO_18"
363	363	St ~
364	364	$EndEQUIPOT
365	365	$EQUIPOT
366		Na 72 "/fpga1/FPGA_BANK0_IO_14"
	366	Na 72 "/fpga1/FPGA_BANK0_IO_2"
367	367	St ~
368	368	$EndEQUIPOT
369	369	$EQUIPOT
370		Na 73 "/fpga1/FPGA_BANK0_IO_18"
	370	Na 73 "/fpga1/FPGA_BANK0_IO_20"
371	371	St ~
372	372	$EndEQUIPOT
373	373	$EQUIPOT
374		Na 74 "/fpga1/FPGA_BANK0_IO_22"
	374	Na 74 "/fpga1/FPGA_BANK0_IO_21"
375	375	St ~
376	376	$EndEQUIPOT
377	377	$EQUIPOT
378		Na 75 "/fpga1/FPGA_BANK0_IO_24"
	378	Na 75 "/fpga1/FPGA_BANK0_IO_25"
379	379	St ~
380	380	$EndEQUIPOT
381	381	$EQUIPOT
382		Na 76 "/fpga1/FPGA_BANK0_IO_25"
	382	Na 76 "/fpga1/FPGA_BANK0_IO_27"
383	383	St ~
384	384	$EndEQUIPOT
385	385	$EQUIPOT
386		Na 77 "/fpga1/FPGA_BANK0_IO_27"
	386	Na 77 "/fpga1/FPGA_BANK0_IO_29"
387	387	St ~
388	388	$EndEQUIPOT
389	389	$EQUIPOT
390		Na 78 "/fpga1/FPGA_BANK0_IO_28"
	390	Na 78 "/fpga1/FPGA_BANK0_IO_30"
391	391	St ~
392	392	$EndEQUIPOT
393	393	$EQUIPOT
394		Na 79 "/fpga1/FPGA_BANK0_IO_30"
	394	Na 79 "/fpga1/FPGA_BANK0_IO_32"
395	395	St ~
396	396	$EndEQUIPOT
397	397	$EQUIPOT
398		Na 80 "/fpga1/FPGA_BANK0_IO_33"
	398	Na 80 "/fpga1/FPGA_BANK0_IO_49"
399	399	St ~
400	400	$EndEQUIPOT
401	401	$EQUIPOT
402		Na 81 "/fpga1/FPGA_BANK0_IO_36"
	402	Na 81 "/fpga1/FPGA_BANK0_IO_50"
403	403	St ~
404	404	$EndEQUIPOT
405	405	$EQUIPOT
406		Na 82 "/fpga1/FPGA_BANK0_IO_44"
	406	Na 82 "/fpga1/FPGA_BANK0_IO_52"
407	407	St ~
408	408	$EndEQUIPOT
409	409	$EQUIPOT
410		Na 83 "/fpga1/FPGA_BANK0_IO_45"
	410	Na 83 "/fpga1/FPGA_BANK0_IO_53"
411	411	St ~
412	412	$EndEQUIPOT
413	413	$EQUIPOT
414		Na 84 "/fpga1/FPGA_BANK0_IO_48"
	414	Na 84 "/fpga1/FPGA_BANK0_IO_54"
415	415	St ~
416	416	$EndEQUIPOT
417	417	$EQUIPOT
418		Na 85 "/fpga1/FPGA_BANK0_IO_49"
	418	Na 85 "/fpga1/FPGA_BANK0_IO_56"
419	419	St ~
420	420	$EndEQUIPOT
421	421	$EQUIPOT
422		Na 86 "/fpga1/FPGA_BANK0_IO_51"
	422	Na 86 "/fpga1/FPGA_BANK0_IO_57"
423	423	St ~
424	424	$EndEQUIPOT
425	425	$EQUIPOT
426		Na 87 "/fpga1/FPGA_BANK0_IO_52"
	426	Na 87 "/fpga1/FPGA_BANK0_IO_58"
427	427	St ~
428	428	$EndEQUIPOT
429	429	$EQUIPOT
430		Na 88 "/fpga1/FPGA_BANK0_IO_53"
	430	Na 88 "/fpga1/FPGA_BANK0_IO_6"
431	431	St ~
432	432	$EndEQUIPOT
433	433	$EQUIPOT
434		Na 89 "/fpga1/FPGA_BANK0_IO_56"
	434	Na 89 "/fpga1/FPGA_BANK0_IO_60"
435	435	St ~
436	436	$EndEQUIPOT
437	437	$EQUIPOT
438		Na 90 "/fpga1/FPGA_BANK0_IO_57"
	438	Na 90 "/fpga1/FPGA_BANK0_IO_63"
439	439	St ~
440	440	$EndEQUIPOT
441	441	$EQUIPOT
442		Na 91 "/fpga1/FPGA_BANK0_IO_58"
	442	Na 91 "/fpga1/FPGA_BANK0_IO_8"
443	443	St ~
444	444	$EndEQUIPOT
445	445	$EQUIPOT
446		Na 92 "/fpga1/FPGA_BANK0_IO_60"
	446	Na 92 "/fpga1/NF_ALE"
447	447	St ~
448	448	$EndEQUIPOT
449	449	$EQUIPOT
450		Na 93 "/fpga1/FPGA_BANK0_IO_62"
	450	Na 93 "/fpga1/NF_CLE"
451	451	St ~
452	452	$EndEQUIPOT
453	453	$EQUIPOT
454		Na 94 "/fpga1/FPGA_BANK0_IO_63"
	454	Na 94 "/fpga1/NF_CS1_N"
455	455	St ~
456	456	$EndEQUIPOT
457	457	$EQUIPOT
458		Na 95 "/fpga1/FPGA_BANK0_IO_8"
	458	Na 95 "/fpga1/NF_D0"
459	459	St ~
460	460	$EndEQUIPOT
461	461	$EQUIPOT
462		Na 96 "/fpga1/NF_D2"
	462	Na 96 "/fpga1/NF_D1"
463	463	St ~
464	464	$EndEQUIPOT
465	465	$EQUIPOT
466		Na 97 "/fpga1/NF_D4"
	466	Na 97 "/fpga1/NF_D3"
467	467	St ~
468	468	$EndEQUIPOT
469	469	$EQUIPOT
470		Na 98 "/fpga1/NF_D6"
	470	Na 98 "/fpga1/NF_D4"
471	471	St ~
472	472	$EndEQUIPOT
473	473	$EQUIPOT
474		Na 99 "/fpga1/NF_RNB"
	474	Na 99 "/fpga1/NF_D5"
475	475	St ~
476	476	$EndEQUIPOT
477	477	$EQUIPOT
478		Na 100 "/fpga1/NF_WE_N"
	478	Na 100 "/fpga1/NF_D6"
479	479	St ~
480	480	$EndEQUIPOT
481	481	$EQUIPOT
482		Na 101 "/fpga1/PROG_CCLK"
	482	Na 101 "/fpga1/NF_D7"
483	483	St ~
484	484	$EndEQUIPOT
485	485	$EQUIPOT
486		Na 102 "/fpga1/PROG_CSO"
	486	Na 102 "/fpga1/NF_RE_N"
487	487	St ~
488	488	$EndEQUIPOT
489	489	$EQUIPOT
490		Na 103 "/fpga1/PROG_MISO0"
	490	Na 103 "/fpga1/PROG_CCLK"
491	491	St ~
492	492	$EndEQUIPOT
493	493	$EQUIPOT
494		Na 104 "/fpga1/PROG_MISO1"
	494	Na 104 "/fpga1/PROG_CSO"
495	495	St ~
496	496	$EndEQUIPOT
497	497	$EQUIPOT
498		Na 105 "/fpga1/PROG_MISO2"
	498	Na 105 "/fpga1/PROG_MISO0"
499	499	St ~
500	500	$EndEQUIPOT
501	501	$EQUIPOT
502		Na 106 "/fpga1/PROG_MISO3"
	502	Na 106 "/fpga1/PROG_MISO1"
503	503	St ~
504	504	$EndEQUIPOT
505	505	$EQUIPOT
506		Na 107 "/fpga1/SD_CLK"
	506	Na 107 "/fpga1/PROG_MISO2"
507	507	St ~
508	508	$EndEQUIPOT
509	509	$EQUIPOT
510		Na 108 "/fpga1/SD_CMD"
	510	Na 108 "/fpga1/PROG_MISO3"
511	511	St ~
512	512	$EndEQUIPOT
513	513	$EQUIPOT
514		Na 109 "/fpga1/SD_DAT0"
	514	Na 109 "/fpga1/SD_CMD"
515	515	St ~
516	516	$EndEQUIPOT
517	517	$EQUIPOT
518		Na 110 "/fpga1/SD_DAT1"
	518	Na 110 "/fpga1/SD_DAT0"
519	519	St ~
520	520	$EndEQUIPOT
521	521	$EQUIPOT
522		Na 111 "/fpga1/SD_DAT3"
	522	Na 111 "/fpga1/SD_DAT2"
523	523	St ~
524	524	$EndEQUIPOT
525	525	$EQUIPOT
...	...
531	531	St ~
532	532	$EndEQUIPOT
533	533	$EQUIPOT
534		Na 114 "/fpga2/M0_A12"
	534	Na 114 "/fpga2/M0_A11"
535	535	St ~
536	536	$EndEQUIPOT
537	537	$EQUIPOT
538		Na 115 "/fpga2/M0_A2"
	538	Na 115 "/fpga2/M0_A12"
539	539	St ~
540	540	$EndEQUIPOT
541	541	$EQUIPOT
542		Na 116 "/fpga2/M0_A4"
	542	Na 116 "/fpga2/M0_A2"
543	543	St ~
544	544	$EndEQUIPOT
545	545	$EQUIPOT
...	...
551	551	St ~
552	552	$EndEQUIPOT
553	553	$EQUIPOT
554		Na 119 "/fpga2/M0_A8"
	554	Na 119 "/fpga2/M0_A9"
555	555	St ~
556	556	$EndEQUIPOT
557	557	$EQUIPOT
558		Na 120 "/fpga2/M0_A9"
	558	Na 120 "/fpga2/M0_DQ1"
559	559	St ~
560	560	$EndEQUIPOT
561	561	$EQUIPOT
562		Na 121 "/fpga2/M0_BA0"
	562	Na 121 "/fpga2/M0_DQ11"
563	563	St ~
564	564	$EndEQUIPOT
565	565	$EQUIPOT
566		Na 122 "/fpga2/M0_CAS#"
	566	Na 122 "/fpga2/M0_DQ2"
567	567	St ~
568	568	$EndEQUIPOT
569	569	$EQUIPOT
570		Na 123 "/fpga2/M0_CLK"
	570	Na 123 "/fpga2/M0_DQ3"
571	571	St ~
572	572	$EndEQUIPOT
573	573	$EQUIPOT
574		Na 124 "/fpga2/M0_DQ0"
	574	Na 124 "/fpga2/M0_DQ5"
575	575	St ~
576	576	$EndEQUIPOT
577	577	$EQUIPOT
578		Na 125 "/fpga2/M0_DQ1"
	578	Na 125 "/fpga2/M0_DQ8"
579	579	St ~
580	580	$EndEQUIPOT
581	581	$EQUIPOT
582		Na 126 "/fpga2/M0_DQ10"
	582	Na 126 "/fpga2/M0_DQ9"
583	583	St ~
584	584	$EndEQUIPOT
585	585	$EQUIPOT
586		Na 127 "/fpga2/M0_DQ11"
	586	Na 127 "/fpga2/M0_LDM"
587	587	St ~
588	588	$EndEQUIPOT
589	589	$EQUIPOT
590		Na 128 "/fpga2/M0_DQ15"
	590	Na 128 "/fpga2/M1_A0"
591	591	St ~
592	592	$EndEQUIPOT
593	593	$EQUIPOT
594		Na 129 "/fpga2/M0_DQ2"
	594	Na 129 "/fpga2/M1_A1"
595	595	St ~
596	596	$EndEQUIPOT
597	597	$EQUIPOT
598		Na 130 "/fpga2/M0_DQ3"
	598	Na 130 "/fpga2/M1_A12"
599	599	St ~
600	600	$EndEQUIPOT
601	601	$EQUIPOT
602		Na 131 "/fpga2/M0_DQ6"
	602	Na 131 "/fpga2/M1_A5"
603	603	St ~
604	604	$EndEQUIPOT
605	605	$EQUIPOT
606		Na 132 "/fpga2/M0_DQ7"
	606	Na 132 "/fpga2/M1_A6"
607	607	St ~
608	608	$EndEQUIPOT
609	609	$EQUIPOT
610		Na 133 "/fpga2/M0_DQ9"
	610	Na 133 "/fpga2/M1_A8"
611	611	St ~
612	612	$EndEQUIPOT
613	613	$EQUIPOT
614		Na 134 "/fpga2/M0_LDM"
	614	Na 134 "/fpga2/M1_BA1"
615	615	St ~
616	616	$EndEQUIPOT
617	617	$EQUIPOT
618		Na 135 "/fpga2/M0_LDQS"
	618	Na 135 "/fpga2/M1_CAS#"
619	619	St ~
620	620	$EndEQUIPOT
621	621	$EQUIPOT
622		Na 136 "/fpga2/M0_UDM"
	622	Na 136 "/fpga2/M1_CLK"
623	623	St ~
624	624	$EndEQUIPOT
625	625	$EQUIPOT
626		Na 137 "/fpga2/M1_A0"
	626	Na 137 "/fpga2/M1_CLK#"
627	627	St ~
628	628	$EndEQUIPOT
629	629	$EQUIPOT
630		Na 138 "/fpga2/M1_A11"
	630	Na 138 "/fpga2/M1_CS#"
631	631	St ~
632	632	$EndEQUIPOT
633	633	$EQUIPOT
634		Na 139 "/fpga2/M1_A2"
	634	Na 139 "/fpga2/M1_DQ0"
635	635	St ~
636	636	$EndEQUIPOT
637	637	$EQUIPOT
638		Na 140 "/fpga2/M1_A6"
	638	Na 140 "/fpga2/M1_DQ12"
639	639	St ~
640	640	$EndEQUIPOT
641	641	$EQUIPOT
642		Na 141 "/fpga2/M1_A7"
	642	Na 141 "/fpga2/M1_DQ13"
643	643	St ~
644	644	$EndEQUIPOT
645	645	$EQUIPOT
646		Na 142 "/fpga2/M1_A8"
	646	Na 142 "/fpga2/M1_DQ14"
647	647	St ~
648	648	$EndEQUIPOT
649	649	$EQUIPOT
650		Na 143 "/fpga2/M1_A9"
	650	Na 143 "/fpga2/M1_DQ15"
651	651	St ~
652	652	$EndEQUIPOT
653	653	$EQUIPOT
654		Na 144 "/fpga2/M1_BA1"
	654	Na 144 "/fpga2/M1_DQ3"
655	655	St ~
656	656	$EndEQUIPOT
657	657	$EQUIPOT
658		Na 145 "/fpga2/M1_CKE"
	658	Na 145 "/fpga2/M1_DQ4"
659	659	St ~
660	660	$EndEQUIPOT
661	661	$EQUIPOT
662		Na 146 "/fpga2/M1_CLK"
	662	Na 146 "/fpga2/M1_DQ5"
663	663	St ~
664	664	$EndEQUIPOT
665	665	$EQUIPOT
666		Na 147 "/fpga2/M1_CLK#"
	666	Na 147 "/fpga2/M1_DQ6"
667	667	St ~
668	668	$EndEQUIPOT
669	669	$EQUIPOT
670		Na 148 "/fpga2/M1_CS#"
	670	Na 148 "/fpga2/M1_DQ7"
671	671	St ~
672	672	$EndEQUIPOT
673	673	$EQUIPOT
674		Na 149 "/fpga2/M1_DQ0"
	674	Na 149 "/fpga2/M1_DQ8"
675	675	St ~
676	676	$EndEQUIPOT
677	677	$EQUIPOT
678		Na 150 "/fpga2/M1_DQ10"
	678	Na 150 "/fpga2/M1_DQ9"
679	679	St ~
680	680	$EndEQUIPOT
681	681	$EQUIPOT
682		Na 151 "/fpga2/M1_DQ11"
	682	Na 151 "/fpga2/M1_LDM"
683	683	St ~
684	684	$EndEQUIPOT
685	685	$EQUIPOT
686		Na 152 "/fpga2/M1_DQ14"
	686	Na 152 "/fpga2/M1_RAS#"
687	687	St ~
688	688	$EndEQUIPOT
689	689	$EQUIPOT
690		Na 153 "/fpga2/M1_DQ15"
	690	Na 153 "/fpga2/R_M0_A0"
691	691	St ~
692	692	$EndEQUIPOT
693	693	$EQUIPOT
694		Na 154 "/fpga2/M1_DQ2"
	694	Na 154 "/fpga2/R_M0_A1"
695	695	St ~
696	696	$EndEQUIPOT
697	697	$EQUIPOT
698		Na 155 "/fpga2/M1_DQ3"
	698	Na 155 "/fpga2/R_M0_A10"
699	699	St ~
700	700	$EndEQUIPOT
701	701	$EQUIPOT
702		Na 156 "/fpga2/M1_DQ4"
	702	Na 156 "/fpga2/R_M0_A11"
703	703	St ~
704	704	$EndEQUIPOT
705	705	$EQUIPOT
706		Na 157 "/fpga2/M1_DQ7"
	706	Na 157 "/fpga2/R_M0_A12"
707	707	St ~
708	708	$EndEQUIPOT
709	709	$EQUIPOT
710		Na 158 "/fpga2/M1_DQ8"
	710	Na 158 "/fpga2/R_M0_A2"
711	711	St ~
712	712	$EndEQUIPOT
713	713	$EQUIPOT
714		Na 159 "/fpga2/M1_DQ9"
	714	Na 159 "/fpga2/R_M0_A3"
715	715	St ~
716	716	$EndEQUIPOT
717	717	$EQUIPOT
718		Na 160 "/fpga2/M1_LDM"
	718	Na 160 "/fpga2/R_M0_A4"
719	719	St ~
720	720	$EndEQUIPOT
721	721	$EQUIPOT
722		Na 161 "/fpga2/M1_UDQS"
	722	Na 161 "/fpga2/R_M0_A5"
723	723	St ~
724	724	$EndEQUIPOT
725	725	$EQUIPOT
726		Na 162 "/fpga2/R_M0_A0"
	726	Na 162 "/fpga2/R_M0_A6"
727	727	St ~
728	728	$EndEQUIPOT
729	729	$EQUIPOT
730		Na 163 "/fpga2/R_M0_A1"
	730	Na 163 "/fpga2/R_M0_A7"
731	731	St ~
732	732	$EndEQUIPOT
733	733	$EQUIPOT
734		Na 164 "/fpga2/R_M0_A10"
	734	Na 164 "/fpga2/R_M0_A8"
735	735	St ~
736	736	$EndEQUIPOT
737	737	$EQUIPOT
738		Na 165 "/fpga2/R_M0_A11"
	738	Na 165 "/fpga2/R_M0_A9"
739	739	St ~
740	740	$EndEQUIPOT
741	741	$EQUIPOT
742		Na 166 "/fpga2/R_M0_A12"
	742	Na 166 "/fpga2/R_M0_BA0"
743	743	St ~
744	744	$EndEQUIPOT
745	745	$EQUIPOT
746		Na 167 "/fpga2/R_M0_A2"
	746	Na 167 "/fpga2/R_M0_BA1"
747	747	St ~
748	748	$EndEQUIPOT
749	749	$EQUIPOT
750		Na 168 "/fpga2/R_M0_A3"
	750	Na 168 "/fpga2/R_M0_CAS#"
751	751	St ~
752	752	$EndEQUIPOT
753	753	$EQUIPOT
754		Na 169 "/fpga2/R_M0_A4"
	754	Na 169 "/fpga2/R_M0_CKE"
755	755	St ~
756	756	$EndEQUIPOT
757	757	$EQUIPOT
758		Na 170 "/fpga2/R_M0_A5"
	758	Na 170 "/fpga2/R_M0_DQ0"
759	759	St ~
760	760	$EndEQUIPOT
761	761	$EQUIPOT
762		Na 171 "/fpga2/R_M0_A6"
	762	Na 171 "/fpga2/R_M0_DQ1"
763	763	St ~
764	764	$EndEQUIPOT
765	765	$EQUIPOT
766		Na 172 "/fpga2/R_M0_A7"
	766	Na 172 "/fpga2/R_M0_DQ10"
767	767	St ~
768	768	$EndEQUIPOT
769	769	$EQUIPOT
770		Na 173 "/fpga2/R_M0_A8"
	770	Na 173 "/fpga2/R_M0_DQ11"
771	771	St ~
772	772	$EndEQUIPOT
773	773	$EQUIPOT
774		Na 174 "/fpga2/R_M0_A9"
	774	Na 174 "/fpga2/R_M0_DQ12"
775	775	St ~
776	776	$EndEQUIPOT
777	777	$EQUIPOT
778		Na 175 "/fpga2/R_M0_BA0"
	778	Na 175 "/fpga2/R_M0_DQ13"
779	779	St ~
780	780	$EndEQUIPOT
781	781	$EQUIPOT
782		Na 176 "/fpga2/R_M0_BA1"
	782	Na 176 "/fpga2/R_M0_DQ14"
783	783	St ~
784	784	$EndEQUIPOT
785	785	$EQUIPOT
786		Na 177 "/fpga2/R_M0_CAS#"
	786	Na 177 "/fpga2/R_M0_DQ15"
787	787	St ~
788	788	$EndEQUIPOT
789	789	$EQUIPOT
790		Na 178 "/fpga2/R_M0_CKE"
	790	Na 178 "/fpga2/R_M0_DQ2"
791	791	St ~
792	792	$EndEQUIPOT
793	793	$EQUIPOT
794		Na 179 "/fpga2/R_M0_DQ0"
	794	Na 179 "/fpga2/R_M0_DQ3"
795	795	St ~
796	796	$EndEQUIPOT
797	797	$EQUIPOT
798		Na 180 "/fpga2/R_M0_DQ1"
	798	Na 180 "/fpga2/R_M0_DQ4"
799	799	St ~
800	800	$EndEQUIPOT
801	801	$EQUIPOT
802		Na 181 "/fpga2/R_M0_DQ10"
	802	Na 181 "/fpga2/R_M0_DQ5"
803	803	St ~
804	804	$EndEQUIPOT
805	805	$EQUIPOT
806		Na 182 "/fpga2/R_M0_DQ11"
	806	Na 182 "/fpga2/R_M0_DQ6"
807	807	St ~
808	808	$EndEQUIPOT
809	809	$EQUIPOT
810		Na 183 "/fpga2/R_M0_DQ12"
	810	Na 183 "/fpga2/R_M0_DQ7"
811	811	St ~
812	812	$EndEQUIPOT
813	813	$EQUIPOT
814		Na 184 "/fpga2/R_M0_DQ13"
	814	Na 184 "/fpga2/R_M0_DQ8"
815	815	St ~
816	816	$EndEQUIPOT
817	817	$EQUIPOT
818		Na 185 "/fpga2/R_M0_DQ14"
	818	Na 185 "/fpga2/R_M0_DQ9"
819	819	St ~
820	820	$EndEQUIPOT
821	821	$EQUIPOT
822		Na 186 "/fpga2/R_M0_DQ15"
	822	Na 186 "/fpga2/R_M0_LDM"
823	823	St ~
824	824	$EndEQUIPOT
825	825	$EQUIPOT
826		Na 187 "/fpga2/R_M0_DQ2"
	826	Na 187 "/fpga2/R_M0_LDQS"
827	827	St ~
828	828	$EndEQUIPOT
829	829	$EQUIPOT
830		Na 188 "/fpga2/R_M0_DQ3"
	830	Na 188 "/fpga2/R_M0_RAS#"
831	831	St ~
832	832	$EndEQUIPOT
833	833	$EQUIPOT
834		Na 189 "/fpga2/R_M0_DQ4"
	834	Na 189 "/fpga2/R_M0_UDM"
835	835	St ~
836	836	$EndEQUIPOT
837	837	$EQUIPOT
838		Na 190 "/fpga2/R_M0_DQ5"
	838	Na 190 "/fpga2/R_M0_UDQS"
839	839	St ~
840	840	$EndEQUIPOT
841	841	$EQUIPOT
842		Na 191 "/fpga2/R_M0_DQ6"
	842	Na 191 "/fpga2/R_M0_WE#"
843	843	St ~
844	844	$EndEQUIPOT
845	845	$EQUIPOT
846		Na 192 "/fpga2/R_M0_DQ7"
	846	Na 192 "/fpga2/R_M1_A0"
847	847	St ~
848	848	$EndEQUIPOT
849	849	$EQUIPOT
850		Na 193 "/fpga2/R_M0_DQ8"
	850	Na 193 "/fpga2/R_M1_A1"
851	851	St ~
852	852	$EndEQUIPOT
853	853	$EQUIPOT
854		Na 194 "/fpga2/R_M0_DQ9"
	854	Na 194 "/fpga2/R_M1_A10"
855	855	St ~
856	856	$EndEQUIPOT
857	857	$EQUIPOT
858		Na 195 "/fpga2/R_M0_LDM"
	858	Na 195 "/fpga2/R_M1_A11"
859	859	St ~
860	860	$EndEQUIPOT
861	861	$EQUIPOT
862		Na 196 "/fpga2/R_M0_LDQS"
	862	Na 196 "/fpga2/R_M1_A12"
863	863	St ~
864	864	$EndEQUIPOT
865	865	$EQUIPOT
866		Na 197 "/fpga2/R_M0_RAS#"
	866	Na 197 "/fpga2/R_M1_A2"
867	867	St ~
868	868	$EndEQUIPOT
869	869	$EQUIPOT
870		Na 198 "/fpga2/R_M0_UDM"
	870	Na 198 "/fpga2/R_M1_A3"
871	871	St ~
872	872	$EndEQUIPOT
873	873	$EQUIPOT
874		Na 199 "/fpga2/R_M0_UDQS"
	874	Na 199 "/fpga2/R_M1_A4"
875	875	St ~
876	876	$EndEQUIPOT
877	877	$EQUIPOT
878		Na 200 "/fpga2/R_M0_WE#"
	878	Na 200 "/fpga2/R_M1_A5"
879	879	St ~
880	880	$EndEQUIPOT
881	881	$EQUIPOT
882		Na 201 "/fpga2/R_M1_A0"
	882	Na 201 "/fpga2/R_M1_A6"
883	883	St ~
884	884	$EndEQUIPOT
885	885	$EQUIPOT
886		Na 202 "/fpga2/R_M1_A1"
	886	Na 202 "/fpga2/R_M1_A7"
887	887	St ~
888	888	$EndEQUIPOT
889	889	$EQUIPOT
890		Na 203 "/fpga2/R_M1_A10"
	890	Na 203 "/fpga2/R_M1_A8"
891	891	St ~
892	892	$EndEQUIPOT
893	893	$EQUIPOT
894		Na 204 "/fpga2/R_M1_A11"
	894	Na 204 "/fpga2/R_M1_A9"
895	895	St ~
896	896	$EndEQUIPOT
897	897	$EQUIPOT
898		Na 205 "/fpga2/R_M1_A12"
	898	Na 205 "/fpga2/R_M1_BA0"
899	899	St ~
900	900	$EndEQUIPOT
901	901	$EQUIPOT
902		Na 206 "/fpga2/R_M1_A2"
	902	Na 206 "/fpga2/R_M1_BA1"
903	903	St ~
904	904	$EndEQUIPOT
905	905	$EQUIPOT
906		Na 207 "/fpga2/R_M1_A3"
	906	Na 207 "/fpga2/R_M1_CAS#"
907	907	St ~
908	908	$EndEQUIPOT
909	909	$EQUIPOT
910		Na 208 "/fpga2/R_M1_A4"
	910	Na 208 "/fpga2/R_M1_CKE"
911	911	St ~
912	912	$EndEQUIPOT
913	913	$EQUIPOT
914		Na 209 "/fpga2/R_M1_A5"
	914	Na 209 "/fpga2/R_M1_CS#"
915	915	St ~
916	916	$EndEQUIPOT
917	917	$EQUIPOT
918		Na 210 "/fpga2/R_M1_A6"
	918	Na 210 "/fpga2/R_M1_DQ0"
919	919	St ~
920	920	$EndEQUIPOT
921	921	$EQUIPOT
922		Na 211 "/fpga2/R_M1_A7"
	922	Na 211 "/fpga2/R_M1_DQ1"
923	923	St ~
924	924	$EndEQUIPOT
925	925	$EQUIPOT
926		Na 212 "/fpga2/R_M1_A8"
	926	Na 212 "/fpga2/R_M1_DQ10"
927	927	St ~
928	928	$EndEQUIPOT
929	929	$EQUIPOT
930		Na 213 "/fpga2/R_M1_A9"
	930	Na 213 "/fpga2/R_M1_DQ11"
931	931	St ~
932	932	$EndEQUIPOT
933	933	$EQUIPOT
934		Na 214 "/fpga2/R_M1_BA0"
	934	Na 214 "/fpga2/R_M1_DQ12"
935	935	St ~
936	936	$EndEQUIPOT
937	937	$EQUIPOT
938		Na 215 "/fpga2/R_M1_BA1"
	938	Na 215 "/fpga2/R_M1_DQ13"
939	939	St ~
940	940	$EndEQUIPOT
941	941	$EQUIPOT
942		Na 216 "/fpga2/R_M1_CAS#"
	942	Na 216 "/fpga2/R_M1_DQ14"
943	943	St ~
944	944	$EndEQUIPOT
945	945	$EQUIPOT
946		Na 217 "/fpga2/R_M1_CKE"
	946	Na 217 "/fpga2/R_M1_DQ15"
947	947	St ~
948	948	$EndEQUIPOT
949	949	$EQUIPOT
950		Na 218 "/fpga2/R_M1_CS#"
	950	Na 218 "/fpga2/R_M1_DQ2"
951	951	St ~
952	952	$EndEQUIPOT
953	953	$EQUIPOT
954		Na 219 "/fpga2/R_M1_DQ0"
	954	Na 219 "/fpga2/R_M1_DQ3"
955	955	St ~
956	956	$EndEQUIPOT
957	957	$EQUIPOT
958		Na 220 "/fpga2/R_M1_DQ1"
	958	Na 220 "/fpga2/R_M1_DQ4"
959	959	St ~
960	960	$EndEQUIPOT
961	961	$EQUIPOT
962		Na 221 "/fpga2/R_M1_DQ10"
	962	Na 221 "/fpga2/R_M1_DQ5"
963	963	St ~
964	964	$EndEQUIPOT
965	965	$EQUIPOT
966		Na 222 "/fpga2/R_M1_DQ11"
	966	Na 222 "/fpga2/R_M1_DQ6"
967	967	St ~
968	968	$EndEQUIPOT
969	969	$EQUIPOT
970		Na 223 "/fpga2/R_M1_DQ12"
	970	Na 223 "/fpga2/R_M1_DQ7"
971	971	St ~
972	972	$EndEQUIPOT
973	973	$EQUIPOT
974		Na 224 "/fpga2/R_M1_DQ13"
	974	Na 224 "/fpga2/R_M1_DQ8"
975	975	St ~
976	976	$EndEQUIPOT
977	977	$EQUIPOT
978		Na 225 "/fpga2/R_M1_DQ14"
	978	Na 225 "/fpga2/R_M1_DQ9"
979	979	St ~
980	980	$EndEQUIPOT
981	981	$EQUIPOT
982		Na 226 "/fpga2/R_M1_DQ15"
	982	Na 226 "/fpga2/R_M1_LDM"
983	983	St ~
984	984	$EndEQUIPOT
985	985	$EQUIPOT
986		Na 227 "/fpga2/R_M1_DQ2"
	986	Na 227 "/fpga2/R_M1_LDQS"
987	987	St ~
988	988	$EndEQUIPOT
989	989	$EQUIPOT
990		Na 228 "/fpga2/R_M1_DQ3"
	990	Na 228 "/fpga2/R_M1_RAS#"
991	991	St ~
992	992	$EndEQUIPOT
993	993	$EQUIPOT
994		Na 229 "/fpga2/R_M1_DQ4"
	994	Na 229 "/fpga2/R_M1_UDM"
995	995	St ~
996	996	$EndEQUIPOT
997	997	$EQUIPOT
998		Na 230 "/fpga2/R_M1_DQ5"
	998	Na 230 "/fpga2/R_M1_UDQS"
999	999	St ~
1000	1000	$EndEQUIPOT
1001	1001	$EQUIPOT
1002		Na 231 "/fpga2/R_M1_DQ6"
	1002	Na 231 "/fpga2/R_M1_WE#"
1003	1003	St ~
1004	1004	$EndEQUIPOT
1005	1005	$EQUIPOT
1006		Na 232 "/fpga2/R_M1_DQ7"
	1006	Na 232 "/fpga2/USBA_RCV"
1007	1007	St ~
1008	1008	$EndEQUIPOT
1009	1009	$EQUIPOT
1010		Na 233 "/fpga2/R_M1_DQ8"
	1010	Na 233 "/fpga2/USBA_VP"
1011	1011	St ~
1012	1012	$EndEQUIPOT
1013	1013	$EQUIPOT
1014		Na 234 "/fpga2/R_M1_DQ9"
	1014	Na 234 "/fpga2/USBD_OE_N"
1015	1015	St ~
1016	1016	$EndEQUIPOT
1017	1017	$EQUIPOT
1018		Na 235 "/fpga2/R_M1_LDM"
	1018	Na 235 "/fpga2/USBD_RCV"
1019	1019	St ~
1020	1020	$EndEQUIPOT
1021	1021	$EQUIPOT
1022		Na 236 "/fpga2/R_M1_LDQS"
	1022	Na 236 "/fpga2/USBD_VP"
1023	1023	St ~
1024	1024	$EndEQUIPOT
1025	1025	$EQUIPOT
1026		Na 237 "/fpga2/R_M1_RAS#"
	1026	Na 237 "/sdram/M0_A1"
1027	1027	St ~
1028	1028	$EndEQUIPOT
1029	1029	$EQUIPOT
1030		Na 238 "/fpga2/R_M1_UDM"
	1030	Na 238 "/sdram/M0_A3"
1031	1031	St ~
1032	1032	$EndEQUIPOT
1033	1033	$EQUIPOT
1034		Na 239 "/fpga2/R_M1_UDQS"
	1034	Na 239 "/sdram/M0_A4"
1035	1035	St ~
1036	1036	$EndEQUIPOT
1037	1037	$EQUIPOT
1038		Na 240 "/fpga2/R_M1_WE#"
	1038	Na 240 "/sdram/M0_A6"
1039	1039	St ~
1040	1040	$EndEQUIPOT
1041	1041	$EQUIPOT
1042		Na 241 "/fpga2/USBA_RCV"
	1042	Na 241 "/sdram/M0_A8"
1043	1043	St ~
1044	1044	$EndEQUIPOT
1045	1045	$EQUIPOT
1046		Na 242 "/fpga2/USBA_VP"
	1046	Na 242 "/sdram/M0_BA0"
1047	1047	St ~
1048	1048	$EndEQUIPOT
1049	1049	$EQUIPOT
1050		Na 243 "/fpga2/USBD_RCV"
	1050	Na 243 "/sdram/M0_BA1"
1051	1051	St ~
1052	1052	$EndEQUIPOT
1053	1053	$EQUIPOT
1054		Na 244 "/fpga2/USBD_VM"
	1054	Na 244 "/sdram/M0_CAS#"
1055	1055	St ~
1056	1056	$EndEQUIPOT
1057	1057	$EQUIPOT
1058		Na 245 "/fpga2/USBD_VP"
	1058	Na 245 "/sdram/M0_CKE"
1059	1059	St ~
1060	1060	$EndEQUIPOT
1061	1061	$EQUIPOT
1062		Na 246 "/sdram/M0_A1"
	1062	Na 246 "/sdram/M0_CLK"
1063	1063	St ~
1064	1064	$EndEQUIPOT
1065	1065	$EQUIPOT
1066		Na 247 "/sdram/M0_A11"
	1066	Na 247 "/sdram/M0_CLK#"
1067	1067	St ~
1068	1068	$EndEQUIPOT
1069	1069	$EQUIPOT
1070		Na 248 "/sdram/M0_A3"
	1070	Na 248 "/sdram/M0_DQ0"
1071	1071	St ~
1072	1072	$EndEQUIPOT
1073	1073	$EQUIPOT
1074		Na 249 "/sdram/M0_A6"
	1074	Na 249 "/sdram/M0_DQ10"
1075	1075	St ~
1076	1076	$EndEQUIPOT
1077	1077	$EQUIPOT
1078		Na 250 "/sdram/M0_BA1"
	1078	Na 250 "/sdram/M0_DQ12"
1079	1079	St ~
1080	1080	$EndEQUIPOT
1081	1081	$EQUIPOT
1082		Na 251 "/sdram/M0_CKE"
	1082	Na 251 "/sdram/M0_DQ13"
1083	1083	St ~
1084	1084	$EndEQUIPOT
1085	1085	$EQUIPOT
1086		Na 252 "/sdram/M0_CLK#"
	1086	Na 252 "/sdram/M0_DQ14"
1087	1087	St ~
1088	1088	$EndEQUIPOT
1089	1089	$EQUIPOT
1090		Na 253 "/sdram/M0_DQ12"
	1090	Na 253 "/sdram/M0_DQ15"
1091	1091	St ~
1092	1092	$EndEQUIPOT
1093	1093	$EQUIPOT
1094		Na 254 "/sdram/M0_DQ13"
	1094	Na 254 "/sdram/M0_DQ4"
1095	1095	St ~
1096	1096	$EndEQUIPOT
1097	1097	$EQUIPOT
1098		Na 255 "/sdram/M0_DQ14"
	1098	Na 255 "/sdram/M0_DQ6"
1099	1099	St ~
1100	1100	$EndEQUIPOT
1101	1101	$EQUIPOT
1102		Na 256 "/sdram/M0_DQ4"
	1102	Na 256 "/sdram/M0_DQ7"
1103	1103	St ~
1104	1104	$EndEQUIPOT
1105	1105	$EQUIPOT
1106		Na 257 "/sdram/M0_DQ5"
	1106	Na 257 "/sdram/M0_LDQS"
1107	1107	St ~
1108	1108	$EndEQUIPOT
1109	1109	$EQUIPOT
1110		Na 258 "/sdram/M0_DQ8"
	1110	Na 258 "/sdram/M0_RAS#"
1111	1111	St ~
1112	1112	$EndEQUIPOT
1113	1113	$EQUIPOT
1114		Na 259 "/sdram/M0_RAS#"
	1114	Na 259 "/sdram/M0_UDM"
1115	1115	St ~
1116	1116	$EndEQUIPOT
1117	1117	$EQUIPOT
...	...
1127	1127	St ~
1128	1128	$EndEQUIPOT
1129	1129	$EQUIPOT
1130		Na 263 "/sdram/M1_A1"
	1130	Na 263 "/sdram/M1_A10"
1131	1131	St ~
1132	1132	$EndEQUIPOT
1133	1133	$EQUIPOT
1134		Na 264 "/sdram/M1_A10"
	1134	Na 264 "/sdram/M1_A11"
1135	1135	St ~
1136	1136	$EndEQUIPOT
1137	1137	$EQUIPOT
1138		Na 265 "/sdram/M1_A12"
	1138	Na 265 "/sdram/M1_A2"
1139	1139	St ~
1140	1140	$EndEQUIPOT
1141	1141	$EQUIPOT
...	...
1147	1147	St ~
1148	1148	$EndEQUIPOT
1149	1149	$EQUIPOT
1150		Na 268 "/sdram/M1_A5"
	1150	Na 268 "/sdram/M1_A7"
1151	1151	St ~
1152	1152	$EndEQUIPOT
1153	1153	$EQUIPOT
1154		Na 269 "/sdram/M1_BA0"
	1154	Na 269 "/sdram/M1_A9"
1155	1155	St ~
1156	1156	$EndEQUIPOT
1157	1157	$EQUIPOT
1158		Na 270 "/sdram/M1_CAS#"
	1158	Na 270 "/sdram/M1_BA0"
1159	1159	St ~
1160	1160	$EndEQUIPOT
1161	1161	$EQUIPOT
1162		Na 271 "/sdram/M1_DQ1"
	1162	Na 271 "/sdram/M1_CKE"
1163	1163	St ~
1164	1164	$EndEQUIPOT
1165	1165	$EQUIPOT
1166		Na 272 "/sdram/M1_DQ12"
	1166	Na 272 "/sdram/M1_DQ1"
1167	1167	St ~
1168	1168	$EndEQUIPOT
1169	1169	$EQUIPOT
1170		Na 273 "/sdram/M1_DQ13"
	1170	Na 273 "/sdram/M1_DQ10"
1171	1171	St ~
1172	1172	$EndEQUIPOT
1173	1173	$EQUIPOT
1174		Na 274 "/sdram/M1_DQ5"
	1174	Na 274 "/sdram/M1_DQ11"
1175	1175	St ~
1176	1176	$EndEQUIPOT
1177	1177	$EQUIPOT
1178		Na 275 "/sdram/M1_DQ6"
	1178	Na 275 "/sdram/M1_DQ2"
1179	1179	St ~
1180	1180	$EndEQUIPOT
1181	1181	$EQUIPOT
...	...
1183	1183	St ~
1184	1184	$EndEQUIPOT
1185	1185	$EQUIPOT
1186		Na 277 "/sdram/M1_RAS#"
	1186	Na 277 "/sdram/M1_UDM"
1187	1187	St ~
1188	1188	$EndEQUIPOT
1189	1189	$EQUIPOT
1190		Na 278 "/sdram/M1_UDM"
	1190	Na 278 "/sdram/M1_UDQS"
1191	1191	St ~
1192	1192	$EndEQUIPOT
1193	1193	$EQUIPOT
...	...
1227	1227	St ~
1228	1228	$EndEQUIPOT
1229	1229	$EQUIPOT
1230		Na 288 "/usb/USBD_OE_N"
	1230	Na 288 "/usb/USBD_SPD"
1231	1231	St ~
1232	1232	$EndEQUIPOT
1233	1233	$EQUIPOT
1234		Na 289 "/usb/USBD_SPD"
	1234	Na 289 "/usb/USBD_VM"
1235	1235	St ~
1236	1236	$EndEQUIPOT
1237	1237	$EQUIPOT
...	...
1247	1247	St ~
1248	1248	$EndEQUIPOT
1249	1249	$EQUIPOT
1250		Na 293 "N-000120"
	1250	Na 293 "N-000121"
1251	1251	St ~
1252	1252	$EndEQUIPOT
1253	1253	$EQUIPOT
1254		Na 294 "N-000121"
	1254	Na 294 "N-000124"
1255	1255	St ~
1256	1256	$EndEQUIPOT
1257	1257	$EQUIPOT
1258		Na 295 "N-000125"
	1258	Na 295 "N-000126"
1259	1259	St ~
1260	1260	$EndEQUIPOT
1261	1261	$EQUIPOT
...	...
1315	1315	St ~
1316	1316	$EndEQUIPOT
1317	1317	$EQUIPOT
1318		Na 310 "N-000165"
	1318	Na 310 "N-000164"
1319	1319	St ~
1320	1320	$EndEQUIPOT
1321	1321	$EQUIPOT
1322		Na 311 "N-000166"
	1322	Na 311 "N-000165"
1323	1323	St ~
1324	1324	$EndEQUIPOT
1325	1325	$EQUIPOT
...	...
1383	1383	St ~
1384	1384	$EndEQUIPOT
1385	1385	$EQUIPOT
1386		Na 327 "N-000184"
	1386	Na 327 "N-000182"
1387	1387	St ~
1388	1388	$EndEQUIPOT
1389	1389	$EQUIPOT
...	...
1395	1395	St ~
1396	1396	$EndEQUIPOT
1397	1397	$EQUIPOT
1398		Na 330 "N-000190"
	1398	Na 330 "N-000187"
1399	1399	St ~
1400	1400	$EndEQUIPOT
1401	1401	$EQUIPOT
1402		Na 331 "N-000201"
	1402	Na 331 "N-000191"
1403	1403	St ~
1404	1404	$EndEQUIPOT
1405	1405	$EQUIPOT
1406		Na 332 "N-000202"
	1406	Na 332 "N-000197"
1407	1407	St ~
1408	1408	$EndEQUIPOT
1409	1409	$EQUIPOT
1410		Na 333 "N-000203"
	1410	Na 333 "N-000198"
1411	1411	St ~
1412	1412	$EndEQUIPOT
1413	1413	$EQUIPOT
1414		Na 334 "N-000362"
	1414	Na 334 "N-000363"
1415	1415	St ~
1416	1416	$EndEQUIPOT
1417	1417	$EQUIPOT
1418		Na 335 "N-000365"
	1418	Na 335 "N-000366"
1419	1419	St ~
1420	1420	$EndEQUIPOT
1421	1421	$EQUIPOT
1422	1422	Na 336 "VCCO2"
1423	1423	St ~
1424	1424	$EndEQUIPOT
	1425	$EQUIPOT
	1426	Na 337 "Vin"
	1427	St ~
	1428	$EndEQUIPOT
1425	1429	$NCLASS
1426	1430	Name "Default"
1427	1431	Desc "This is the default net class."
...	...
1435	1439	AddNet "+1.8V"
1436	1440	AddNet "/ether/ETH_A1.8V"
1437	1441	AddNet "/ether/ETH_A3.3V"
1438		AddNet "/ether/ETH_CLK"
1439	1442	AddNet "/ether/ETH_COL"
1440		AddNet "/ether/ETH_CRS"
1441	1443	AddNet "/ether/ETH_INT"
1442	1444	AddNet "/ether/ETH_LED0"
1443	1445	AddNet "/ether/ETH_LED1"
1444		AddNet "/ether/ETH_MDC"
1445	1446	AddNet "/ether/ETH_MDIO"
1446	1447	AddNet "/ether/ETH_PLL1.8V"
1447		AddNet "/ether/ETH_RXC"
1448	1448	AddNet "/ether/ETH_RXDV"
1449		AddNet "/ether/ETH_TXD0"
1450		AddNet "/ether/ETH_TXD3"
	1449	AddNet "/ether/ETH_RXER"
	1450	AddNet "/ether/ETH_TXD2"
1451	1451	AddNet "/ether/ETH_TXER"
1452	1452	AddNet "/ether/MAG_RX+"
1453	1453	AddNet "/ether/MAG_RX-"
1454	1454	AddNet "/ether/MAG_SHIELD"
1455	1455	AddNet "/ether/MAG_TX+"
1456	1456	AddNet "/ether/MAG_TX-"
1457		AddNet "/expansion/FPGA_BANK0_IO_1"
1458		AddNet "/expansion/FPGA_BANK0_IO_10"
1459	1457	AddNet "/expansion/FPGA_BANK0_IO_11"
	1458	AddNet "/expansion/FPGA_BANK0_IO_12"
	1459	AddNet "/expansion/FPGA_BANK0_IO_14"
1460	1460	AddNet "/expansion/FPGA_BANK0_IO_15"
1461		AddNet "/expansion/FPGA_BANK0_IO_17"
1462		AddNet "/expansion/FPGA_BANK0_IO_2"
1463		AddNet "/expansion/FPGA_BANK0_IO_20"
1464		AddNet "/expansion/FPGA_BANK0_IO_21"
1465		AddNet "/expansion/FPGA_BANK0_IO_29"
	1461	AddNet "/expansion/FPGA_BANK0_IO_22"
	1462	AddNet "/expansion/FPGA_BANK0_IO_24"
	1463	AddNet "/expansion/FPGA_BANK0_IO_28"
1466	1464	AddNet "/expansion/FPGA_BANK0_IO_3"
1467		AddNet "/expansion/FPGA_BANK0_IO_32"
	1465	AddNet "/expansion/FPGA_BANK0_IO_33"
1468	1466	AddNet "/expansion/FPGA_BANK0_IO_34"
	1467	AddNet "/expansion/FPGA_BANK0_IO_36"
1469	1468	AddNet "/expansion/FPGA_BANK0_IO_38"
1470	1469	AddNet "/expansion/FPGA_BANK0_IO_39"
1471	1470	AddNet "/expansion/FPGA_BANK0_IO_40"
1472	1471	AddNet "/expansion/FPGA_BANK0_IO_43"
	1472	AddNet "/expansion/FPGA_BANK0_IO_44"
	1473	AddNet "/expansion/FPGA_BANK0_IO_45"
1473	1474	AddNet "/expansion/FPGA_BANK0_IO_46"
1474	1475	AddNet "/expansion/FPGA_BANK0_IO_47"
	1476	AddNet "/expansion/FPGA_BANK0_IO_48"
1475	1477	AddNet "/expansion/FPGA_BANK0_IO_5"
1476		AddNet "/expansion/FPGA_BANK0_IO_50"
1477		AddNet "/expansion/FPGA_BANK0_IO_54"
1478		AddNet "/expansion/FPGA_BANK0_IO_6"
	1478	AddNet "/expansion/FPGA_BANK0_IO_51"
	1479	AddNet "/expansion/FPGA_BANK0_IO_62"
1479	1480	AddNet "/expansion/FPGA_BANK0_IO_7"
1480	1481	AddNet "/expansion/FPGA_BANK0_IO_9"
1481		AddNet "/flash/NF_ALE"
1482		AddNet "/flash/NF_CLE"
1483		AddNet "/flash/NF_CS1_N"
1484		AddNet "/flash/NF_D0"
1485		AddNet "/flash/NF_D1"
1486		AddNet "/flash/NF_D3"
1487		AddNet "/flash/NF_D5"
1488		AddNet "/flash/NF_D7"
1489		AddNet "/flash/NF_RE_N"
1490		AddNet "/flash/SD_DAT2"
	1482	AddNet "/flash/NF_D2"
	1483	AddNet "/flash/NF_RNB"
	1484	AddNet "/flash/NF_WE_N"
	1485	AddNet "/flash/SD_CLK"
	1486	AddNet "/flash/SD_DAT1"
	1487	AddNet "/flash/SD_DAT3"
	1488	AddNet "/fpga1/ETH_CLK"
	1489	AddNet "/fpga1/ETH_CRS"
	1490	AddNet "/fpga1/ETH_MDC"
1491	1491	AddNet "/fpga1/ETH_RESET_N"
	1492	AddNet "/fpga1/ETH_RXC"
1492	1493	AddNet "/fpga1/ETH_RXD0"
1493	1494	AddNet "/fpga1/ETH_RXD1"
1494	1495	AddNet "/fpga1/ETH_RXD2"
1495	1496	AddNet "/fpga1/ETH_RXD3"
1496		AddNet "/fpga1/ETH_RXER"
1497	1497	AddNet "/fpga1/ETH_TXC"
	1498	AddNet "/fpga1/ETH_TXD0"
1498	1499	AddNet "/fpga1/ETH_TXD1"
1499		AddNet "/fpga1/ETH_TXD2"
	1500	AddNet "/fpga1/ETH_TXD3"
1500	1501	AddNet "/fpga1/ETH_TXEN"
1501		AddNet "/fpga1/FPGA_BANK0_IO_12"
1502		AddNet "/fpga1/FPGA_BANK0_IO_14"
	1502	AddNet "/fpga1/FPGA_BANK0_IO_1"
	1503	AddNet "/fpga1/FPGA_BANK0_IO_10"
	1504	AddNet "/fpga1/FPGA_BANK0_IO_17"
1503	1505	AddNet "/fpga1/FPGA_BANK0_IO_18"
1504		AddNet "/fpga1/FPGA_BANK0_IO_22"
1505		AddNet "/fpga1/FPGA_BANK0_IO_24"
	1506	AddNet "/fpga1/FPGA_BANK0_IO_2"
	1507	AddNet "/fpga1/FPGA_BANK0_IO_20"
	1508	AddNet "/fpga1/FPGA_BANK0_IO_21"
1506	1509	AddNet "/fpga1/FPGA_BANK0_IO_25"
1507	1510	AddNet "/fpga1/FPGA_BANK0_IO_27"
1508		AddNet "/fpga1/FPGA_BANK0_IO_28"
	1511	AddNet "/fpga1/FPGA_BANK0_IO_29"
1509	1512	AddNet "/fpga1/FPGA_BANK0_IO_30"
1510		AddNet "/fpga1/FPGA_BANK0_IO_33"
1511		AddNet "/fpga1/FPGA_BANK0_IO_36"
1512		AddNet "/fpga1/FPGA_BANK0_IO_44"
1513		AddNet "/fpga1/FPGA_BANK0_IO_45"
1514		AddNet "/fpga1/FPGA_BANK0_IO_48"
	1513	AddNet "/fpga1/FPGA_BANK0_IO_32"
1515	1514	AddNet "/fpga1/FPGA_BANK0_IO_49"
1516		AddNet "/fpga1/FPGA_BANK0_IO_51"
	1515	AddNet "/fpga1/FPGA_BANK0_IO_50"
1517	1516	AddNet "/fpga1/FPGA_BANK0_IO_52"
1518	1517	AddNet "/fpga1/FPGA_BANK0_IO_53"
	1518	AddNet "/fpga1/FPGA_BANK0_IO_54"
1519	1519	AddNet "/fpga1/FPGA_BANK0_IO_56"
1520	1520	AddNet "/fpga1/FPGA_BANK0_IO_57"
1521	1521	AddNet "/fpga1/FPGA_BANK0_IO_58"
	1522	AddNet "/fpga1/FPGA_BANK0_IO_6"
1522	1523	AddNet "/fpga1/FPGA_BANK0_IO_60"
1523		AddNet "/fpga1/FPGA_BANK0_IO_62"
1524	1524	AddNet "/fpga1/FPGA_BANK0_IO_63"
1525	1525	AddNet "/fpga1/FPGA_BANK0_IO_8"
1526		AddNet "/fpga1/NF_D2"
	1526	AddNet "/fpga1/NF_ALE"
	1527	AddNet "/fpga1/NF_CLE"
	1528	AddNet "/fpga1/NF_CS1_N"
	1529	AddNet "/fpga1/NF_D0"
	1530	AddNet "/fpga1/NF_D1"
	1531	AddNet "/fpga1/NF_D3"
1527	1532	AddNet "/fpga1/NF_D4"
	1533	AddNet "/fpga1/NF_D5"
1528	1534	AddNet "/fpga1/NF_D6"
1529		AddNet "/fpga1/NF_RNB"
1530		AddNet "/fpga1/NF_WE_N"
	1535	AddNet "/fpga1/NF_D7"
	1536	AddNet "/fpga1/NF_RE_N"
1531	1537	AddNet "/fpga1/PROG_CCLK"
1532	1538	AddNet "/fpga1/PROG_CSO"
1533	1539	AddNet "/fpga1/PROG_MISO0"
1534	1540	AddNet "/fpga1/PROG_MISO1"
1535	1541	AddNet "/fpga1/PROG_MISO2"
1536	1542	AddNet "/fpga1/PROG_MISO3"
1537		AddNet "/fpga1/SD_CLK"
1538	1543	AddNet "/fpga1/SD_CMD"
1539	1544	AddNet "/fpga1/SD_DAT0"
1540		AddNet "/fpga1/SD_DAT1"
1541		AddNet "/fpga1/SD_DAT3"
	1545	AddNet "/fpga1/SD_DAT2"
1542	1546	AddNet "/fpga2/M0_A0"
1543	1547	AddNet "/fpga2/M0_A10"
	1548	AddNet "/fpga2/M0_A11"
1544	1549	AddNet "/fpga2/M0_A12"
1545	1550	AddNet "/fpga2/M0_A2"
1546		AddNet "/fpga2/M0_A4"
1547	1551	AddNet "/fpga2/M0_A5"
1548	1552	AddNet "/fpga2/M0_A7"
1549		AddNet "/fpga2/M0_A8"
1550	1553	AddNet "/fpga2/M0_A9"
1551		AddNet "/fpga2/M0_BA0"
1552		AddNet "/fpga2/M0_CAS#"
1553		AddNet "/fpga2/M0_CLK"
1554		AddNet "/fpga2/M0_DQ0"
1555	1554	AddNet "/fpga2/M0_DQ1"
1556		AddNet "/fpga2/M0_DQ10"
1557	1555	AddNet "/fpga2/M0_DQ11"
1558		AddNet "/fpga2/M0_DQ15"
1559	1556	AddNet "/fpga2/M0_DQ2"
1560	1557	AddNet "/fpga2/M0_DQ3"
1561		AddNet "/fpga2/M0_DQ6"
1562		AddNet "/fpga2/M0_DQ7"
	1558	AddNet "/fpga2/M0_DQ5"
	1559	AddNet "/fpga2/M0_DQ8"
1563	1560	AddNet "/fpga2/M0_DQ9"
1564	1561	AddNet "/fpga2/M0_LDM"
1565		AddNet "/fpga2/M0_LDQS"
1566		AddNet "/fpga2/M0_UDM"
1567	1562	AddNet "/fpga2/M1_A0"
1568		AddNet "/fpga2/M1_A11"
1569		AddNet "/fpga2/M1_A2"
	1563	AddNet "/fpga2/M1_A1"
	1564	AddNet "/fpga2/M1_A12"
	1565	AddNet "/fpga2/M1_A5"
1570	1566	AddNet "/fpga2/M1_A6"
1571		AddNet "/fpga2/M1_A7"
1572	1567	AddNet "/fpga2/M1_A8"
1573		AddNet "/fpga2/M1_A9"
1574	1568	AddNet "/fpga2/M1_BA1"
1575		AddNet "/fpga2/M1_CKE"
	1569	AddNet "/fpga2/M1_CAS#"
1576	1570	AddNet "/fpga2/M1_CLK"
1577	1571	AddNet "/fpga2/M1_CLK#"
1578	1572	AddNet "/fpga2/M1_CS#"
1579	1573	AddNet "/fpga2/M1_DQ0"
1580		AddNet "/fpga2/M1_DQ10"
1581		AddNet "/fpga2/M1_DQ11"
	1574	AddNet "/fpga2/M1_DQ12"
	1575	AddNet "/fpga2/M1_DQ13"
1582	1576	AddNet "/fpga2/M1_DQ14"
1583	1577	AddNet "/fpga2/M1_DQ15"
1584		AddNet "/fpga2/M1_DQ2"
1585	1578	AddNet "/fpga2/M1_DQ3"
1586	1579	AddNet "/fpga2/M1_DQ4"
	1580	AddNet "/fpga2/M1_DQ5"
	1581	AddNet "/fpga2/M1_DQ6"
1587	1582	AddNet "/fpga2/M1_DQ7"
1588	1583	AddNet "/fpga2/M1_DQ8"
1589	1584	AddNet "/fpga2/M1_DQ9"
1590	1585	AddNet "/fpga2/M1_LDM"
1591		AddNet "/fpga2/M1_UDQS"
	1586	AddNet "/fpga2/M1_RAS#"
1592	1587	AddNet "/fpga2/R_M0_A0"
1593	1588	AddNet "/fpga2/R_M0_A1"
1594	1589	AddNet "/fpga2/R_M0_A10"
...	...
1670	1665	AddNet "/fpga2/R_M1_WE#"
1671	1666	AddNet "/fpga2/USBA_RCV"
1672	1667	AddNet "/fpga2/USBA_VP"
	1668	AddNet "/fpga2/USBD_OE_N"
1673	1669	AddNet "/fpga2/USBD_RCV"
1674		AddNet "/fpga2/USBD_VM"
1675	1670	AddNet "/fpga2/USBD_VP"
1676	1671	AddNet "/sdram/M0_A1"
1677		AddNet "/sdram/M0_A11"
1678	1672	AddNet "/sdram/M0_A3"
	1673	AddNet "/sdram/M0_A4"
1679	1674	AddNet "/sdram/M0_A6"
	1675	AddNet "/sdram/M0_A8"
	1676	AddNet "/sdram/M0_BA0"
1680	1677	AddNet "/sdram/M0_BA1"
	1678	AddNet "/sdram/M0_CAS#"
1681	1679	AddNet "/sdram/M0_CKE"
	1680	AddNet "/sdram/M0_CLK"
1682	1681	AddNet "/sdram/M0_CLK#"
	1682	AddNet "/sdram/M0_DQ0"
	1683	AddNet "/sdram/M0_DQ10"
1683	1684	AddNet "/sdram/M0_DQ12"
1684	1685	AddNet "/sdram/M0_DQ13"
1685	1686	AddNet "/sdram/M0_DQ14"
	1687	AddNet "/sdram/M0_DQ15"
1686	1688	AddNet "/sdram/M0_DQ4"
1687		AddNet "/sdram/M0_DQ5"
1688		AddNet "/sdram/M0_DQ8"
	1689	AddNet "/sdram/M0_DQ6"
	1690	AddNet "/sdram/M0_DQ7"
	1691	AddNet "/sdram/M0_LDQS"
1689	1692	AddNet "/sdram/M0_RAS#"
	1693	AddNet "/sdram/M0_UDM"
1690	1694	AddNet "/sdram/M0_UDQS"
1691	1695	AddNet "/sdram/M0_VREF"
1692	1696	AddNet "/sdram/M0_WE#"
1693		AddNet "/sdram/M1_A1"
1694	1697	AddNet "/sdram/M1_A10"
1695		AddNet "/sdram/M1_A12"
	1698	AddNet "/sdram/M1_A11"
	1699	AddNet "/sdram/M1_A2"
1696	1700	AddNet "/sdram/M1_A3"
1697	1701	AddNet "/sdram/M1_A4"
1698		AddNet "/sdram/M1_A5"
	1702	AddNet "/sdram/M1_A7"
	1703	AddNet "/sdram/M1_A9"
1699	1704	AddNet "/sdram/M1_BA0"
1700		AddNet "/sdram/M1_CAS#"
	1705	AddNet "/sdram/M1_CKE"
1701	1706	AddNet "/sdram/M1_DQ1"
1702		AddNet "/sdram/M1_DQ12"
1703		AddNet "/sdram/M1_DQ13"
1704		AddNet "/sdram/M1_DQ5"
1705		AddNet "/sdram/M1_DQ6"
	1707	AddNet "/sdram/M1_DQ10"
	1708	AddNet "/sdram/M1_DQ11"
	1709	AddNet "/sdram/M1_DQ2"
1706	1710	AddNet "/sdram/M1_LDQS"
1707		AddNet "/sdram/M1_RAS#"
1708	1711	AddNet "/sdram/M1_UDM"
	1712	AddNet "/sdram/M1_UDQS"
1709	1713	AddNet "/sdram/M1_VREF"
1710	1714	AddNet "/sdram/M1_WE#"
1711	1715	AddNet "/usb/USBA_D+"
...	...
1715	1719	AddNet "/usb/USBA_VM"
1716	1720	AddNet "/usb/USBD_D+"
1717	1721	AddNet "/usb/USBD_D-"
1718		AddNet "/usb/USBD_OE_N"
1719	1722	AddNet "/usb/USBD_SPD"
	1723	AddNet "/usb/USBD_VM"
1720	1724	AddNet "/usb/USB_CASE_DEV"
1721	1725	AddNet "/usb/USB_CASE_HOST"
1722		AddNet "N-000120"
1723	1726	AddNet "N-000121"
1724		AddNet "N-000125"
	1727	AddNet "N-000124"
	1728	AddNet "N-000126"
1725	1729	AddNet "N-000141"
1726	1730	AddNet "N-000142"
1727	1731	AddNet "N-000143"
...	...
1736	1740	AddNet "N-000161"
1737	1741	AddNet "N-000162"
1738	1742	AddNet "N-000163"
	1743	AddNet "N-000164"
1739	1744	AddNet "N-000165"
1740		AddNet "N-000166"
1741	1745	AddNet "N-000167"
1742	1746	AddNet "N-000168"
1743	1747	AddNet "N-000169"
...	...
1753	1757	AddNet "N-000179"
1754	1758	AddNet "N-000180"
1755	1759	AddNet "N-000181"
1756		AddNet "N-000184"
	1760	AddNet "N-000182"
1757	1761	AddNet "N-000185"
1758	1762	AddNet "N-000186"
1759		AddNet "N-000190"
1760		AddNet "N-000201"
1761		AddNet "N-000202"
1762		AddNet "N-000203"
1763		AddNet "N-000362"
1764		AddNet "N-000365"
	1763	AddNet "N-000187"
	1764	AddNet "N-000191"
	1765	AddNet "N-000197"
	1766	AddNet "N-000198"
	1767	AddNet "N-000363"
	1768	AddNet "N-000366"
1765	1769	AddNet "VCCO2"
	1770	AddNet "Vin"
1766	1771	$EndNCLASS
1767	1772	$NCLASS
1768	1773	Name "ADDRESS/DDR"
...	...
1878	1883	Sh "2" R 197 355 0 0 900
1879	1884	Dr 0 0 0
1880	1885	At SMD N 00888000
1881		Ne 312 "N-000167"
	1886	Ne 314 "N-000169"
1882	1887	Po -249 1003
1883	1888	$EndPAD
1884	1889	$PAD
1885	1890	Sh "7" R 197 355 0 0 900
1886	1891	Dr 0 0 0
1887	1892	At SMD N 00888000
1888		Ne 312 "N-000167"
	1893	Ne 314 "N-000169"
1889	1894	Po -249 -1003
1890	1895	$EndPAD
1891	1896	$PAD
...	...
1899	1904	Sh "6" R 197 355 0 0 900
1900	1905	Dr 0 0 0
1901	1906	At SMD N 00888000
1902		Ne 311 "N-000166"
	1907	Ne 313 "N-000168"
1903	1908	Po 249 -1003
1904	1909	$EndPAD
1905	1910	$PAD
...	...
1934	1939	Sh "1" R 157 236 0 0 0
1935	1940	Dr 0 0 0
1936	1941	At SMD N 00440001
1937		Ne 326 "N-000181"
	1942	Ne 327 "N-000182"
1938	1943	Po -176 0
1939	1944	$EndPAD
1940	1945	$PAD
...	...
1997	2002	Sh "2" R 157 236 0 0 900
1998	2003	Dr 0 0 0
1999	2004	At SMD N 00440001
2000		Ne 310 "N-000165"
	2005	Ne 312 "N-000167"
2001	2006	Po 176 0
2002	2007	$EndPAD
2003	2008	$EndMODULE 0402
...	...
2018	2023	Sh "1" R 157 236 0 0 1800
2019	2024	Dr 0 0 0
2020	2025	At SMD N 00440001
2021		Ne 326 "N-000181"
	2026	Ne 327 "N-000182"
2022	2027	Po -176 0
2023	2028	$EndPAD
2024	2029	$PAD
...	...
2046	2051	Sh "1" R 355 984 0 0 900
2047	2052	Dr 0 0 0
2048	2053	At SMD N 00888000
2049		Ne 326 "N-000181"
	2054	Ne 327 "N-000182"
2050	2055	Po -570 0
2051	2056	$EndPAD
2052	2057	$PAD
2053	2058	Sh "2" R 355 984 0 0 900
2054	2059	Dr 0 0 0
2055	2060	At SMD N 00888000
2056		Ne 311 "N-000166"
	2061	Ne 313 "N-000168"
2057	2062	Po 570 0
2058	2063	$EndPAD
2059	2064	$EndMODULE 1210
...	...
2074	2079	Sh "1" R 355 984 0 0 900
2075	2080	Dr 0 0 0
2076	2081	At SMD N 00888000
2077		Ne 326 "N-000181"
	2082	Ne 327 "N-000182"
2078	2083	Po -570 0
2079	2084	$EndPAD
2080	2085	$PAD
...	...
2127	2132	Sh "A4" O 157 157 0 0 0
2128	2133	Dr 0 0 0
2129	2134	At SMD N 00888000
2130		Ne 8 "/ether/ETH_CLK"
	2135	Ne 54 "/fpga1/ETH_CLK"
2131	2136	Po -2952 -4133
2132	2137	$EndPAD
2133	2138	$PAD
2134	2139	Sh "A5" O 157 157 0 0 0
2135	2140	Dr 0 0 0
2136	2141	At SMD N 00888000
2137		Ne 63 "/fpga1/ETH_RXD1"
	2142	Ne 60 "/fpga1/ETH_RXD1"
2138	2143	Po -2558 -4133
2139	2144	$EndPAD
2140	2145	$PAD
2141	2146	Sh "A6" O 158 157 0 0 0
2142	2147	Dr 0 0 0
2143	2148	At SMD N 00888000
2144		Ne 18 "/ether/ETH_RXDV"
	2149	Ne 14 "/ether/ETH_RXDV"
2145	2150	Po -2165 -4133
2146	2151	$EndPAD
2147	2152	$PAD
2148	2153	Sh "A7" O 158 157 0 0 0
2149	2154	Dr 0 0 0
2150	2155	At SMD N 00888000
2151		Ne 17 "/ether/ETH_RXC"
	2156	Ne 58 "/fpga1/ETH_RXC"
2152	2157	Po -1771 -4133
2153	2158	$EndPAD
2154	2159	$PAD
2155	2160	Sh "A8" O 157 157 0 0 0
2156	2161	Dr 0 0 0
2157	2162	At SMD N 00888000
2158		Ne 20 "/ether/ETH_TXD3"
	2163	Ne 66 "/fpga1/ETH_TXD3"
2159	2164	Po -1377 -4133
2160	2165	$EndPAD
2161	2166	$PAD
2162	2167	Sh "A9" O 157 157 0 0 0
2163	2168	Dr 0 0 0
2164	2169	At SMD N 00888000
2165		Ne 9 "/ether/ETH_COL"
	2170	Ne 8 "/ether/ETH_COL"
2166	2171	Po -983 -4133
2167	2172	$EndPAD
2168	2173	$PAD
2169	2174	Sh "A10" O 158 157 0 0 0
2170	2175	Dr 0 0 0
2171	2176	At SMD N 00888000
2172		Ne 11 "/ether/ETH_INT"
	2177	Ne 9 "/ether/ETH_INT"
2173	2178	Po -590 -4133
2174	2179	$EndPAD
2175	2180	$PAD
2176	2181	Sh "A11" O 157 157 0 0 0
2177	2182	Dr 0 0 0
2178	2183	At SMD N 00888000
2179		Ne 98 "/fpga1/NF_D6"
	2184	Ne 100 "/fpga1/NF_D6"
2180	2185	Po -196 -4133
2181	2186	$EndPAD
2182	2187	$PAD
2183	2188	Sh "A12" O 157 157 0 0 0
2184	2189	Dr 0 0 0
2185	2190	At SMD N 00888000
2186		Ne 97 "/fpga1/NF_D4"
	2191	Ne 98 "/fpga1/NF_D4"
2187	2192	Po 196 -4133
2188	2193	$EndPAD
2189	2194	$PAD
2190	2195	Sh "A13" O 158 157 0 0 0
2191	2196	Dr 0 0 0
2192	2197	At SMD N 00888000
2193		Ne 96 "/fpga1/NF_D2"
	2198	Ne 48 "/flash/NF_D2"
2194	2199	Po 590 -4133
2195	2200	$EndPAD
2196	2201	$PAD
2197	2202	Sh "A14" O 157 157 0 0 0
2198	2203	Dr 0 0 0
2199	2204	At SMD N 00888000
2200		Ne 51 "/flash/NF_ALE"
	2205	Ne 92 "/fpga1/NF_ALE"
2201	2206	Po 983 -4133
2202	2207	$EndPAD
2203	2208	$PAD
2204	2209	Sh "A15" O 157 157 0 0 0
2205	2210	Dr 0 0 0
2206	2211	At SMD N 00888000
2207		Ne 99 "/fpga1/NF_RNB"
	2212	Ne 49 "/flash/NF_RNB"
2208	2213	Po 1377 -4133
2209	2214	$EndPAD
2210	2215	$PAD
2211	2216	Sh "A16" O 158 157 0 0 0
2212	2217	Dr 0 0 0
2213	2218	At SMD N 00888000
2214		Ne 60 "/flash/SD_DAT2"
	2219	Ne 111 "/fpga1/SD_DAT2"
2215	2220	Po 1771 -4133
2216	2221	$EndPAD
2217	2222	$PAD
2218	2223	Sh "A17" O 158 157 0 0 0
2219	2224	Dr 0 0 0
2220	2225	At SMD N 00888000
2221		Ne 107 "/fpga1/SD_CLK"
	2226	Ne 51 "/flash/SD_CLK"
2222	2227	Po 2165 -4133
2223	2228	$EndPAD
2224	2229	$PAD
2225	2230	Sh "A18" O 157 157 0 0 0
2226	2231	Dr 0 0 0
2227	2232	At SMD N 00888000
2228		Ne 109 "/fpga1/SD_DAT0"
	2233	Ne 110 "/fpga1/SD_DAT0"
2229	2234	Po 2558 -4133
2230	2235	$EndPAD
2231	2236	$PAD
...	...
2239	2244	Sh "A20" O 158 157 0 0 0
2240	2245	Dr 0 0 0
2241	2246	At SMD N 00888000
2242		Ne 243 "/fpga2/USBD_RCV"
	2247	Ne 235 "/fpga2/USBD_RCV"
2243	2248	Po 3346 -4133
2244	2249	$EndPAD
2245	2250	$PAD
2246	2251	Sh "A21" O 157 157 0 0 0
2247	2252	Dr 0 0 0
2248	2253	At SMD N 00888000
2249		Ne 288 "/usb/USBD_OE_N"
	2254	Ne 234 "/fpga2/USBD_OE_N"
2250	2255	Po 3739 -4133
2251	2256	$EndPAD
2252	2257	$PAD
...	...
2295	2300	Sh "B6" O 158 157 0 0 0
2296	2301	Dr 0 0 0
2297	2302	At SMD N 00888000
2298		Ne 62 "/fpga1/ETH_RXD0"
	2303	Ne 59 "/fpga1/ETH_RXD0"
2299	2304	Po -2165 -3739
2300	2305	$EndPAD
2301	2306	$PAD
...	...
2309	2314	Sh "B8" O 157 157 0 0 0
2310	2315	Dr 0 0 0
2311	2316	At SMD N 00888000
2312		Ne 66 "/fpga1/ETH_RXER"
	2317	Ne 15 "/ether/ETH_RXER"
2313	2318	Po -1377 -3739
2314	2319	$EndPAD
2315	2320	$PAD
...	...
2323	2328	Sh "B10" O 158 157 0 0 0
2324	2329	Dr 0 0 0
2325	2330	At SMD N 00888000
2326		Ne 10 "/ether/ETH_CRS"
	2331	Ne 55 "/fpga1/ETH_CRS"
2327	2332	Po -590 -3739
2328	2333	$EndPAD
2329	2334	$PAD
...	...
2337	2342	Sh "B12" O 157 157 0 0 0
2338	2343	Dr 0 0 0
2339	2344	At SMD N 00888000
2340		Ne 56 "/flash/NF_D3"
	2345	Ne 97 "/fpga1/NF_D3"
2341	2346	Po 196 -3739
2342	2347	$EndPAD
2343	2348	$PAD
...	...
2351	2356	Sh "B14" O 157 157 0 0 0
2352	2357	Dr 0 0 0
2353	2358	At SMD N 00888000
2354		Ne 52 "/flash/NF_CLE"
	2359	Ne 93 "/fpga1/NF_CLE"
2355	2360	Po 983 -3739
2356	2361	$EndPAD
2357	2362	$PAD
...	...
2365	2370	Sh "B16" O 158 157 0 0 0
2366	2371	Dr 0 0 0
2367	2372	At SMD N 00888000
2368		Ne 111 "/fpga1/SD_DAT3"
	2373	Ne 53 "/flash/SD_DAT3"
2369	2374	Po 1771 -3739
2370	2375	$EndPAD
2371	2376	$PAD
...	...
2379	2384	Sh "B18" O 157 157 0 0 0
2380	2385	Dr 0 0 0
2381	2386	At SMD N 00888000
2382		Ne 110 "/fpga1/SD_DAT1"
	2387	Ne 52 "/flash/SD_DAT1"
2383	2388	Po 2558 -3739
2384	2389	$EndPAD
2385	2390	$PAD
...	...
2393	2398	Sh "B20" O 158 157 0 0 0
2394	2399	Dr 0 0 0
2395	2400	At SMD N 00888000
2396		Ne 289 "/usb/USBD_SPD"
	2401	Ne 288 "/usb/USBD_SPD"
2397	2402	Po 3346 -3739
2398	2403	$EndPAD
2399	2404	$PAD
2400	2405	Sh "B21" O 157 157 0 0 0
2401	2406	Dr 0 0 0
2402	2407	At SMD N 00888000
2403		Ne 245 "/fpga2/USBD_VP"
	2408	Ne 236 "/fpga2/USBD_VP"
2404	2409	Po 3739 -3739
2405	2410	$EndPAD
2406	2411	$PAD
2407	2412	Sh "B22" O 157 157 0 0 0
2408	2413	Dr 0 0 0
2409	2414	At SMD N 00888000
2410		Ne 244 "/fpga2/USBD_VM"
	2415	Ne 289 "/usb/USBD_VM"
2411	2416	Po 4133 -3739
2412	2417	$EndPAD
2413	2418	$PAD
2414	2419	Sh "C1" O 157 158 0 0 0
2415	2420	Dr 0 0 0
2416	2421	At SMD N 00888000
2417		Ne 165 "/fpga2/R_M0_A11"
	2422	Ne 156 "/fpga2/R_M0_A11"
2418	2423	Po -4133 -3346
2419	2424	$EndPAD
2420	2425	$PAD
...	...
2442	2447	Sh "C5" O 157 158 0 0 0
2443	2448	Dr 0 0 0
2444	2449	At SMD N 00888000
2445		Ne 65 "/fpga1/ETH_RXD3"
	2450	Ne 62 "/fpga1/ETH_RXD3"
2446	2451	Po -2558 -3346
2447	2452	$EndPAD
2448	2453	$PAD
2449	2454	Sh "C6" O 158 158 0 0 0
2450	2455	Dr 0 0 0
2451	2456	At SMD N 00888000
2452		Ne 64 "/fpga1/ETH_RXD2"
	2457	Ne 61 "/fpga1/ETH_RXD2"
2453	2458	Po -2165 -3346
2454	2459	$EndPAD
2455	2460	$PAD
2456	2461	Sh "C7" O 158 158 0 0 0
2457	2462	Dr 0 0 0
2458	2463	At SMD N 00888000
2459		Ne 61 "/fpga1/ETH_RESET_N"
	2464	Ne 57 "/fpga1/ETH_RESET_N"
2460	2465	Po -1771 -3346
2461	2466	$EndPAD
2462	2467	$PAD
2463	2468	Sh "C8" O 157 158 0 0 0
2464	2469	Dr 0 0 0
2465	2470	At SMD N 00888000
2466		Ne 67 "/fpga1/ETH_TXC"
	2471	Ne 63 "/fpga1/ETH_TXC"
2467	2472	Po -1377 -3346
2468	2473	$EndPAD
2469	2474	$PAD
2470	2475	Sh "C9" O 157 158 0 0 0
2471	2476	Dr 0 0 0
2472	2477	At SMD N 00888000
2473		Ne 68 "/fpga1/ETH_TXD1"
	2478	Ne 65 "/fpga1/ETH_TXD1"
2474	2479	Po -983 -3346
2475	2480	$EndPAD
2476	2481	$PAD
2477	2482	Sh "C10" O 158 158 0 0 0
2478	2483	Dr 0 0 0
2479	2484	At SMD N 00888000
2480		Ne 69 "/fpga1/ETH_TXD2"
	2485	Ne 16 "/ether/ETH_TXD2"
2481	2486	Po -590 -3346
2482	2487	$EndPAD
2483	2488	$PAD
2484	2489	Sh "C11" O 157 158 0 0 0
2485	2490	Dr 0 0 0
2486	2491	At SMD N 00888000
2487		Ne 57 "/flash/NF_D5"
	2492	Ne 99 "/fpga1/NF_D5"
2488	2493	Po -196 -3346
2489	2494	$EndPAD
2490	2495	$PAD
2491	2496	Sh "C12" O 157 158 0 0 0
2492	2497	Dr 0 0 0
2493	2498	At SMD N 00888000
2494		Ne 54 "/flash/NF_D0"
	2499	Ne 95 "/fpga1/NF_D0"
2495	2500	Po 196 -3346
2496	2501	$EndPAD
2497	2502	$PAD
...	...
2505	2510	Sh "C14" O 157 158 0 0 0
2506	2511	Dr 0 0 0
2507	2512	At SMD N 00888000
2508		Ne 100 "/fpga1/NF_WE_N"
	2513	Ne 50 "/flash/NF_WE_N"
2509	2514	Po 983 -3346
2510	2515	$EndPAD
2511	2516	$PAD
2512	2517	Sh "C15" O 157 158 0 0 0
2513	2518	Dr 0 0 0
2514	2519	At SMD N 00888000
2515		Ne 59 "/flash/NF_RE_N"
	2520	Ne 102 "/fpga1/NF_RE_N"
2516	2521	Po 1377 -3346
2517	2522	$EndPAD
2518	2523	$PAD
2519	2524	Sh "C16" O 158 158 0 0 0
2520	2525	Dr 0 0 0
2521	2526	At SMD N 00888000
2522		Ne 108 "/fpga1/SD_CMD"
	2527	Ne 109 "/fpga1/SD_CMD"
2523	2528	Po 1771 -3346
2524	2529	$EndPAD
2525	2530	$PAD
...	...
2547	2552	Sh "C20" O 158 158 0 0 0
2548	2553	Dr 0 0 0
2549	2554	At SMD N 00888000
2550		Ne 212 "/fpga2/R_M1_A8"
	2555	Ne 203 "/fpga2/R_M1_A8"
2551	2556	Po 3346 -3346
2552	2557	$EndPAD
2553	2558	$PAD
...	...
2561	2566	Sh "C22" O 157 158 0 0 0
2562	2567	Dr 0 0 0
2563	2568	At SMD N 00888000
2564		Ne 213 "/fpga2/R_M1_A9"
	2569	Ne 204 "/fpga2/R_M1_A9"
2565	2570	Po 4133 -3346
2566	2571	$EndPAD
2567	2572	$PAD
2568	2573	Sh "D1" O 157 157 0 0 0
2569	2574	Dr 0 0 0
2570	2575	At SMD N 00888000
2571		Ne 166 "/fpga2/R_M0_A12"
	2576	Ne 157 "/fpga2/R_M0_A12"
2572	2577	Po -4133 -2952
2573	2578	$EndPAD
2574	2579	$PAD
2575	2580	Sh "D2" O 157 157 0 0 0
2576	2581	Dr 0 0 0
2577	2582	At SMD N 00888000
2578		Ne 178 "/fpga2/R_M0_CKE"
	2583	Ne 169 "/fpga2/R_M0_CKE"
2579	2584	Po -3739 -2952
2580	2585	$EndPAD
2581	2586	$PAD
...	...
2603	2608	Sh "D6" O 158 157 0 0 0
2604	2609	Dr 0 0 0
2605	2610	At SMD N 00888000
2606		Ne 15 "/ether/ETH_MDIO"
	2611	Ne 12 "/ether/ETH_MDIO"
2607	2612	Po -2165 -2952
2608	2613	$EndPAD
2609	2614	$PAD
2610	2615	Sh "D7" O 158 157 0 0 0
2611	2616	Dr 0 0 0
2612	2617	At SMD N 00888000
2613		Ne 14 "/ether/ETH_MDC"
	2618	Ne 56 "/fpga1/ETH_MDC"
2614	2619	Po -1771 -2952
2615	2620	$EndPAD
2616	2621	$PAD
2617	2622	Sh "D8" O 157 157 0 0 0
2618	2623	Dr 0 0 0
2619	2624	At SMD N 00888000
2620		Ne 21 "/ether/ETH_TXER"
	2625	Ne 17 "/ether/ETH_TXER"
2621	2626	Po -1377 -2952
2622	2627	$EndPAD
2623	2628	$PAD
2624	2629	Sh "D9" O 157 157 0 0 0
2625	2630	Dr 0 0 0
2626	2631	At SMD N 00888000
2627		Ne 70 "/fpga1/ETH_TXEN"
	2632	Ne 67 "/fpga1/ETH_TXEN"
2628	2633	Po -983 -2952
2629	2634	$EndPAD
2630	2635	$PAD
2631	2636	Sh "D10" O 158 157 0 0 0
2632	2637	Dr 0 0 0
2633	2638	At SMD N 00888000
2634		Ne 19 "/ether/ETH_TXD0"
	2639	Ne 64 "/fpga1/ETH_TXD0"
2635	2640	Po -590 -2952
2636	2641	$EndPAD
2637	2642	$PAD
2638	2643	Sh "D11" O 157 157 0 0 0
2639	2644	Dr 0 0 0
2640	2645	At SMD N 00888000
2641		Ne 58 "/flash/NF_D7"
	2646	Ne 101 "/fpga1/NF_D7"
2642	2647	Po -196 -2952
2643	2648	$EndPAD
2644	2649	$PAD
...	...
2659	2664	Sh "D14" O 157 157 0 0 0
2660	2665	Dr 0 0 0
2661	2666	At SMD N 00888000
2662		Ne 55 "/flash/NF_D1"
	2667	Ne 96 "/fpga1/NF_D1"
2663	2668	Po 983 -2952
2664	2669	$EndPAD
2665	2670	$PAD
2666	2671	Sh "D15" O 157 157 0 0 0
2667	2672	Dr 0 0 0
2668	2673	At SMD N 00888000
2669		Ne 53 "/flash/NF_CS1_N"
	2674	Ne 94 "/fpga1/NF_CS1_N"
2670	2675	Po 1377 -2952
2671	2676	$EndPAD
2672	2677	$PAD
...	...
2694	2699	Sh "D19" O 157 157 0 0 0
2695	2700	Dr 0 0 0
2696	2701	At SMD N 00888000
2697		Ne 242 "/fpga2/USBA_VP"
	2702	Ne 233 "/fpga2/USBA_VP"
2698	2703	Po 2952 -2952
2699	2704	$EndPAD
2700	2705	$PAD
...	...
2708	2713	Sh "D21" O 157 157 0 0 0
2709	2714	Dr 0 0 0
2710	2715	At SMD N 00888000
2711		Ne 217 "/fpga2/R_M1_CKE"
	2716	Ne 208 "/fpga2/R_M1_CKE"
2712	2717	Po 3739 -2952
2713	2718	$EndPAD
2714	2719	$PAD
2715	2720	Sh "D22" O 157 157 0 0 0
2716	2721	Dr 0 0 0
2717	2722	At SMD N 00888000
2718		Ne 205 "/fpga2/R_M1_A12"
	2723	Ne 196 "/fpga2/R_M1_A12"
2719	2724	Po 4133 -2952
2720	2725	$EndPAD
2721	2726	$PAD
2722	2727	Sh "E1" O 157 157 0 0 0
2723	2728	Dr 0 0 0
2724	2729	At SMD N 00888000
2725		Ne 174 "/fpga2/R_M0_A9"
	2730	Ne 165 "/fpga2/R_M0_A9"
2726	2731	Po -4133 -2558
2727	2732	$EndPAD
2728	2733	$PAD
...	...
2736	2741	Sh "E3" O 158 157 0 0 0
2737	2742	Dr 0 0 0
2738	2743	At SMD N 00888000
2739		Ne 173 "/fpga2/R_M0_A8"
	2744	Ne 164 "/fpga2/R_M0_A8"
2740	2745	Po -3346 -2558
2741	2746	$EndPAD
2742	2747	$PAD
...	...
2855	2860	Sh "E20" O 158 157 0 0 0
2856	2861	Dr 0 0 0
2857	2862	At SMD N 00888000
2858		Ne 211 "/fpga2/R_M1_A7"
	2863	Ne 202 "/fpga2/R_M1_A7"
2859	2864	Po 3346 -2558
2860	2865	$EndPAD
2861	2866	$PAD
...	...
2869	2874	Sh "E22" O 157 157 0 0 0
2870	2875	Dr 0 0 0
2871	2876	At SMD N 00888000
2872		Ne 206 "/fpga2/R_M1_A2"
	2877	Ne 197 "/fpga2/R_M1_A2"
2873	2878	Po 4133 -2558
2874	2879	$EndPAD
2875	2880	$PAD
...	...
2883	2888	Sh "F2" O 157 158 0 0 0
2884	2889	Dr 0 0 0
2885	2890	At SMD N 00888000
2886		Ne 200 "/fpga2/R_M0_WE#"
	2891	Ne 191 "/fpga2/R_M0_WE#"
2887	2892	Po -3739 -2165
2888	2893	$EndPAD
2889	2894	$PAD
2890	2895	Sh "F3" O 158 158 0 0 0
2891	2896	Dr 0 0 0
2892	2897	At SMD N 00888000
2893		Ne 169 "/fpga2/R_M0_A4"
	2898	Ne 160 "/fpga2/R_M0_A4"
2894	2899	Po -3346 -2165
2895	2900	$EndPAD
2896	2901	$PAD
...	...
2988	2993	Sh "F17" O 158 158 0 0 0
2989	2994	Dr 0 0 0
2990	2995	At SMD N 00888000
2991		Ne 241 "/fpga2/USBA_RCV"
	2996	Ne 232 "/fpga2/USBA_RCV"
2992	2997	Po 2165 -2165
2993	2998	$EndPAD
2994	2999	$PAD
...	...
3002	3007	Sh "F19" O 157 158 0 0 0
3003	3008	Dr 0 0 0
3004	3009	At SMD N 00888000
3005		Ne 204 "/fpga2/R_M1_A11"
	3010	Ne 195 "/fpga2/R_M1_A11"
3006	3011	Po 2952 -2165
3007	3012	$EndPAD
3008	3013	$PAD
3009	3014	Sh "F20" O 158 158 0 0 0
3010	3015	Dr 0 0 0
3011	3016	At SMD N 00888000
3012		Ne 208 "/fpga2/R_M1_A4"
	3017	Ne 199 "/fpga2/R_M1_A4"
3013	3018	Po 3346 -2165
3014	3019	$EndPAD
3015	3020	$PAD
3016	3021	Sh "F21" O 157 158 0 0 0
3017	3022	Dr 0 0 0
3018	3023	At SMD N 00888000
3019		Ne 201 "/fpga2/R_M1_A0"
	3024	Ne 192 "/fpga2/R_M1_A0"
3020	3025	Po 3739 -2165
3021	3026	$EndPAD
3022	3027	$PAD
3023	3028	Sh "F22" O 157 158 0 0 0
3024	3029	Dr 0 0 0
3025	3030	At SMD N 00888000
3026		Ne 202 "/fpga2/R_M1_A1"
	3031	Ne 193 "/fpga2/R_M1_A1"
3027	3032	Po 4133 -2165
3028	3033	$EndPAD
3029	3034	$PAD
3030	3035	Sh "G1" O 157 158 0 0 0
3031	3036	Dr 0 0 0
3032	3037	At SMD N 00888000
3033		Ne 176 "/fpga2/R_M0_BA1"
	3038	Ne 167 "/fpga2/R_M0_BA1"
3034	3039	Po -4133 -1771
3035	3040	$EndPAD
3036	3041	$PAD
...	...
3044	3049	Sh "G3" O 158 158 0 0 0
3045	3050	Dr 0 0 0
3046	3051	At SMD N 00888000
3047		Ne 175 "/fpga2/R_M0_BA0"
	3052	Ne 166 "/fpga2/R_M0_BA0"
3048	3053	Po -3346 -1771
3049	3054	$EndPAD
3050	3055	$PAD
3051	3056	Sh "G4" O 157 158 0 0 0
3052	3057	Dr 0 0 0
3053	3058	At SMD N 00888000
3054		Ne 164 "/fpga2/R_M0_A10"
	3059	Ne 155 "/fpga2/R_M0_A10"
3055	3060	Po -2952 -1771
3056	3061	$EndPAD
3057	3062	$PAD
...	...
3156	3161	Sh "G19" O 157 158 0 0 0
3157	3162	Dr 0 0 0
3158	3163	At SMD N 00888000
3159		Ne 203 "/fpga2/R_M1_A10"
	3164	Ne 194 "/fpga2/R_M1_A10"
3160	3165	Po 2952 -1771
3161	3166	$EndPAD
3162	3167	$PAD
3163	3168	Sh "G20" O 158 158 0 0 0
3164	3169	Dr 0 0 0
3165	3170	At SMD N 00888000
3166		Ne 207 "/fpga2/R_M1_A3"
	3171	Ne 198 "/fpga2/R_M1_A3"
3167	3172	Po 3346 -1771
3168	3173	$EndPAD
3169	3174	$PAD
...	...
3184	3189	Sh "H1" O 157 157 0 0 0
3185	3190	Dr 0 0 0
3186	3191	At SMD N 00888000
3187		Ne 163 "/fpga2/R_M0_A1"
	3192	Ne 154 "/fpga2/R_M0_A1"
3188	3193	Po -4133 -1377
3189	3194	$EndPAD
3190	3195	$PAD
3191	3196	Sh "H2" O 157 157 0 0 0
3192	3197	Dr 0 0 0
3193	3198	At SMD N 00888000
3194		Ne 162 "/fpga2/R_M0_A0"
	3199	Ne 153 "/fpga2/R_M0_A0"
3195	3200	Po -3739 -1377
3196	3201	$EndPAD
3197	3202	$PAD
3198	3203	Sh "H3" O 158 157 0 0 0
3199	3204	Dr 0 0 0
3200	3205	At SMD N 00888000
3201		Ne 252 "/sdram/M0_CLK#"
	3206	Ne 247 "/sdram/M0_CLK#"
3202	3207	Po -3346 -1377
3203	3208	$EndPAD
3204	3209	$PAD
3205	3210	Sh "H4" O 157 157 0 0 0
3206	3211	Dr 0 0 0
3207	3212	At SMD N 00888000
3208		Ne 123 "/fpga2/M0_CLK"
	3213	Ne 246 "/sdram/M0_CLK"
3209	3214	Po -2952 -1377
3210	3215	$EndPAD
3211	3216	$PAD
3212	3217	Sh "H5" O 157 157 0 0 0
3213	3218	Dr 0 0 0
3214	3219	At SMD N 00888000
3215		Ne 167 "/fpga2/R_M0_A2"
	3220	Ne 158 "/fpga2/R_M0_A2"
3216	3221	Po -2558 -1377
3217	3222	$EndPAD
3218	3223	$PAD
3219	3224	Sh "H6" O 158 157 0 0 0
3220	3225	Dr 0 0 0
3221	3226	At SMD N 00888000
3222		Ne 172 "/fpga2/R_M0_A7"
	3227	Ne 163 "/fpga2/R_M0_A7"
3223	3228	Po -2165 -1377
3224	3229	$EndPAD
3225	3230	$PAD
...	...
3289	3294	Sh "H16" O 158 157 0 0 0
3290	3295	Dr 0 0 0
3291	3296	At SMD N 00888000
3292		Ne 218 "/fpga2/R_M1_CS#"
	3297	Ne 209 "/fpga2/R_M1_CS#"
3293	3298	Po 1771 -1377
3294	3299	$EndPAD
3295	3300	$PAD
...	...
3310	3315	Sh "H19" O 157 157 0 0 0
3311	3316	Dr 0 0 0
3312	3317	At SMD N 00888000
3313		Ne 240 "/fpga2/R_M1_WE#"
	3318	Ne 231 "/fpga2/R_M1_WE#"
3314	3319	Po 2952 -1377
3315	3320	$EndPAD
3316	3321	$PAD
3317	3322	Sh "H20" O 158 157 0 0 0
3318	3323	Dr 0 0 0
3319	3324	At SMD N 00888000
3320		Ne 146 "/fpga2/M1_CLK"
	3325	Ne 136 "/fpga2/M1_CLK"
3321	3326	Po 3346 -1377
3322	3327	$EndPAD
3323	3328	$PAD
3324	3329	Sh "H21" O 157 157 0 0 0
3325	3330	Dr 0 0 0
3326	3331	At SMD N 00888000
3327		Ne 237 "/fpga2/R_M1_RAS#"
	3332	Ne 228 "/fpga2/R_M1_RAS#"
3328	3333	Po 3739 -1377
3329	3334	$EndPAD
3330	3335	$PAD
3331	3336	Sh "H22" O 157 157 0 0 0
3332	3337	Dr 0 0 0
3333	3338	At SMD N 00888000
3334		Ne 216 "/fpga2/R_M1_CAS#"
	3339	Ne 207 "/fpga2/R_M1_CAS#"
3335	3340	Po 4133 -1377
3336	3341	$EndPAD
3337	3342	$PAD
3338	3343	Sh "J1" O 157 157 0 0 0
3339	3344	Dr 0 0 0
3340	3345	At SMD N 00888000
3341		Ne 190 "/fpga2/R_M0_DQ5"
	3346	Ne 181 "/fpga2/R_M0_DQ5"
3342	3347	Po -4133 -983
3343	3348	$EndPAD
3344	3349	$PAD
...	...
3352	3357	Sh "J3" O 158 157 0 0 0
3353	3358	Dr 0 0 0
3354	3359	At SMD N 00888000
3355		Ne 189 "/fpga2/R_M0_DQ4"
	3360	Ne 180 "/fpga2/R_M0_DQ4"
3356	3361	Po -3346 -983
3357	3362	$EndPAD
3358	3363	$PAD
3359	3364	Sh "J4" O 157 157 0 0 0
3360	3365	Dr 0 0 0
3361	3366	At SMD N 00888000
3362		Ne 171 "/fpga2/R_M0_A6"
	3367	Ne 162 "/fpga2/R_M0_A6"
3363	3368	Po -2952 -983
3364	3369	$EndPAD
3365	3370	$PAD
...	...
3450	3455	Sh "J17" O 158 157 0 0 0
3451	3456	Dr 0 0 0
3452	3457	At SMD N 00888000
3453		Ne 214 "/fpga2/R_M1_BA0"
	3458	Ne 205 "/fpga2/R_M1_BA0"
3454	3459	Po 2165 -983
3455	3460	$EndPAD
3456	3461	$PAD
...	...
3464	3469	Sh "J19" O 157 157 0 0 0
3465	3470	Dr 0 0 0
3466	3471	At SMD N 00888000
3467		Ne 147 "/fpga2/M1_CLK#"
	3472	Ne 137 "/fpga2/M1_CLK#"
3468	3473	Po 2952 -983
3469	3474	$EndPAD
3470	3475	$PAD
3471	3476	Sh "J20" O 158 157 0 0 0
3472	3477	Dr 0 0 0
3473	3478	At SMD N 00888000
3474		Ne 229 "/fpga2/R_M1_DQ4"
	3479	Ne 220 "/fpga2/R_M1_DQ4"
3475	3480	Po 3346 -983
3476	3481	$EndPAD
3477	3482	$PAD
...	...
3485	3490	Sh "J22" O 157 157 0 0 0
3486	3491	Dr 0 0 0
3487	3492	At SMD N 00888000
3488		Ne 230 "/fpga2/R_M1_DQ5"
	3493	Ne 221 "/fpga2/R_M1_DQ5"
3489	3494	Po 4133 -983
3490	3495	$EndPAD
3491	3496	$PAD
3492	3497	Sh "K1" O 157 158 0 0 0
3493	3498	Dr 0 0 0
3494	3499	At SMD N 00888000
3495		Ne 192 "/fpga2/R_M0_DQ7"
	3500	Ne 183 "/fpga2/R_M0_DQ7"
3496	3501	Po -4133 -590
3497	3502	$EndPAD
3498	3503	$PAD
3499	3504	Sh "K2" O 157 158 0 0 0
3500	3505	Dr 0 0 0
3501	3506	At SMD N 00888000
3502		Ne 191 "/fpga2/R_M0_DQ6"
	3507	Ne 182 "/fpga2/R_M0_DQ6"
3503	3508	Po -3739 -590
3504	3509	$EndPAD
3505	3510	$PAD
3506	3511	Sh "K3" O 158 158 0 0 0
3507	3512	Dr 0 0 0
3508	3513	At SMD N 00888000
3509		Ne 170 "/fpga2/R_M0_A5"
	3514	Ne 161 "/fpga2/R_M0_A5"
3510	3515	Po -3346 -590
3511	3516	$EndPAD
3512	3517	$PAD
3513	3518	Sh "K4" O 157 158 0 0 0
3514	3519	Dr 0 0 0
3515	3520	At SMD N 00888000
3516		Ne 177 "/fpga2/R_M0_CAS#"
	3521	Ne 168 "/fpga2/R_M0_CAS#"
3517	3522	Po -2952 -590
3518	3523	$EndPAD
3519	3524	$PAD
3520	3525	Sh "K5" O 157 158 0 0 0
3521	3526	Dr 0 0 0
3522	3527	At SMD N 00888000
3523		Ne 197 "/fpga2/R_M0_RAS#"
	3528	Ne 188 "/fpga2/R_M0_RAS#"
3524	3529	Po -2558 -590
3525	3530	$EndPAD
3526	3531	$PAD
3527	3532	Sh "K6" O 158 158 0 0 0
3528	3533	Dr 0 0 0
3529	3534	At SMD N 00888000
3530		Ne 168 "/fpga2/R_M0_A3"
	3535	Ne 159 "/fpga2/R_M0_A3"
3531	3536	Po -2165 -590
3532	3537	$EndPAD
3533	3538	$PAD
...	...
3604	3609	Sh "K17" O 158 158 0 0 0
3605	3610	Dr 0 0 0
3606	3611	At SMD N 00888000
3607		Ne 215 "/fpga2/R_M1_BA1"
	3612	Ne 206 "/fpga2/R_M1_BA1"
3608	3613	Po 2165 -590
3609	3614	$EndPAD
3610	3615	$PAD
...	...
3618	3623	Sh "K19" O 157 158 0 0 0
3619	3624	Dr 0 0 0
3620	3625	At SMD N 00888000
3621		Ne 210 "/fpga2/R_M1_A6"
	3626	Ne 201 "/fpga2/R_M1_A6"
3622	3627	Po 2952 -590
3623	3628	$EndPAD
3624	3629	$PAD
3625	3630	Sh "K20" O 158 158 0 0 0
3626	3631	Dr 0 0 0
3627	3632	At SMD N 00888000
3628		Ne 209 "/fpga2/R_M1_A5"
	3633	Ne 200 "/fpga2/R_M1_A5"
3629	3634	Po 3346 -590
3630	3635	$EndPAD
3631	3636	$PAD
3632	3637	Sh "K21" O 157 158 0 0 0
3633	3638	Dr 0 0 0
3634	3639	At SMD N 00888000
3635		Ne 231 "/fpga2/R_M1_DQ6"
	3640	Ne 222 "/fpga2/R_M1_DQ6"
3636	3641	Po 3739 -590
3637	3642	$EndPAD
3638	3643	$PAD
3639	3644	Sh "K22" O 157 158 0 0 0
3640	3645	Dr 0 0 0
3641	3646	At SMD N 00888000
3642		Ne 232 "/fpga2/R_M1_DQ7"
	3647	Ne 223 "/fpga2/R_M1_DQ7"
3643	3648	Po 4133 -590
3644	3649	$EndPAD
3645	3650	$PAD
...	...
3660	3665	Sh "L3" O 158 157 0 0 0
3661	3666	Dr 0 0 0
3662	3667	At SMD N 00888000
3663		Ne 196 "/fpga2/R_M0_LDQS"
	3668	Ne 187 "/fpga2/R_M0_LDQS"
3664	3669	Po -3346 -196
3665	3670	$EndPAD
3666	3671	$PAD
3667	3672	Sh "L4" O 157 157 0 0 0
3668	3673	Dr 0 0 0
3669	3674	At SMD N 00888000
3670		Ne 195 "/fpga2/R_M0_LDM"
	3675	Ne 186 "/fpga2/R_M0_LDM"
3671	3676	Po -2952 -196
3672	3677	$EndPAD
3673	3678	$PAD
...	...
3772	3777	Sh "L19" O 157 157 0 0 0
3773	3778	Dr 0 0 0
3774	3779	At SMD N 00888000
3775		Ne 235 "/fpga2/R_M1_LDM"
	3780	Ne 226 "/fpga2/R_M1_LDM"
3776	3781	Po 2952 -196
3777	3782	$EndPAD
3778	3783	$PAD
3779	3784	Sh "L20" O 158 157 0 0 0
3780	3785	Dr 0 0 0
3781	3786	At SMD N 00888000
3782		Ne 236 "/fpga2/R_M1_LDQS"
	3787	Ne 227 "/fpga2/R_M1_LDQS"
3783	3788	Po 3346 -196
3784	3789	$EndPAD
3785	3790	$PAD
...	...
3800	3805	Sh "M1" O 157 157 0 0 0
3801	3806	Dr 0 0 0
3802	3807	At SMD N 00888000
3803		Ne 188 "/fpga2/R_M0_DQ3"
	3808	Ne 179 "/fpga2/R_M0_DQ3"
3804	3809	Po -4133 196
3805	3810	$EndPAD
3806	3811	$PAD
3807	3812	Sh "M2" O 157 157 0 0 0
3808	3813	Dr 0 0 0
3809	3814	At SMD N 00888000
3810		Ne 187 "/fpga2/R_M0_DQ2"
	3815	Ne 178 "/fpga2/R_M0_DQ2"
3811	3816	Po -3739 196
3812	3817	$EndPAD
3813	3818	$PAD
3814	3819	Sh "M3" O 158 157 0 0 0
3815	3820	Dr 0 0 0
3816	3821	At SMD N 00888000
3817		Ne 198 "/fpga2/R_M0_UDM"
	3822	Ne 189 "/fpga2/R_M0_UDM"
3818	3823	Po -3346 196
3819	3824	$EndPAD
3820	3825	$PAD
...	...
3933	3938	Sh "M20" O 158 157 0 0 0
3934	3939	Dr 0 0 0
3935	3940	At SMD N 00888000
3936		Ne 238 "/fpga2/R_M1_UDM"
	3941	Ne 229 "/fpga2/R_M1_UDM"
3937	3942	Po 3346 196
3938	3943	$EndPAD
3939	3944	$PAD
3940	3945	Sh "M21" O 157 157 0 0 0
3941	3946	Dr 0 0 0
3942	3947	At SMD N 00888000
3943		Ne 227 "/fpga2/R_M1_DQ2"
	3948	Ne 218 "/fpga2/R_M1_DQ2"
3944	3949	Po 3739 196
3945	3950	$EndPAD
3946	3951	$PAD
3947	3952	Sh "M22" O 157 157 0 0 0
3948	3953	Dr 0 0 0
3949	3954	At SMD N 00888000
3950		Ne 228 "/fpga2/R_M1_DQ3"
	3955	Ne 219 "/fpga2/R_M1_DQ3"
3951	3956	Po 4133 196
3952	3957	$EndPAD
3953	3958	$PAD
3954	3959	Sh "N1" O 157 158 0 0 0
3955	3960	Dr 0 0 0
3956	3961	At SMD N 00888000
3957		Ne 180 "/fpga2/R_M0_DQ1"
	3962	Ne 171 "/fpga2/R_M0_DQ1"
3958	3963	Po -4133 590
3959	3964	$EndPAD
3960	3965	$PAD
...	...
3968	3973	Sh "N3" O 158 158 0 0 0
3969	3974	Dr 0 0 0
3970	3975	At SMD N 00888000
3971		Ne 179 "/fpga2/R_M0_DQ0"
	3976	Ne 170 "/fpga2/R_M0_DQ0"
3972	3977	Po -3346 590
3973	3978	$EndPAD
3974	3979	$PAD
...	...
4087	4092	Sh "N20" O 158 158 0 0 0
4088	4093	Dr 0 0 0
4089	4094	At SMD N 00888000
4090		Ne 219 "/fpga2/R_M1_DQ0"
	4095	Ne 210 "/fpga2/R_M1_DQ0"
4091	4096	Po 3346 590
4092	4097	$EndPAD
4093	4098	$PAD
...	...
4101	4106	Sh "N22" O 157 158 0 0 0
4102	4107	Dr 0 0 0
4103	4108	At SMD N 00888000
4104		Ne 220 "/fpga2/R_M1_DQ1"
	4109	Ne 211 "/fpga2/R_M1_DQ1"
4105	4110	Po 4133 590
4106	4111	$EndPAD
4107	4112	$PAD
4108	4113	Sh "P1" O 157 157 0 0 0
4109	4114	Dr 0 0 0
4110	4115	At SMD N 00888000
4111		Ne 194 "/fpga2/R_M0_DQ9"
	4116	Ne 185 "/fpga2/R_M0_DQ9"
4112	4117	Po -4133 983
4113	4118	$EndPAD
4114	4119	$PAD
4115	4120	Sh "P2" O 157 157 0 0 0
4116	4121	Dr 0 0 0
4117	4122	At SMD N 00888000
4118		Ne 193 "/fpga2/R_M0_DQ8"
	4123	Ne 184 "/fpga2/R_M0_DQ8"
4119	4124	Po -3739 983
4120	4125	$EndPAD
4121	4126	$PAD
...	...
4248	4253	Sh "P21" O 157 157 0 0 0
4249	4254	Dr 0 0 0
4250	4255	At SMD N 00888000
4251		Ne 233 "/fpga2/R_M1_DQ8"
	4256	Ne 224 "/fpga2/R_M1_DQ8"
4252	4257	Po 3739 983
4253	4258	$EndPAD
4254	4259	$PAD
4255	4260	Sh "P22" O 157 157 0 0 0
4256	4261	Dr 0 0 0
4257	4262	At SMD N 00888000
4258		Ne 234 "/fpga2/R_M1_DQ9"
	4263	Ne 225 "/fpga2/R_M1_DQ9"
4259	4264	Po 4133 983
4260	4265	$EndPAD
4261	4266	$PAD
4262	4267	Sh "R1" O 157 157 0 0 0
4263	4268	Dr 0 0 0
4264	4269	At SMD N 00888000
4265		Ne 182 "/fpga2/R_M0_DQ11"
	4270	Ne 173 "/fpga2/R_M0_DQ11"
4266	4271	Po -4133 1377
4267	4272	$EndPAD
4268	4273	$PAD
...	...
4276	4281	Sh "R3" O 158 157 0 0 0
4277	4282	Dr 0 0 0
4278	4283	At SMD N 00888000
4279		Ne 181 "/fpga2/R_M0_DQ10"
	4284	Ne 172 "/fpga2/R_M0_DQ10"
4280	4285	Po -3346 1377
4281	4286	$EndPAD
4282	4287	$PAD
...	...
4318	4323	Sh "R9" O 157 157 0 0 0
4319	4324	Dr 0 0 0
4320	4325	At SMD N 00888000
4321		Ne 91 "/fpga1/FPGA_BANK0_IO_58"
	4326	Ne 87 "/fpga1/FPGA_BANK0_IO_58"
4322	4327	Po -983 1377
4323	4328	$EndPAD
4324	4329	$PAD
...	...
4367	4372	Sh "R16" O 158 157 0 0 0
4368	4373	Dr 0 0 0
4369	4374	At SMD N 00888000
4370		Ne 71 "/fpga1/FPGA_BANK0_IO_12"
	4375	Ne 24 "/expansion/FPGA_BANK0_IO_12"
4371	4376	Po 1771 1377
4372	4377	$EndPAD
4373	4378	$PAD
...	...
4395	4400	Sh "R20" O 158 157 0 0 0
4396	4401	Dr 0 0 0
4397	4402	At SMD N 00888000
4398		Ne 221 "/fpga2/R_M1_DQ10"
	4403	Ne 212 "/fpga2/R_M1_DQ10"
4399	4404	Po 3346 1377
4400	4405	$EndPAD
4401	4406	$PAD
...	...
4409	4414	Sh "R22" O 157 157 0 0 0
4410	4415	Dr 0 0 0
4411	4416	At SMD N 00888000
4412		Ne 222 "/fpga2/R_M1_DQ11"
	4417	Ne 213 "/fpga2/R_M1_DQ11"
4413	4418	Po 4133 1377
4414	4419	$EndPAD
4415	4420	$PAD
...	...
4423	4428	Sh "T2" O 157 158 0 0 0
4424	4429	Dr 0 0 0
4425	4430	At SMD N 00888000
4426		Ne 199 "/fpga2/R_M0_UDQS"
	4431	Ne 190 "/fpga2/R_M0_UDQS"
4427	4432	Po -3739 1771
4428	4433	$EndPAD
4429	4434	$PAD
...	...
4444	4449	Sh "T5" O 157 158 0 0 0
4445	4450	Dr 0 0 0
4446	4451	At SMD N 00888000
4447		Ne 102 "/fpga1/PROG_CSO"
	4452	Ne 104 "/fpga1/PROG_CSO"
4448	4453	Po -2558 1771
4449	4454	$EndPAD
4450	4455	$PAD
...	...
4458	4463	Sh "T7" O 158 158 0 0 0
4459	4464	Dr 0 0 0
4460	4465	At SMD N 00888000
4461		Ne 92 "/fpga1/FPGA_BANK0_IO_60"
	4466	Ne 89 "/fpga1/FPGA_BANK0_IO_60"
4462	4467	Po -1771 1771
4463	4468	$EndPAD
4464	4469	$PAD
4465	4470	Sh "T8" O 157 158 0 0 0
4466	4471	Dr 0 0 0
4467	4472	At SMD N 00888000
4468		Ne 88 "/fpga1/FPGA_BANK0_IO_53"
	4473	Ne 83 "/fpga1/FPGA_BANK0_IO_53"
4469	4474	Po -1377 1771
4470	4475	$EndPAD
4471	4476	$PAD
...	...
4493	4498	Sh "T12" O 157 158 0 0 0
4494	4499	Dr 0 0 0
4495	4500	At SMD N 00888000
4496		Ne 38 "/expansion/FPGA_BANK0_IO_34"
	4501	Ne 32 "/expansion/FPGA_BANK0_IO_34"
4497	4502	Po 196 1771
4498	4503	$EndPAD
4499	4504	$PAD
...	...
4507	4512	Sh "T14" O 157 158 0 0 0
4508	4513	Dr 0 0 0
4509	4514	At SMD N 00888000
4510		Ne 81 "/fpga1/FPGA_BANK0_IO_36"
	4515	Ne 33 "/expansion/FPGA_BANK0_IO_36"
4511	4516	Po 983 1771
4512	4517	$EndPAD
4513	4518	$PAD
4514	4519	Sh "T15" O 157 158 0 0 0
4515	4520	Dr 0 0 0
4516	4521	At SMD N 00888000
4517		Ne 49 "/expansion/FPGA_BANK0_IO_7"
	4522	Ne 46 "/expansion/FPGA_BANK0_IO_7"
4518	4523	Po 1377 1771
4519	4524	$EndPAD
4520	4525	$PAD
4521	4526	Sh "T16" O 158 158 0 0 0
4522	4527	Dr 0 0 0
4523	4528	At SMD N 00888000
4524		Ne 48 "/expansion/FPGA_BANK0_IO_6"
	4529	Ne 88 "/fpga1/FPGA_BANK0_IO_6"
4525	4530	Po 1771 1771
4526	4531	$EndPAD
4527	4532	$PAD
4528	4533	Sh "T17" O 158 158 0 0 0
4529	4534	Dr 0 0 0
4530	4535	At SMD N 00888000
4531		Ne 32 "/expansion/FPGA_BANK0_IO_2"
	4536	Ne 72 "/fpga1/FPGA_BANK0_IO_2"
4532	4537	Po 2165 1771
4533	4538	$EndPAD
4534	4539	$PAD
4535	4540	Sh "T18" O 157 158 0 0 0
4536	4541	Dr 0 0 0
4537	4542	At SMD N 00888000
4538		Ne 27 "/expansion/FPGA_BANK0_IO_1"
	4543	Ne 68 "/fpga1/FPGA_BANK0_IO_1"
4539	4544	Po 2558 1771
4540	4545	$EndPAD
4541	4546	$PAD
...	...
4556	4561	Sh "T21" O 157 158 0 0 0
4557	4562	Dr 0 0 0
4558	4563	At SMD N 00888000
4559		Ne 239 "/fpga2/R_M1_UDQS"
	4564	Ne 230 "/fpga2/R_M1_UDQS"
4560	4565	Po 3739 1771
4561	4566	$EndPAD
4562	4567	$PAD
...	...
4570	4575	Sh "U1" O 157 158 0 0 0
4571	4576	Dr 0 0 0
4572	4577	At SMD N 00888000
4573		Ne 184 "/fpga2/R_M0_DQ13"
	4578	Ne 175 "/fpga2/R_M0_DQ13"
4574	4579	Po -4133 2165
4575	4580	$EndPAD
4576	4581	$PAD
...	...
4584	4589	Sh "U3" O 158 158 0 0 0
4585	4590	Dr 0 0 0
4586	4591	At SMD N 00888000
4587		Ne 183 "/fpga2/R_M0_DQ12"
	4592	Ne 174 "/fpga2/R_M0_DQ12"
4588	4593	Po -3346 2165
4589	4594	$EndPAD
4590	4595	$PAD
...	...
4605	4610	Sh "U6" O 158 158 0 0 0
4606	4611	Dr 0 0 0
4607	4612	At SMD N 00888000
4608		Ne 93 "/fpga1/FPGA_BANK0_IO_62"
	4613	Ne 45 "/expansion/FPGA_BANK0_IO_62"
4609	4614	Po -2165 2165
4610	4615	$EndPAD
4611	4616	$PAD
...	...
4619	4624	Sh "U8" O 157 158 0 0 0
4620	4625	Dr 0 0 0
4621	4626	At SMD N 00888000
4622		Ne 47 "/expansion/FPGA_BANK0_IO_54"
	4627	Ne 84 "/fpga1/FPGA_BANK0_IO_54"
4623	4628	Po -1377 2165
4624	4629	$EndPAD
4625	4630	$PAD
4626	4631	Sh "U9" O 157 158 0 0 0
4627	4632	Dr 0 0 0
4628	4633	At SMD N 00888000
4629		Ne 86 "/fpga1/FPGA_BANK0_IO_51"
	4634	Ne 44 "/expansion/FPGA_BANK0_IO_51"
4630	4635	Po -983 2165
4631	4636	$EndPAD
4632	4637	$PAD
4633	4638	Sh "U10" O 158 158 0 0 0
4634	4639	Dr 0 0 0
4635	4640	At SMD N 00888000
4636		Ne 89 "/fpga1/FPGA_BANK0_IO_56"
	4641	Ne 85 "/fpga1/FPGA_BANK0_IO_56"
4637	4642	Po -590 2165
4638	4643	$EndPAD
4639	4644	$PAD
...	...
4654	4659	Sh "U13" O 158 158 0 0 0
4655	4660	Dr 0 0 0
4656	4661	At SMD N 00888000
4657		Ne 106 "/fpga1/PROG_MISO3"
	4662	Ne 108 "/fpga1/PROG_MISO3"
4658	4663	Po 590 2165
4659	4664	$EndPAD
4660	4665	$PAD
4661	4666	Sh "U14" O 157 158 0 0 0
4662	4667	Dr 0 0 0
4663	4668	At SMD N 00888000
4664		Ne 105 "/fpga1/PROG_MISO2"
	4669	Ne 107 "/fpga1/PROG_MISO2"
4665	4670	Po 983 2165
4666	4671	$EndPAD
4667	4672	$PAD
...	...
4675	4680	Sh "U16" O 158 158 0 0 0
4676	4681	Dr 0 0 0
4677	4682	At SMD N 00888000
4678		Ne 50 "/expansion/FPGA_BANK0_IO_9"
	4683	Ne 47 "/expansion/FPGA_BANK0_IO_9"
4679	4684	Po 1771 2165
4680	4685	$EndPAD
4681	4686	$PAD
4682	4687	Sh "U17" O 158 158 0 0 0
4683	4688	Dr 0 0 0
4684	4689	At SMD N 00888000
4685		Ne 95 "/fpga1/FPGA_BANK0_IO_8"
	4690	Ne 91 "/fpga1/FPGA_BANK0_IO_8"
4686	4691	Po 2165 2165
4687	4692	$EndPAD
4688	4693	$PAD
...	...
4703	4708	Sh "U20" O 158 158 0 0 0
4704	4709	Dr 0 0 0
4705	4710	At SMD N 00888000
4706		Ne 223 "/fpga2/R_M1_DQ12"
	4711	Ne 214 "/fpga2/R_M1_DQ12"
4707	4712	Po 3346 2165
4708	4713	$EndPAD
4709	4714	$PAD
...	...
4717	4722	Sh "U22" O 157 158 0 0 0
4718	4723	Dr 0 0 0
4719	4724	At SMD N 00888000
4720		Ne 224 "/fpga2/R_M1_DQ13"
	4725	Ne 215 "/fpga2/R_M1_DQ13"
4721	4726	Po 4133 2165
4722	4727	$EndPAD
4723	4728	$PAD
4724	4729	Sh "V1" O 157 157 0 0 0
4725	4730	Dr 0 0 0
4726	4731	At SMD N 00888000
4727		Ne 186 "/fpga2/R_M0_DQ15"
	4732	Ne 177 "/fpga2/R_M0_DQ15"
4728	4733	Po -4133 2558
4729	4734	$EndPAD
4730	4735	$PAD
4731	4736	Sh "V2" O 157 157 0 0 0
4732	4737	Dr 0 0 0
4733	4738	At SMD N 00888000
4734		Ne 185 "/fpga2/R_M0_DQ14"
	4739	Ne 176 "/fpga2/R_M0_DQ14"
4735	4740	Po -3739 2558
4736	4741	$EndPAD
4737	4742	$PAD
...	...
4752	4757	Sh "V5" O 157 157 0 0 0
4753	4758	Dr 0 0 0
4754	4759	At SMD N 00888000
4755		Ne 94 "/fpga1/FPGA_BANK0_IO_63"
	4760	Ne 90 "/fpga1/FPGA_BANK0_IO_63"
4756	4761	Po -2558 2558
4757	4762	$EndPAD
4758	4763	$PAD
...	...
4766	4771	Sh "V7" O 158 157 0 0 0
4767	4772	Dr 0 0 0
4768	4773	At SMD N 00888000
4769		Ne 85 "/fpga1/FPGA_BANK0_IO_49"
	4774	Ne 80 "/fpga1/FPGA_BANK0_IO_49"
4770	4775	Po -1771 2558
4771	4776	$EndPAD
4772	4777	$PAD
...	...
4780	4785	Sh "V9" O 157 157 0 0 0
4781	4786	Dr 0 0 0
4782	4787	At SMD N 00888000
4783		Ne 87 "/fpga1/FPGA_BANK0_IO_52"
	4788	Ne 82 "/fpga1/FPGA_BANK0_IO_52"
4784	4789	Po -983 2558
4785	4790	$EndPAD
4786	4791	$PAD
...	...
4794	4799	Sh "V11" O 157 157 0 0 0
4795	4800	Dr 0 0 0
4796	4801	At SMD N 00888000
4797		Ne 42 "/expansion/FPGA_BANK0_IO_43"
	4802	Ne 37 "/expansion/FPGA_BANK0_IO_43"
4798	4803	Po -196 2558
4799	4804	$EndPAD
4800	4805	$PAD
...	...
4822	4827	Sh "V15" O 157 157 0 0 0
4823	4828	Dr 0 0 0
4824	4829	At SMD N 00888000
4825		Ne 31 "/expansion/FPGA_BANK0_IO_17"
	4830	Ne 70 "/fpga1/FPGA_BANK0_IO_17"
4826	4831	Po 1377 2558
4827	4832	$EndPAD
4828	4833	$PAD
...	...
4836	4841	Sh "V17" O 158 157 0 0 0
4837	4842	Dr 0 0 0
4838	4843	At SMD N 00888000
4839		Ne 72 "/fpga1/FPGA_BANK0_IO_14"
	4844	Ne 25 "/expansion/FPGA_BANK0_IO_14"
4840	4845	Po 2165 2558
4841	4846	$EndPAD
4842	4847	$PAD
4843	4848	Sh "V18" O 157 157 0 0 0
4844	4849	Dr 0 0 0
4845	4850	At SMD N 00888000
4846		Ne 29 "/expansion/FPGA_BANK0_IO_11"
	4851	Ne 23 "/expansion/FPGA_BANK0_IO_11"
4847	4852	Po 2558 2558
4848	4853	$EndPAD
4849	4854	$PAD
4850	4855	Sh "V19" O 157 157 0 0 0
4851	4856	Dr 0 0 0
4852	4857	At SMD N 00888000
4853		Ne 28 "/expansion/FPGA_BANK0_IO_10"
	4858	Ne 69 "/fpga1/FPGA_BANK0_IO_10"
4854	4859	Po 2952 2558
4855	4860	$EndPAD
4856	4861	$PAD
...	...
4864	4869	Sh "V21" O 157 157 0 0 0
4865	4870	Dr 0 0 0
4866	4871	At SMD N 00888000
4867		Ne 225 "/fpga2/R_M1_DQ14"
	4872	Ne 216 "/fpga2/R_M1_DQ14"
4868	4873	Po 3739 2558
4869	4874	$EndPAD
4870	4875	$PAD
4871	4876	Sh "V22" O 157 157 0 0 0
4872	4877	Dr 0 0 0
4873	4878	At SMD N 00888000
4874		Ne 226 "/fpga2/R_M1_DQ15"
	4879	Ne 217 "/fpga2/R_M1_DQ15"
4875	4880	Po 4133 2558
4876	4881	$EndPAD
4877	4882	$PAD
...	...
4913	4918	Sh "W6" O 158 157 0 0 0
4914	4919	Dr 0 0 0
4915	4920	At SMD N 00888000
4916		Ne 90 "/fpga1/FPGA_BANK0_IO_57"
	4921	Ne 86 "/fpga1/FPGA_BANK0_IO_57"
4917	4922	Po -2165 2952
4918	4923	$EndPAD
4919	4924	$PAD
...	...
4927	4932	Sh "W8" O 157 157 0 0 0
4928	4933	Dr 0 0 0
4929	4934	At SMD N 00888000
4930		Ne 84 "/fpga1/FPGA_BANK0_IO_48"
	4935	Ne 42 "/expansion/FPGA_BANK0_IO_48"
4931	4936	Po -1377 2952
4932	4937	$EndPAD
4933	4938	$PAD
4934	4939	Sh "W9" O 157 157 0 0 0
4935	4940	Dr 0 0 0
4936	4941	At SMD N 00888000
4937		Ne 46 "/expansion/FPGA_BANK0_IO_50"
	4942	Ne 81 "/fpga1/FPGA_BANK0_IO_50"
4938	4943	Po -983 2952
4939	4944	$EndPAD
4940	4945	$PAD
4941	4946	Sh "W10" O 158 157 0 0 0
4942	4947	Dr 0 0 0
4943	4948	At SMD N 00888000
4944		Ne 43 "/expansion/FPGA_BANK0_IO_46"
	4949	Ne 40 "/expansion/FPGA_BANK0_IO_46"
4945	4950	Po -590 2952
4946	4951	$EndPAD
4947	4952	$PAD
4948	4953	Sh "W11" O 157 157 0 0 0
4949	4954	Dr 0 0 0
4950	4955	At SMD N 00888000
4951		Ne 82 "/fpga1/FPGA_BANK0_IO_44"
	4956	Ne 38 "/expansion/FPGA_BANK0_IO_44"
4952	4957	Po -196 2952
4953	4958	$EndPAD
4954	4959	$PAD
...	...
4962	4967	Sh "W13" O 158 157 0 0 0
4963	4968	Dr 0 0 0
4964	4969	At SMD N 00888000
4965		Ne 77 "/fpga1/FPGA_BANK0_IO_27"
	4970	Ne 76 "/fpga1/FPGA_BANK0_IO_27"
4966	4971	Po 590 2952
4967	4972	$EndPAD
4968	4973	$PAD
4969	4974	Sh "W14" O 157 157 0 0 0
4970	4975	Dr 0 0 0
4971	4976	At SMD N 00888000
4972		Ne 79 "/fpga1/FPGA_BANK0_IO_30"
	4977	Ne 78 "/fpga1/FPGA_BANK0_IO_30"
4973	4978	Po 983 2952
4974	4979	$EndPAD
4975	4980	$PAD
4976	4981	Sh "W15" O 157 157 0 0 0
4977	4982	Dr 0 0 0
4978	4983	At SMD N 00888000
4979		Ne 76 "/fpga1/FPGA_BANK0_IO_25"
	4984	Ne 75 "/fpga1/FPGA_BANK0_IO_25"
4980	4985	Po 1377 2952
4981	4986	$EndPAD
4982	4987	$PAD
...	...
4990	4995	Sh "W17" O 158 157 0 0 0
4991	4996	Dr 0 0 0
4992	4997	At SMD N 00888000
4993		Ne 30 "/expansion/FPGA_BANK0_IO_15"
	4998	Ne 26 "/expansion/FPGA_BANK0_IO_15"
4994	4999	Po 2165 2952
4995	5000	$EndPAD
4996	5001	$PAD
...	...
5088	5093	Sh "Y9" O 157 158 0 0 0
5089	5094	Dr 0 0 0
5090	5095	At SMD N 00888000
5091		Ne 83 "/fpga1/FPGA_BANK0_IO_45"
	5096	Ne 39 "/expansion/FPGA_BANK0_IO_45"
5092	5097	Po -983 3346
5093	5098	$EndPAD
5094	5099	$PAD
5095	5100	Sh "Y10" O 158 158 0 0 0
5096	5101	Dr 0 0 0
5097	5102	At SMD N 00888000
5098		Ne 44 "/expansion/FPGA_BANK0_IO_47"
	5103	Ne 41 "/expansion/FPGA_BANK0_IO_47"
5099	5104	Po -590 3346
5100	5105	$EndPAD
5101	5106	$PAD
5102	5107	Sh "Y11" O 157 158 0 0 0
5103	5108	Dr 0 0 0
5104	5109	At SMD N 00888000
5105		Ne 41 "/expansion/FPGA_BANK0_IO_40"
	5110	Ne 36 "/expansion/FPGA_BANK0_IO_40"
5106	5111	Po -196 3346
5107	5112	$EndPAD
5108	5113	$PAD
...	...
5116	5121	Sh "Y13" O 158 158 0 0 0
5117	5122	Dr 0 0 0
5118	5123	At SMD N 00888000
5119		Ne 39 "/expansion/FPGA_BANK0_IO_38"
	5124	Ne 34 "/expansion/FPGA_BANK0_IO_38"
5120	5125	Po 590 3346
5121	5126	$EndPAD
5122	5127	$PAD
...	...
5130	5135	Sh "Y15" O 157 158 0 0 0
5131	5136	Dr 0 0 0
5132	5137	At SMD N 00888000
5133		Ne 37 "/expansion/FPGA_BANK0_IO_32"
	5138	Ne 79 "/fpga1/FPGA_BANK0_IO_32"
5134	5139	Po 1377 3346
5135	5140	$EndPAD
5136	5141	$PAD
5137	5142	Sh "Y16" O 158 158 0 0 0
5138	5143	Dr 0 0 0
5139	5144	At SMD N 00888000
5140		Ne 75 "/fpga1/FPGA_BANK0_IO_24"
	5145	Ne 28 "/expansion/FPGA_BANK0_IO_24"
5141	5146	Po 1771 3346
5142	5147	$EndPAD
5143	5148	$PAD
5144	5149	Sh "Y17" O 158 158 0 0 0
5145	5150	Dr 0 0 0
5146	5151	At SMD N 00888000
5147		Ne 33 "/expansion/FPGA_BANK0_IO_20"
	5152	Ne 73 "/fpga1/FPGA_BANK0_IO_20"
5148	5153	Po 2165 3346
5149	5154	$EndPAD
5150	5155	$PAD
5151	5156	Sh "Y18" O 157 158 0 0 0
5152	5157	Dr 0 0 0
5153	5158	At SMD N 00888000
5154		Ne 45 "/expansion/FPGA_BANK0_IO_5"
	5159	Ne 43 "/expansion/FPGA_BANK0_IO_5"
5155	5160	Po 2558 3346
5156	5161	$EndPAD
5157	5162	$PAD
5158	5163	Sh "Y19" O 157 158 0 0 0
5159	5164	Dr 0 0 0
5160	5165	At SMD N 00888000
5161		Ne 36 "/expansion/FPGA_BANK0_IO_3"
	5166	Ne 30 "/expansion/FPGA_BANK0_IO_3"
5162	5167	Po 2952 3346
5163	5168	$EndPAD
5164	5169	$PAD
...	...
5179	5184	Sh "Y22" O 157 158 0 0 0
5180	5185	Dr 0 0 0
5181	5186	At SMD N 00888000
5182		Ne 335 "N-000365"
	5187	Ne 335 "N-000366"
5183	5188	Po 4133 3346
5184	5189	$EndPAD
5185	5190	$PAD
5186	5191	Sh "AA1" O 157 157 0 0 0
5187	5192	Dr 0 0 0
5188	5193	At SMD N 00888000
5189		Ne 334 "N-000362"
	5194	Ne 334 "N-000363"
5190	5195	Po -4133 3739
5191	5196	$EndPAD
5192	5197	$PAD
...	...
5277	5282	Sh "AA14" O 157 157 0 0 0
5278	5283	Dr 0 0 0
5279	5284	At SMD N 00888000
5280		Ne 74 "/fpga1/FPGA_BANK0_IO_22"
	5285	Ne 27 "/expansion/FPGA_BANK0_IO_22"
5281	5286	Po 983 3739
5282	5287	$EndPAD
5283	5288	$PAD
...	...
5291	5296	Sh "AA16" O 158 157 0 0 0
5292	5297	Dr 0 0 0
5293	5298	At SMD N 00888000
5294		Ne 78 "/fpga1/FPGA_BANK0_IO_28"
	5299	Ne 29 "/expansion/FPGA_BANK0_IO_28"
5295	5300	Po 1771 3739
5296	5301	$EndPAD
5297	5302	$PAD
...	...
5305	5310	Sh "AA18" O 157 157 0 0 0
5306	5311	Dr 0 0 0
5307	5312	At SMD N 00888000
5308		Ne 73 "/fpga1/FPGA_BANK0_IO_18"
	5313	Ne 71 "/fpga1/FPGA_BANK0_IO_18"
5309	5314	Po 2558 3739
5310	5315	$EndPAD
5311	5316	$PAD
...	...
5319	5324	Sh "AA20" O 158 157 0 0 0
5320	5325	Dr 0 0 0
5321	5326	At SMD N 00888000
5322		Ne 104 "/fpga1/PROG_MISO1"
	5327	Ne 106 "/fpga1/PROG_MISO1"
5323	5328	Po 3346 3739
5324	5329	$EndPAD
5325	5330	$PAD
5326	5331	Sh "AA21" O 157 157 0 0 0
5327	5332	Dr 0 0 0
5328	5333	At SMD N 00888000
5329		Ne 101 "/fpga1/PROG_CCLK"
	5334	Ne 103 "/fpga1/PROG_CCLK"
5330	5335	Po 3739 3739
5331	5336	$EndPAD
5332	5337	$PAD
...	...
5424	5429	Sh "AB13" O 158 157 0 0 0
5425	5430	Dr 0 0 0
5426	5431	At SMD N 00888000
5427		Ne 40 "/expansion/FPGA_BANK0_IO_39"
	5432	Ne 35 "/expansion/FPGA_BANK0_IO_39"
5428	5433	Po 590 4133
5429	5434	$EndPAD
5430	5435	$PAD
...	...
5438	5443	Sh "AB15" O 157 157 0 0 0
5439	5444	Dr 0 0 0
5440	5445	At SMD N 00888000
5441		Ne 80 "/fpga1/FPGA_BANK0_IO_33"
	5446	Ne 31 "/expansion/FPGA_BANK0_IO_33"
5442	5447	Po 1377 4133
5443	5448	$EndPAD
5444	5449	$PAD
5445	5450	Sh "AB16" O 158 157 0 0 0
5446	5451	Dr 0 0 0
5447	5452	At SMD N 00888000
5448		Ne 35 "/expansion/FPGA_BANK0_IO_29"
	5453	Ne 77 "/fpga1/FPGA_BANK0_IO_29"
5449	5454	Po 1771 4133
5450	5455	$EndPAD
5451	5456	$PAD
5452	5457	Sh "AB17" O 158 157 0 0 0
5453	5458	Dr 0 0 0
5454	5459	At SMD N 00888000
5455		Ne 34 "/expansion/FPGA_BANK0_IO_21"
	5460	Ne 74 "/fpga1/FPGA_BANK0_IO_21"
5456	5461	Po 2165 4133
5457	5462	$EndPAD
5458	5463	$PAD
...	...
5473	5478	Sh "AB20" O 158 157 0 0 0
5474	5479	Dr 0 0 0
5475	5480	At SMD N 00888000
5476		Ne 103 "/fpga1/PROG_MISO0"
	5481	Ne 105 "/fpga1/PROG_MISO0"
5477	5482	Po 3346 4133
5478	5483	$EndPAD
5479	5484	$PAD
...	...
5564	5569	Sh "1" R 157 236 0 0 1800
5565	5570	Dr 0 0 0
5566	5571	At SMD N 00440001
5567		Ne 198 "/fpga2/R_M0_UDM"
	5572	Ne 189 "/fpga2/R_M0_UDM"
5568	5573	Po -176 0
5569	5574	$EndPAD
5570	5575	$PAD
5571	5576	Sh "2" R 157 236 0 0 1800
5572	5577	Dr 0 0 0
5573	5578	At SMD N 00440001
5574		Ne 136 "/fpga2/M0_UDM"
	5579	Ne 259 "/sdram/M0_UDM"
5575	5580	Po 176 0
5576	5581	$EndPAD
5577	5582	$EndMODULE 0402
...	...
5592	5597	Sh "1" R 157 236 0 0 1800
5593	5598	Dr 0 0 0
5594	5599	At SMD N 00440001
5595		Ne 199 "/fpga2/R_M0_UDQS"
	5600	Ne 190 "/fpga2/R_M0_UDQS"
5596	5601	Po -176 0
5597	5602	$EndPAD
5598	5603	$PAD
...	...
5620	5625	Sh "1" R 157 236 0 0 1800
5621	5626	Dr 0 0 0
5622	5627	At SMD N 00440001
5623		Ne 178 "/fpga2/R_M0_CKE"
	5628	Ne 169 "/fpga2/R_M0_CKE"
5624	5629	Po -176 0
5625	5630	$EndPAD
5626	5631	$PAD
5627	5632	Sh "2" R 157 236 0 0 1800
5628	5633	Dr 0 0 0
5629	5634	At SMD N 00440001
5630		Ne 251 "/sdram/M0_CKE"
	5635	Ne 245 "/sdram/M0_CKE"
5631	5636	Po 176 0
5632	5637	$EndPAD
5633	5638	$EndMODULE 0402
...	...
5648	5653	Sh "1" R 157 236 0 0 900
5649	5654	Dr 0 0 0
5650	5655	At SMD N 00440001
5651		Ne 123 "/fpga2/M0_CLK"
	5656	Ne 246 "/sdram/M0_CLK"
5652	5657	Po -176 0
5653	5658	$EndPAD
5654	5659	$PAD
5655	5660	Sh "2" R 157 236 0 0 900
5656	5661	Dr 0 0 0
5657	5662	At SMD N 00440001
5658		Ne 252 "/sdram/M0_CLK#"
	5663	Ne 247 "/sdram/M0_CLK#"
5659	5664	Po 176 0
5660	5665	$EndPAD
5661	5666	$EndMODULE 0402
...	...
5674	5679	Sh "1" R 118 157 0 0 2700
5675	5680	Dr 0 0 0
5676	5681	At SMD N 00440001
5677		Ne 162 "/fpga2/R_M0_A0"
	5682	Ne 153 "/fpga2/R_M0_A0"
5678	5683	Po -295 -177
5679	5684	$EndPAD
5680	5685	$PAD
5681	5686	Sh "2" R 118 157 0 0 2700
5682	5687	Dr 0 0 0
5683	5688	At SMD N 00440001
5684		Ne 163 "/fpga2/R_M0_A1"
	5689	Ne 154 "/fpga2/R_M0_A1"
5685	5690	Po -98 -177
5686	5691	$EndPAD
5687	5692	$PAD
5688	5693	Sh "3" R 118 157 0 0 2700
5689	5694	Dr 0 0 0
5690	5695	At SMD N 00440001
5691		Ne 167 "/fpga2/R_M0_A2"
	5696	Ne 158 "/fpga2/R_M0_A2"
5692	5697	Po 98 -177
5693	5698	$EndPAD
5694	5699	$PAD
5695	5700	Sh "4" R 118 157 0 0 2700
5696	5701	Dr 0 0 0
5697	5702	At SMD N 00440001
5698		Ne 168 "/fpga2/R_M0_A3"
	5703	Ne 159 "/fpga2/R_M0_A3"
5699	5704	Po 295 -177
5700	5705	$EndPAD
5701	5706	$PAD
5702	5707	Sh "5" R 118 157 0 0 900
5703	5708	Dr 0 0 0
5704	5709	At SMD N 00440001
5705		Ne 248 "/sdram/M0_A3"
	5710	Ne 238 "/sdram/M0_A3"
5706	5711	Po 295 177
5707	5712	$EndPAD
5708	5713	$PAD
5709	5714	Sh "6" R 118 157 0 0 900
5710	5715	Dr 0 0 0
5711	5716	At SMD N 00440001
5712		Ne 115 "/fpga2/M0_A2"
	5717	Ne 116 "/fpga2/M0_A2"
5713	5718	Po 98 177
5714	5719	$EndPAD
5715	5720	$PAD
5716	5721	Sh "7" R 118 157 0 0 900
5717	5722	Dr 0 0 0
5718	5723	At SMD N 00440001
5719		Ne 246 "/sdram/M0_A1"
	5724	Ne 237 "/sdram/M0_A1"
5720	5725	Po -98 177
5721	5726	$EndPAD
5722	5727	$PAD
...	...
5742	5747	Sh "1" R 118 157 0 0 2700
5743	5748	Dr 0 0 0
5744	5749	At SMD N 00440001
5745		Ne 197 "/fpga2/R_M0_RAS#"
	5750	Ne 188 "/fpga2/R_M0_RAS#"
5746	5751	Po -295 -177
5747	5752	$EndPAD
5748	5753	$PAD
5749	5754	Sh "2" R 118 157 0 0 2700
5750	5755	Dr 0 0 0
5751	5756	At SMD N 00440001
5752		Ne 175 "/fpga2/R_M0_BA0"
	5757	Ne 166 "/fpga2/R_M0_BA0"
5753	5758	Po -98 -177
5754	5759	$EndPAD
5755	5760	$PAD
5756	5761	Sh "3" R 118 157 0 0 2700
5757	5762	Dr 0 0 0
5758	5763	At SMD N 00440001
5759		Ne 176 "/fpga2/R_M0_BA1"
	5764	Ne 167 "/fpga2/R_M0_BA1"
5760	5765	Po 98 -177
5761	5766	$EndPAD
5762	5767	$PAD
5763	5768	Sh "4" R 118 157 0 0 2700
5764	5769	Dr 0 0 0
5765	5770	At SMD N 00440001
5766		Ne 164 "/fpga2/R_M0_A10"
	5771	Ne 155 "/fpga2/R_M0_A10"
5767	5772	Po 295 -177
5768	5773	$EndPAD
5769	5774	$PAD
...	...
5777	5782	Sh "6" R 118 157 0 0 900
5778	5783	Dr 0 0 0
5779	5784	At SMD N 00440001
5780		Ne 250 "/sdram/M0_BA1"
	5785	Ne 243 "/sdram/M0_BA1"
5781	5786	Po 98 177
5782	5787	$EndPAD
5783	5788	$PAD
5784	5789	Sh "7" R 118 157 0 0 900
5785	5790	Dr 0 0 0
5786	5791	At SMD N 00440001
5787		Ne 121 "/fpga2/M0_BA0"
	5792	Ne 242 "/sdram/M0_BA0"
5788	5793	Po -98 177
5789	5794	$EndPAD
5790	5795	$PAD
5791	5796	Sh "8" R 118 157 0 0 900
5792	5797	Dr 0 0 0
5793	5798	At SMD N 00440001
5794		Ne 259 "/sdram/M0_RAS#"
	5799	Ne 258 "/sdram/M0_RAS#"
5795	5800	Po -295 177
5796	5801	$EndPAD
5797	5802	$EndMODULE R_PACK4-0402
...	...
5810	5815	Sh "1" R 118 157 0 0 900
5811	5816	Dr 0 0 0
5812	5817	At SMD N 00440001
5813		Ne 172 "/fpga2/R_M0_A7"
	5818	Ne 163 "/fpga2/R_M0_A7"
5814	5819	Po -295 -177
5815	5820	$EndPAD
5816	5821	$PAD
5817	5822	Sh "2" R 118 157 0 0 900
5818	5823	Dr 0 0 0
5819	5824	At SMD N 00440001
5820		Ne 171 "/fpga2/R_M0_A6"
	5825	Ne 162 "/fpga2/R_M0_A6"
5821	5826	Po -98 -177
5822	5827	$EndPAD
5823	5828	$PAD
5824	5829	Sh "3" R 118 157 0 0 900
5825	5830	Dr 0 0 0
5826	5831	At SMD N 00440001
5827		Ne 170 "/fpga2/R_M0_A5"
	5832	Ne 161 "/fpga2/R_M0_A5"
5828	5833	Po 98 -177
5829	5834	$EndPAD
5830	5835	$PAD
5831	5836	Sh "4" R 118 157 0 0 900
5832	5837	Dr 0 0 0
5833	5838	At SMD N 00440001
5834		Ne 169 "/fpga2/R_M0_A4"
	5839	Ne 160 "/fpga2/R_M0_A4"
5835	5840	Po 295 -177
5836	5841	$EndPAD
5837	5842	$PAD
5838	5843	Sh "5" R 118 157 0 0 2700
5839	5844	Dr 0 0 0
5840	5845	At SMD N 00440001
5841		Ne 116 "/fpga2/M0_A4"
	5846	Ne 239 "/sdram/M0_A4"
5842	5847	Po 295 177
5843	5848	$EndPAD
5844	5849	$PAD
...	...
5852	5857	Sh "7" R 118 157 0 0 2700
5853	5858	Dr 0 0 0
5854	5859	At SMD N 00440001
5855		Ne 249 "/sdram/M0_A6"
	5860	Ne 240 "/sdram/M0_A6"
5856	5861	Po -98 177
5857	5862	$EndPAD
5858	5863	$PAD
...	...
5878	5883	Sh "1" R 118 157 0 0 900
5879	5884	Dr 0 0 0
5880	5885	At SMD N 00440001
5881		Ne 166 "/fpga2/R_M0_A12"
	5886	Ne 157 "/fpga2/R_M0_A12"
5882	5887	Po -295 -177
5883	5888	$EndPAD
5884	5889	$PAD
5885	5890	Sh "2" R 118 157 0 0 900
5886	5891	Dr 0 0 0
5887	5892	At SMD N 00440001
5888		Ne 165 "/fpga2/R_M0_A11"
	5893	Ne 156 "/fpga2/R_M0_A11"
5889	5894	Po -98 -177
5890	5895	$EndPAD
5891	5896	$PAD
5892	5897	Sh "3" R 118 157 0 0 900
5893	5898	Dr 0 0 0
5894	5899	At SMD N 00440001
5895		Ne 174 "/fpga2/R_M0_A9"
	5900	Ne 165 "/fpga2/R_M0_A9"
5896	5901	Po 98 -177
5897	5902	$EndPAD
5898	5903	$PAD
5899	5904	Sh "4" R 118 157 0 0 900
5900	5905	Dr 0 0 0
5901	5906	At SMD N 00440001
5902		Ne 173 "/fpga2/R_M0_A8"
	5907	Ne 164 "/fpga2/R_M0_A8"
5903	5908	Po 295 -177
5904	5909	$EndPAD
5905	5910	$PAD
5906	5911	Sh "5" R 118 157 0 0 2700
5907	5912	Dr 0 0 0
5908	5913	At SMD N 00440001
5909		Ne 119 "/fpga2/M0_A8"
	5914	Ne 241 "/sdram/M0_A8"
5910	5915	Po 295 177
5911	5916	$EndPAD
5912	5917	$PAD
5913	5918	Sh "6" R 118 157 0 0 2700
5914	5919	Dr 0 0 0
5915	5920	At SMD N 00440001
5916		Ne 120 "/fpga2/M0_A9"
	5921	Ne 119 "/fpga2/M0_A9"
5917	5922	Po 98 177
5918	5923	$EndPAD
5919	5924	$PAD
5920	5925	Sh "7" R 118 157 0 0 2700
5921	5926	Dr 0 0 0
5922	5927	At SMD N 00440001
5923		Ne 247 "/sdram/M0_A11"
	5928	Ne 114 "/fpga2/M0_A11"
5924	5929	Po -98 177
5925	5930	$EndPAD
5926	5931	$PAD
5927	5932	Sh "8" R 118 157 0 0 2700
5928	5933	Dr 0 0 0
5929	5934	At SMD N 00440001
5930		Ne 114 "/fpga2/M0_A12"
	5935	Ne 115 "/fpga2/M0_A12"
5931	5936	Po -295 177
5932	5937	$EndPAD
5933	5938	$EndMODULE R_PACK4-0402
...	...
5946	5951	Sh "1" R 118 157 0 0 2700
5947	5952	Dr 0 0 0
5948	5953	At SMD N 00440001
5949		Ne 189 "/fpga2/R_M0_DQ4"
	5954	Ne 180 "/fpga2/R_M0_DQ4"
5950	5955	Po -295 -177
5951	5956	$EndPAD
5952	5957	$PAD
5953	5958	Sh "2" R 118 157 0 0 2700
5954	5959	Dr 0 0 0
5955	5960	At SMD N 00440001
5956		Ne 190 "/fpga2/R_M0_DQ5"
	5961	Ne 181 "/fpga2/R_M0_DQ5"
5957	5962	Po -98 -177
5958	5963	$EndPAD
5959	5964	$PAD
5960	5965	Sh "3" R 118 157 0 0 2700
5961	5966	Dr 0 0 0
5962	5967	At SMD N 00440001
5963		Ne 191 "/fpga2/R_M0_DQ6"
	5968	Ne 182 "/fpga2/R_M0_DQ6"
5964	5969	Po 98 -177
5965	5970	$EndPAD
5966	5971	$PAD
5967	5972	Sh "4" R 118 157 0 0 2700
5968	5973	Dr 0 0 0
5969	5974	At SMD N 00440001
5970		Ne 192 "/fpga2/R_M0_DQ7"
	5975	Ne 183 "/fpga2/R_M0_DQ7"
5971	5976	Po 295 -177
5972	5977	$EndPAD
5973	5978	$PAD
5974	5979	Sh "5" R 118 157 0 0 900
5975	5980	Dr 0 0 0
5976	5981	At SMD N 00440001
5977		Ne 132 "/fpga2/M0_DQ7"
	5982	Ne 256 "/sdram/M0_DQ7"
5978	5983	Po 295 177
5979	5984	$EndPAD
5980	5985	$PAD
5981	5986	Sh "6" R 118 157 0 0 900
5982	5987	Dr 0 0 0
5983	5988	At SMD N 00440001
5984		Ne 131 "/fpga2/M0_DQ6"
	5989	Ne 255 "/sdram/M0_DQ6"
5985	5990	Po 98 177
5986	5991	$EndPAD
5987	5992	$PAD
5988	5993	Sh "7" R 118 157 0 0 900
5989	5994	Dr 0 0 0
5990	5995	At SMD N 00440001
5991		Ne 257 "/sdram/M0_DQ5"
	5996	Ne 124 "/fpga2/M0_DQ5"
5992	5997	Po -98 177
5993	5998	$EndPAD
5994	5999	$PAD
5995	6000	Sh "8" R 118 157 0 0 900
5996	6001	Dr 0 0 0
5997	6002	At SMD N 00440001
5998		Ne 256 "/sdram/M0_DQ4"
	6003	Ne 254 "/sdram/M0_DQ4"
5999	6004	Po -295 177
6000	6005	$EndPAD
6001	6006	$EndMODULE R_PACK4-0402
...	...
6014	6019	Sh "1" R 118 157 0 0 2700
6015	6020	Dr 0 0 0
6016	6021	At SMD N 00440001
6017		Ne 179 "/fpga2/R_M0_DQ0"
	6022	Ne 170 "/fpga2/R_M0_DQ0"
6018	6023	Po -295 -177
6019	6024	$EndPAD
6020	6025	$PAD
6021	6026	Sh "2" R 118 157 0 0 2700
6022	6027	Dr 0 0 0
6023	6028	At SMD N 00440001
6024		Ne 180 "/fpga2/R_M0_DQ1"
	6029	Ne 171 "/fpga2/R_M0_DQ1"
6025	6030	Po -98 -177
6026	6031	$EndPAD
6027	6032	$PAD
6028	6033	Sh "3" R 118 157 0 0 2700
6029	6034	Dr 0 0 0
6030	6035	At SMD N 00440001
6031		Ne 187 "/fpga2/R_M0_DQ2"
	6036	Ne 178 "/fpga2/R_M0_DQ2"
6032	6037	Po 98 -177
6033	6038	$EndPAD
6034	6039	$PAD
6035	6040	Sh "4" R 118 157 0 0 2700
6036	6041	Dr 0 0 0
6037	6042	At SMD N 00440001
6038		Ne 188 "/fpga2/R_M0_DQ3"
	6043	Ne 179 "/fpga2/R_M0_DQ3"
6039	6044	Po 295 -177
6040	6045	$EndPAD
6041	6046	$PAD
6042	6047	Sh "5" R 118 157 0 0 900
6043	6048	Dr 0 0 0
6044	6049	At SMD N 00440001
6045		Ne 130 "/fpga2/M0_DQ3"
	6050	Ne 123 "/fpga2/M0_DQ3"
6046	6051	Po 295 177
6047	6052	$EndPAD
6048	6053	$PAD
6049	6054	Sh "6" R 118 157 0 0 900
6050	6055	Dr 0 0 0
6051	6056	At SMD N 00440001
6052		Ne 129 "/fpga2/M0_DQ2"
	6057	Ne 122 "/fpga2/M0_DQ2"
6053	6058	Po 98 177
6054	6059	$EndPAD
6055	6060	$PAD
6056	6061	Sh "7" R 118 157 0 0 900
6057	6062	Dr 0 0 0
6058	6063	At SMD N 00440001
6059		Ne 125 "/fpga2/M0_DQ1"
	6064	Ne 120 "/fpga2/M0_DQ1"
6060	6065	Po -98 177
6061	6066	$EndPAD
6062	6067	$PAD
6063	6068	Sh "8" R 118 157 0 0 900
6064	6069	Dr 0 0 0
6065	6070	At SMD N 00440001
6066		Ne 124 "/fpga2/M0_DQ0"
	6071	Ne 248 "/sdram/M0_DQ0"
6067	6072	Po -295 177
6068	6073	$EndPAD
6069	6074	$EndMODULE R_PACK4-0402
...	...
6082	6087	Sh "1" R 118 157 0 0 900
6083	6088	Dr 0 0 0
6084	6089	At SMD N 00440001
6085		Ne 193 "/fpga2/R_M0_DQ8"
	6090	Ne 184 "/fpga2/R_M0_DQ8"
6086	6091	Po -295 -177
6087	6092	$EndPAD
6088	6093	$PAD
6089	6094	Sh "2" R 118 157 0 0 900
6090	6095	Dr 0 0 0
6091	6096	At SMD N 00440001
6092		Ne 194 "/fpga2/R_M0_DQ9"
	6097	Ne 185 "/fpga2/R_M0_DQ9"
6093	6098	Po -98 -177
6094	6099	$EndPAD
6095	6100	$PAD
6096	6101	Sh "3" R 118 157 0 0 900
6097	6102	Dr 0 0 0
6098	6103	At SMD N 00440001
6099		Ne 181 "/fpga2/R_M0_DQ10"
	6104	Ne 172 "/fpga2/R_M0_DQ10"
6100	6105	Po 98 -177
6101	6106	$EndPAD
6102	6107	$PAD
6103	6108	Sh "4" R 118 157 0 0 900
6104	6109	Dr 0 0 0
6105	6110	At SMD N 00440001
6106		Ne 182 "/fpga2/R_M0_DQ11"
	6111	Ne 173 "/fpga2/R_M0_DQ11"
6107	6112	Po 295 -177
6108	6113	$EndPAD
6109	6114	$PAD
6110	6115	Sh "5" R 118 157 0 0 2700
6111	6116	Dr 0 0 0
6112	6117	At SMD N 00440001
6113		Ne 127 "/fpga2/M0_DQ11"
	6118	Ne 121 "/fpga2/M0_DQ11"
6114	6119	Po 295 177
6115	6120	$EndPAD
6116	6121	$PAD
6117	6122	Sh "6" R 118 157 0 0 2700
6118	6123	Dr 0 0 0
6119	6124	At SMD N 00440001
6120		Ne 126 "/fpga2/M0_DQ10"
	6125	Ne 249 "/sdram/M0_DQ10"
6121	6126	Po 98 177
6122	6127	$EndPAD
6123	6128	$PAD
6124	6129	Sh "7" R 118 157 0 0 2700
6125	6130	Dr 0 0 0
6126	6131	At SMD N 00440001
6127		Ne 133 "/fpga2/M0_DQ9"
	6132	Ne 126 "/fpga2/M0_DQ9"
6128	6133	Po -98 177
6129	6134	$EndPAD
6130	6135	$PAD
6131	6136	Sh "8" R 118 157 0 0 2700
6132	6137	Dr 0 0 0
6133	6138	At SMD N 00440001
6134		Ne 258 "/sdram/M0_DQ8"
	6139	Ne 125 "/fpga2/M0_DQ8"
6135	6140	Po -295 177
6136	6141	$EndPAD
6137	6142	$EndMODULE R_PACK4-0402
...	...
6150	6155	Sh "1" R 118 157 0 0 900
6151	6156	Dr 0 0 0
6152	6157	At SMD N 00440001
6153		Ne 183 "/fpga2/R_M0_DQ12"
	6158	Ne 174 "/fpga2/R_M0_DQ12"
6154	6159	Po -295 -177
6155	6160	$EndPAD
6156	6161	$PAD
6157	6162	Sh "2" R 118 157 0 0 900
6158	6163	Dr 0 0 0
6159	6164	At SMD N 00440001
6160		Ne 184 "/fpga2/R_M0_DQ13"
	6165	Ne 175 "/fpga2/R_M0_DQ13"
6161	6166	Po -98 -177
6162	6167	$EndPAD
6163	6168	$PAD
6164	6169	Sh "3" R 118 157 0 0 900
6165	6170	Dr 0 0 0
6166	6171	At SMD N 00440001
6167		Ne 185 "/fpga2/R_M0_DQ14"
	6172	Ne 176 "/fpga2/R_M0_DQ14"
6168	6173	Po 98 -177
6169	6174	$EndPAD
6170	6175	$PAD
6171	6176	Sh "4" R 118 157 0 0 900
6172	6177	Dr 0 0 0
6173	6178	At SMD N 00440001
6174		Ne 186 "/fpga2/R_M0_DQ15"
	6179	Ne 177 "/fpga2/R_M0_DQ15"
6175	6180	Po 295 -177
6176	6181	$EndPAD
6177	6182	$PAD
6178	6183	Sh "5" R 118 157 0 0 2700
6179	6184	Dr 0 0 0
6180	6185	At SMD N 00440001
6181		Ne 128 "/fpga2/M0_DQ15"
	6186	Ne 253 "/sdram/M0_DQ15"
6182	6187	Po 295 177
6183	6188	$EndPAD
6184	6189	$PAD
6185	6190	Sh "6" R 118 157 0 0 2700
6186	6191	Dr 0 0 0
6187	6192	At SMD N 00440001
6188		Ne 255 "/sdram/M0_DQ14"
	6193	Ne 252 "/sdram/M0_DQ14"
6189	6194	Po 98 177
6190	6195	$EndPAD
6191	6196	$PAD
6192	6197	Sh "7" R 118 157 0 0 2700
6193	6198	Dr 0 0 0
6194	6199	At SMD N 00440001
6195		Ne 254 "/sdram/M0_DQ13"
	6200	Ne 251 "/sdram/M0_DQ13"
6196	6201	Po -98 177
6197	6202	$EndPAD
6198	6203	$PAD
6199	6204	Sh "8" R 118 157 0 0 2700
6200	6205	Dr 0 0 0
6201	6206	At SMD N 00440001
6202		Ne 253 "/sdram/M0_DQ12"
	6207	Ne 250 "/sdram/M0_DQ12"
6203	6208	Po -295 177
6204	6209	$EndPAD
6205	6210	$EndMODULE R_PACK4-0402
...	...
6220	6225	Sh "1" R 157 236 0 0 900
6221	6226	Dr 0 0 0
6222	6227	At SMD N 00440001
6223		Ne 239 "/fpga2/R_M1_UDQS"
	6228	Ne 230 "/fpga2/R_M1_UDQS"
6224	6229	Po -176 0
6225	6230	$EndPAD
6226	6231	$PAD
6227	6232	Sh "2" R 157 236 0 0 900
6228	6233	Dr 0 0 0
6229	6234	At SMD N 00440001
6230		Ne 161 "/fpga2/M1_UDQS"
	6235	Ne 278 "/sdram/M1_UDQS"
6231	6236	Po 176 0
6232	6237	$EndPAD
6233	6238	$EndMODULE 0402
...	...
6248	6253	Sh "1" R 157 236 0 0 0
6249	6254	Dr 0 0 0
6250	6255	At SMD N 00440001
6251		Ne 218 "/fpga2/R_M1_CS#"
	6256	Ne 209 "/fpga2/R_M1_CS#"
6252	6257	Po -176 0
6253	6258	$EndPAD
6254	6259	$PAD
6255	6260	Sh "2" R 157 236 0 0 0
6256	6261	Dr 0 0 0
6257	6262	At SMD N 00440001
6258		Ne 148 "/fpga2/M1_CS#"
	6263	Ne 138 "/fpga2/M1_CS#"
6259	6264	Po 176 0
6260	6265	$EndPAD
6261	6266	$EndMODULE 0402
...	...
6276	6281	Sh "1" R 157 236 0 0 2700
6277	6282	Dr 0 0 0
6278	6283	At SMD N 00440001
6279		Ne 217 "/fpga2/R_M1_CKE"
	6284	Ne 208 "/fpga2/R_M1_CKE"
6280	6285	Po -176 0
6281	6286	$EndPAD
6282	6287	$PAD
6283	6288	Sh "2" R 157 236 0 0 2700
6284	6289	Dr 0 0 0
6285	6290	At SMD N 00440001
6286		Ne 145 "/fpga2/M1_CKE"
	6291	Ne 271 "/sdram/M1_CKE"
6287	6292	Po 176 0
6288	6293	$EndPAD
6289	6294	$EndMODULE 0402
...	...
6304	6309	Sh "1" R 157 236 0 0 0
6305	6310	Dr 0 0 0
6306	6311	At SMD N 00440001
6307		Ne 238 "/fpga2/R_M1_UDM"
	6312	Ne 229 "/fpga2/R_M1_UDM"
6308	6313	Po -176 0
6309	6314	$EndPAD
6310	6315	$PAD
6311	6316	Sh "2" R 157 236 0 0 0
6312	6317	Dr 0 0 0
6313	6318	At SMD N 00440001
6314		Ne 278 "/sdram/M1_UDM"
	6319	Ne 277 "/sdram/M1_UDM"
6315	6320	Po 176 0
6316	6321	$EndPAD
6317	6322	$EndMODULE 0402
...	...
6330	6335	Sh "1" R 118 157 0 0 2700
6331	6336	Dr 0 0 0
6332	6337	At SMD N 00440001
6333		Ne 153 "/fpga2/M1_DQ15"
	6338	Ne 143 "/fpga2/M1_DQ15"
6334	6339	Po -295 -177
6335	6340	$EndPAD
6336	6341	$PAD
6337	6342	Sh "2" R 118 157 0 0 2700
6338	6343	Dr 0 0 0
6339	6344	At SMD N 00440001
6340		Ne 152 "/fpga2/M1_DQ14"
	6345	Ne 142 "/fpga2/M1_DQ14"
6341	6346	Po -98 -177
6342	6347	$EndPAD
6343	6348	$PAD
6344	6349	Sh "3" R 118 157 0 0 2700
6345	6350	Dr 0 0 0
6346	6351	At SMD N 00440001
6347		Ne 273 "/sdram/M1_DQ13"
	6352	Ne 141 "/fpga2/M1_DQ13"
6348	6353	Po 98 -177
6349	6354	$EndPAD
6350	6355	$PAD
6351	6356	Sh "4" R 118 157 0 0 2700
6352	6357	Dr 0 0 0
6353	6358	At SMD N 00440001
6354		Ne 272 "/sdram/M1_DQ12"
	6359	Ne 140 "/fpga2/M1_DQ12"
6355	6360	Po 295 -177
6356	6361	$EndPAD
6357	6362	$PAD
6358	6363	Sh "5" R 118 157 0 0 900
6359	6364	Dr 0 0 0
6360	6365	At SMD N 00440001
6361		Ne 223 "/fpga2/R_M1_DQ12"
	6366	Ne 214 "/fpga2/R_M1_DQ12"
6362	6367	Po 295 177
6363	6368	$EndPAD
6364	6369	$PAD
6365	6370	Sh "6" R 118 157 0 0 900
6366	6371	Dr 0 0 0
6367	6372	At SMD N 00440001
6368		Ne 224 "/fpga2/R_M1_DQ13"
	6373	Ne 215 "/fpga2/R_M1_DQ13"
6369	6374	Po 98 177
6370	6375	$EndPAD
6371	6376	$PAD
6372	6377	Sh "7" R 118 157 0 0 900
6373	6378	Dr 0 0 0
6374	6379	At SMD N 00440001
6375		Ne 225 "/fpga2/R_M1_DQ14"
	6380	Ne 216 "/fpga2/R_M1_DQ14"
6376	6381	Po -98 177
6377	6382	$EndPAD
6378	6383	$PAD
6379	6384	Sh "8" R 118 157 0 0 900
6380	6385	Dr 0 0 0
6381	6386	At SMD N 00440001
6382		Ne 226 "/fpga2/R_M1_DQ15"
	6387	Ne 217 "/fpga2/R_M1_DQ15"
6383	6388	Po -295 177
6384	6389	$EndPAD
6385	6390	$EndMODULE R_PACK4-0402
...	...
6398	6403	Sh "1" R 118 157 0 0 2700
6399	6404	Dr 0 0 0
6400	6405	At SMD N 00440001
6401		Ne 151 "/fpga2/M1_DQ11"
	6406	Ne 274 "/sdram/M1_DQ11"
6402	6407	Po -295 -177
6403	6408	$EndPAD
6404	6409	$PAD
6405	6410	Sh "2" R 118 157 0 0 2700
6406	6411	Dr 0 0 0
6407	6412	At SMD N 00440001
6408		Ne 150 "/fpga2/M1_DQ10"
	6413	Ne 273 "/sdram/M1_DQ10"
6409	6414	Po -98 -177
6410	6415	$EndPAD
6411	6416	$PAD
6412	6417	Sh "3" R 118 157 0 0 2700
6413	6418	Dr 0 0 0
6414	6419	At SMD N 00440001
6415		Ne 159 "/fpga2/M1_DQ9"
	6420	Ne 150 "/fpga2/M1_DQ9"
6416	6421	Po 98 -177
6417	6422	$EndPAD
6418	6423	$PAD
6419	6424	Sh "4" R 118 157 0 0 2700
6420	6425	Dr 0 0 0
6421	6426	At SMD N 00440001
6422		Ne 158 "/fpga2/M1_DQ8"
	6427	Ne 149 "/fpga2/M1_DQ8"
6423	6428	Po 295 -177
6424	6429	$EndPAD
6425	6430	$PAD
6426	6431	Sh "5" R 118 157 0 0 900
6427	6432	Dr 0 0 0
6428	6433	At SMD N 00440001
6429		Ne 233 "/fpga2/R_M1_DQ8"
	6434	Ne 224 "/fpga2/R_M1_DQ8"
6430	6435	Po 295 177
6431	6436	$EndPAD
6432	6437	$PAD
6433	6438	Sh "6" R 118 157 0 0 900
6434	6439	Dr 0 0 0
6435	6440	At SMD N 00440001
6436		Ne 234 "/fpga2/R_M1_DQ9"
	6441	Ne 225 "/fpga2/R_M1_DQ9"
6437	6442	Po 98 177
6438	6443	$EndPAD
6439	6444	$PAD
6440	6445	Sh "7" R 118 157 0 0 900
6441	6446	Dr 0 0 0
6442	6447	At SMD N 00440001
6443		Ne 221 "/fpga2/R_M1_DQ10"
	6448	Ne 212 "/fpga2/R_M1_DQ10"
6444	6449	Po -98 177
6445	6450	$EndPAD
6446	6451	$PAD
6447	6452	Sh "8" R 118 157 0 0 900
6448	6453	Dr 0 0 0
6449	6454	At SMD N 00440001
6450		Ne 222 "/fpga2/R_M1_DQ11"
	6455	Ne 213 "/fpga2/R_M1_DQ11"
6451	6456	Po -295 177
6452	6457	$EndPAD
6453	6458	$EndMODULE R_PACK4-0402
...	...
6468	6473	Sh "1" R 157 236 0 0 900
6469	6474	Dr 0 0 0
6470	6475	At SMD N 00440001
6471		Ne 147 "/fpga2/M1_CLK#"
	6476	Ne 137 "/fpga2/M1_CLK#"
6472	6477	Po -176 0
6473	6478	$EndPAD
6474	6479	$PAD
6475	6480	Sh "2" R 157 236 0 0 900
6476	6481	Dr 0 0 0
6477	6482	At SMD N 00440001
6478		Ne 146 "/fpga2/M1_CLK"
	6483	Ne 136 "/fpga2/M1_CLK"
6479	6484	Po 176 0
6480	6485	$EndPAD
6481	6486	$EndMODULE 0402
...	...
6494	6499	Sh "1" R 118 157 0 0 2700
6495	6500	Dr 0 0 0
6496	6501	At SMD N 00440001
6497		Ne 265 "/sdram/M1_A12"
	6502	Ne 130 "/fpga2/M1_A12"
6498	6503	Po -295 -177
6499	6504	$EndPAD
6500	6505	$PAD
6501	6506	Sh "2" R 118 157 0 0 2700
6502	6507	Dr 0 0 0
6503	6508	At SMD N 00440001
6504		Ne 138 "/fpga2/M1_A11"
	6509	Ne 264 "/sdram/M1_A11"
6505	6510	Po -98 -177
6506	6511	$EndPAD
6507	6512	$PAD
6508	6513	Sh "3" R 118 157 0 0 2700
6509	6514	Dr 0 0 0
6510	6515	At SMD N 00440001
6511		Ne 143 "/fpga2/M1_A9"
	6516	Ne 269 "/sdram/M1_A9"
6512	6517	Po 98 -177
6513	6518	$EndPAD
6514	6519	$PAD
6515	6520	Sh "4" R 118 157 0 0 2700
6516	6521	Dr 0 0 0
6517	6522	At SMD N 00440001
6518		Ne 142 "/fpga2/M1_A8"
	6523	Ne 133 "/fpga2/M1_A8"
6519	6524	Po 295 -177
6520	6525	$EndPAD
6521	6526	$PAD
6522	6527	Sh "5" R 118 157 0 0 900
6523	6528	Dr 0 0 0
6524	6529	At SMD N 00440001
6525		Ne 212 "/fpga2/R_M1_A8"
	6530	Ne 203 "/fpga2/R_M1_A8"
6526	6531	Po 295 177
6527	6532	$EndPAD
6528	6533	$PAD
6529	6534	Sh "6" R 118 157 0 0 900
6530	6535	Dr 0 0 0
6531	6536	At SMD N 00440001
6532		Ne 213 "/fpga2/R_M1_A9"
	6537	Ne 204 "/fpga2/R_M1_A9"
6533	6538	Po 98 177
6534	6539	$EndPAD
6535	6540	$PAD
6536	6541	Sh "7" R 118 157 0 0 900
6537	6542	Dr 0 0 0
6538	6543	At SMD N 00440001
6539		Ne 204 "/fpga2/R_M1_A11"
	6544	Ne 195 "/fpga2/R_M1_A11"
6540	6545	Po -98 177
6541	6546	$EndPAD
6542	6547	$PAD
6543	6548	Sh "8" R 118 157 0 0 900
6544	6549	Dr 0 0 0
6545	6550	At SMD N 00440001
6546		Ne 205 "/fpga2/R_M1_A12"
	6551	Ne 196 "/fpga2/R_M1_A12"
6547	6552	Po -295 177
6548	6553	$EndPAD
6549	6554	$EndMODULE R_PACK4-0402
...	...
6562	6567	Sh "1" R 118 157 0 0 2700
6563	6568	Dr 0 0 0
6564	6569	At SMD N 00440001
6565		Ne 141 "/fpga2/M1_A7"
	6570	Ne 268 "/sdram/M1_A7"
6566	6571	Po -295 -177
6567	6572	$EndPAD
6568	6573	$PAD
6569	6574	Sh "2" R 118 157 0 0 2700
6570	6575	Dr 0 0 0
6571	6576	At SMD N 00440001
6572		Ne 140 "/fpga2/M1_A6"
	6577	Ne 132 "/fpga2/M1_A6"
6573	6578	Po -98 -177
6574	6579	$EndPAD
6575	6580	$PAD
6576	6581	Sh "3" R 118 157 0 0 2700
6577	6582	Dr 0 0 0
6578	6583	At SMD N 00440001
6579		Ne 268 "/sdram/M1_A5"
	6584	Ne 131 "/fpga2/M1_A5"
6580	6585	Po 98 -177
6581	6586	$EndPAD
6582	6587	$PAD
...	...
6590	6595	Sh "5" R 118 157 0 0 900
6591	6596	Dr 0 0 0
6592	6597	At SMD N 00440001
6593		Ne 208 "/fpga2/R_M1_A4"
	6598	Ne 199 "/fpga2/R_M1_A4"
6594	6599	Po 295 177
6595	6600	$EndPAD
6596	6601	$PAD
6597	6602	Sh "6" R 118 157 0 0 900
6598	6603	Dr 0 0 0
6599	6604	At SMD N 00440001
6600		Ne 209 "/fpga2/R_M1_A5"
	6605	Ne 200 "/fpga2/R_M1_A5"
6601	6606	Po 98 177
6602	6607	$EndPAD
6603	6608	$PAD
6604	6609	Sh "7" R 118 157 0 0 900
6605	6610	Dr 0 0 0
6606	6611	At SMD N 00440001
6607		Ne 210 "/fpga2/R_M1_A6"
	6612	Ne 201 "/fpga2/R_M1_A6"
6608	6613	Po -98 177
6609	6614	$EndPAD
6610	6615	$PAD
6611	6616	Sh "8" R 118 157 0 0 900
6612	6617	Dr 0 0 0
6613	6618	At SMD N 00440001
6614		Ne 211 "/fpga2/R_M1_A7"
	6619	Ne 202 "/fpga2/R_M1_A7"
6615	6620	Po -295 177
6616	6621	$EndPAD
6617	6622	$EndMODULE R_PACK4-0402
...	...
6630	6635	Sh "1" R 118 157 0 0 2700
6631	6636	Dr 0 0 0
6632	6637	At SMD N 00440001
6633		Ne 219 "/fpga2/R_M1_DQ0"
	6638	Ne 210 "/fpga2/R_M1_DQ0"
6634	6639	Po -295 -177
6635	6640	$EndPAD
6636	6641	$PAD
6637	6642	Sh "2" R 118 157 0 0 2700
6638	6643	Dr 0 0 0
6639	6644	At SMD N 00440001
6640		Ne 220 "/fpga2/R_M1_DQ1"
	6645	Ne 211 "/fpga2/R_M1_DQ1"
6641	6646	Po -98 -177
6642	6647	$EndPAD
6643	6648	$PAD
6644	6649	Sh "3" R 118 157 0 0 2700
6645	6650	Dr 0 0 0
6646	6651	At SMD N 00440001
6647		Ne 227 "/fpga2/R_M1_DQ2"
	6652	Ne 218 "/fpga2/R_M1_DQ2"
6648	6653	Po 98 -177
6649	6654	$EndPAD
6650	6655	$PAD
6651	6656	Sh "4" R 118 157 0 0 2700
6652	6657	Dr 0 0 0
6653	6658	At SMD N 00440001
6654		Ne 228 "/fpga2/R_M1_DQ3"
	6659	Ne 219 "/fpga2/R_M1_DQ3"
6655	6660	Po 295 -177
6656	6661	$EndPAD
6657	6662	$PAD
6658	6663	Sh "5" R 118 157 0 0 900
6659	6664	Dr 0 0 0
6660	6665	At SMD N 00440001
6661		Ne 155 "/fpga2/M1_DQ3"
	6666	Ne 144 "/fpga2/M1_DQ3"
6662	6667	Po 295 177
6663	6668	$EndPAD
6664	6669	$PAD
6665	6670	Sh "6" R 118 157 0 0 900
6666	6671	Dr 0 0 0
6667	6672	At SMD N 00440001
6668		Ne 154 "/fpga2/M1_DQ2"
	6673	Ne 275 "/sdram/M1_DQ2"
6669	6674	Po 98 177
6670	6675	$EndPAD
6671	6676	$PAD
6672	6677	Sh "7" R 118 157 0 0 900
6673	6678	Dr 0 0 0
6674	6679	At SMD N 00440001
6675		Ne 271 "/sdram/M1_DQ1"
	6680	Ne 272 "/sdram/M1_DQ1"
6676	6681	Po -98 177
6677	6682	$EndPAD
6678	6683	$PAD
6679	6684	Sh "8" R 118 157 0 0 900
6680	6685	Dr 0 0 0
6681	6686	At SMD N 00440001
6682		Ne 149 "/fpga2/M1_DQ0"
	6687	Ne 139 "/fpga2/M1_DQ0"
6683	6688	Po -295 177
6684	6689	$EndPAD
6685	6690	$EndMODULE R_PACK4-0402
...	...
6698	6703	Sh "1" R 118 157 0 0 2700
6699	6704	Dr 0 0 0
6700	6705	At SMD N 00440001
6701		Ne 229 "/fpga2/R_M1_DQ4"
	6706	Ne 220 "/fpga2/R_M1_DQ4"
6702	6707	Po -295 -177
6703	6708	$EndPAD
6704	6709	$PAD
6705	6710	Sh "2" R 118 157 0 0 2700
6706	6711	Dr 0 0 0
6707	6712	At SMD N 00440001
6708		Ne 230 "/fpga2/R_M1_DQ5"
	6713	Ne 221 "/fpga2/R_M1_DQ5"
6709	6714	Po -98 -177
6710	6715	$EndPAD
6711	6716	$PAD
6712	6717	Sh "3" R 118 157 0 0 2700
6713	6718	Dr 0 0 0
6714	6719	At SMD N 00440001
6715		Ne 231 "/fpga2/R_M1_DQ6"
	6720	Ne 222 "/fpga2/R_M1_DQ6"
6716	6721	Po 98 -177
6717	6722	$EndPAD
6718	6723	$PAD
6719	6724	Sh "4" R 118 157 0 0 2700
6720	6725	Dr 0 0 0
6721	6726	At SMD N 00440001
6722		Ne 232 "/fpga2/R_M1_DQ7"
	6727	Ne 223 "/fpga2/R_M1_DQ7"
6723	6728	Po 295 -177
6724	6729	$EndPAD
6725	6730	$PAD
6726	6731	Sh "5" R 118 157 0 0 900
6727	6732	Dr 0 0 0
6728	6733	At SMD N 00440001
6729		Ne 157 "/fpga2/M1_DQ7"
	6734	Ne 148 "/fpga2/M1_DQ7"
6730	6735	Po 295 177
6731	6736	$EndPAD
6732	6737	$PAD
6733	6738	Sh "6" R 118 157 0 0 900
6734	6739	Dr 0 0 0
6735	6740	At SMD N 00440001
6736		Ne 275 "/sdram/M1_DQ6"
	6741	Ne 147 "/fpga2/M1_DQ6"
6737	6742	Po 98 177
6738	6743	$EndPAD
6739	6744	$PAD
6740	6745	Sh "7" R 118 157 0 0 900
6741	6746	Dr 0 0 0
6742	6747	At SMD N 00440001
6743		Ne 274 "/sdram/M1_DQ5"
	6748	Ne 146 "/fpga2/M1_DQ5"
6744	6749	Po -98 177
6745	6750	$EndPAD
6746	6751	$PAD
6747	6752	Sh "8" R 118 157 0 0 900
6748	6753	Dr 0 0 0
6749	6754	At SMD N 00440001
6750		Ne 156 "/fpga2/M1_DQ4"
	6755	Ne 145 "/fpga2/M1_DQ4"
6751	6756	Po -295 177
6752	6757	$EndPAD
6753	6758	$EndMODULE R_PACK4-0402
...	...
6766	6771	Sh "1" R 118 157 0 0 2700
6767	6772	Dr 0 0 0
6768	6773	At SMD N 00440001
6769		Ne 237 "/fpga2/R_M1_RAS#"
	6774	Ne 228 "/fpga2/R_M1_RAS#"
6770	6775	Po -295 -177
6771	6776	$EndPAD
6772	6777	$PAD
6773	6778	Sh "2" R 118 157 0 0 2700
6774	6779	Dr 0 0 0
6775	6780	At SMD N 00440001
6776		Ne 214 "/fpga2/R_M1_BA0"
	6781	Ne 205 "/fpga2/R_M1_BA0"
6777	6782	Po -98 -177
6778	6783	$EndPAD
6779	6784	$PAD
6780	6785	Sh "3" R 118 157 0 0 2700
6781	6786	Dr 0 0 0
6782	6787	At SMD N 00440001
6783		Ne 215 "/fpga2/R_M1_BA1"
	6788	Ne 206 "/fpga2/R_M1_BA1"
6784	6789	Po 98 -177
6785	6790	$EndPAD
6786	6791	$PAD
6787	6792	Sh "4" R 118 157 0 0 2700
6788	6793	Dr 0 0 0
6789	6794	At SMD N 00440001
6790		Ne 203 "/fpga2/R_M1_A10"
	6795	Ne 194 "/fpga2/R_M1_A10"
6791	6796	Po 295 -177
6792	6797	$EndPAD
6793	6798	$PAD
6794	6799	Sh "5" R 118 157 0 0 900
6795	6800	Dr 0 0 0
6796	6801	At SMD N 00440001
6797		Ne 264 "/sdram/M1_A10"
	6802	Ne 263 "/sdram/M1_A10"
6798	6803	Po 295 177
6799	6804	$EndPAD
6800	6805	$PAD
6801	6806	Sh "6" R 118 157 0 0 900
6802	6807	Dr 0 0 0
6803	6808	At SMD N 00440001
6804		Ne 144 "/fpga2/M1_BA1"
	6809	Ne 134 "/fpga2/M1_BA1"
6805	6810	Po 98 177
6806	6811	$EndPAD
6807	6812	$PAD
6808	6813	Sh "7" R 118 157 0 0 900
6809	6814	Dr 0 0 0
6810	6815	At SMD N 00440001
6811		Ne 269 "/sdram/M1_BA0"
	6816	Ne 270 "/sdram/M1_BA0"
6812	6817	Po -98 177
6813	6818	$EndPAD
6814	6819	$PAD
6815	6820	Sh "8" R 118 157 0 0 900
6816	6821	Dr 0 0 0
6817	6822	At SMD N 00440001
6818		Ne 277 "/sdram/M1_RAS#"
	6823	Ne 152 "/fpga2/M1_RAS#"
6819	6824	Po -295 177
6820	6825	$EndPAD
6821	6826	$EndMODULE R_PACK4-0402
...	...
6834	6839	Sh "1" R 118 157 0 0 2700
6835	6840	Dr 0 0 0
6836	6841	At SMD N 00440001
6837		Ne 201 "/fpga2/R_M1_A0"
	6842	Ne 192 "/fpga2/R_M1_A0"
6838	6843	Po -295 -177
6839	6844	$EndPAD
6840	6845	$PAD
6841	6846	Sh "2" R 118 157 0 0 2700
6842	6847	Dr 0 0 0
6843	6848	At SMD N 00440001
6844		Ne 202 "/fpga2/R_M1_A1"
	6849	Ne 193 "/fpga2/R_M1_A1"
6845	6850	Po -98 -177
6846	6851	$EndPAD
6847	6852	$PAD
6848	6853	Sh "3" R 118 157 0 0 2700
6849	6854	Dr 0 0 0
6850	6855	At SMD N 00440001
6851		Ne 206 "/fpga2/R_M1_A2"
	6856	Ne 197 "/fpga2/R_M1_A2"
6852	6857	Po 98 -177
6853	6858	$EndPAD
6854	6859	$PAD
6855	6860	Sh "4" R 118 157 0 0 2700
6856	6861	Dr 0 0 0
6857	6862	At SMD N 00440001
6858		Ne 207 "/fpga2/R_M1_A3"
	6863	Ne 198 "/fpga2/R_M1_A3"
6859	6864	Po 295 -177
6860	6865	$EndPAD
6861	6866	$PAD
...	...
6869	6874	Sh "6" R 118 157 0 0 900
6870	6875	Dr 0 0 0
6871	6876	At SMD N 00440001
6872		Ne 139 "/fpga2/M1_A2"
	6877	Ne 265 "/sdram/M1_A2"
6873	6878	Po 98 177
6874	6879	$EndPAD
6875	6880	$PAD
6876	6881	Sh "7" R 118 157 0 0 900
6877	6882	Dr 0 0 0
6878	6883	At SMD N 00440001
6879		Ne 263 "/sdram/M1_A1"
	6884	Ne 129 "/fpga2/M1_A1"
6880	6885	Po -98 177
6881	6886	$EndPAD
6882	6887	$PAD
6883	6888	Sh "8" R 118 157 0 0 900
6884	6889	Dr 0 0 0
6885	6890	At SMD N 00440001
6886		Ne 137 "/fpga2/M1_A0"
	6891	Ne 128 "/fpga2/M1_A0"
6887	6892	Po -295 177
6888	6893	$EndPAD
6889	6894	$EndMODULE R_PACK4-0402
...	...
6939	6944	Sh "2" R 157 236 0 0 1800
6940	6945	Dr 0 0 0
6941	6946	At SMD N 00440001
6942		Ne 16 "/ether/ETH_PLL1.8V"
	6947	Ne 13 "/ether/ETH_PLL1.8V"
6943	6948	Po 176 0
6944	6949	$EndPAD
6945	6950	$EndMODULE 0402
...	...
7141	7146	Sh "1" R 200 450 0 0 2700
7142	7147	Dr 0 0 0
7143	7148	At SMD N 00888000
7144		Ne 102 "/fpga1/PROG_CSO"
	7149	Ne 104 "/fpga1/PROG_CSO"
7145	7150	Po -750 1050
7146	7151	$EndPAD
7147	7152	$PAD
7148	7153	Sh "7" R 200 450 0 0 2700
7149	7154	Dr 0 0 0
7150	7155	At SMD N 00888000
7151		Ne 106 "/fpga1/PROG_MISO3"
	7156	Ne 108 "/fpga1/PROG_MISO3"
7152	7157	Po -250 -1050
7153	7158	$EndPAD
7154	7159	$PAD
7155	7160	Sh "6" R 200 450 0 0 2700
7156	7161	Dr 0 0 0
7157	7162	At SMD N 00888000
7158		Ne 101 "/fpga1/PROG_CCLK"
	7163	Ne 103 "/fpga1/PROG_CCLK"
7159	7164	Po 250 -1050
7160	7165	$EndPAD
7161	7166	$PAD
7162	7167	Sh "5" R 200 450 0 0 2700
7163	7168	Dr 0 0 0
7164	7169	At SMD N 00888000
7165		Ne 103 "/fpga1/PROG_MISO0"
	7170	Ne 105 "/fpga1/PROG_MISO0"
7166	7171	Po 750 -1050
7167	7172	$EndPAD
7168	7173	$PAD
7169	7174	Sh "2" R 200 450 0 0 2700
7170	7175	Dr 0 0 0
7171	7176	At SMD N 00888000
7172		Ne 104 "/fpga1/PROG_MISO1"
	7177	Ne 106 "/fpga1/PROG_MISO1"
7173	7178	Po -250 1050
7174	7179	$EndPAD
7175	7180	$PAD
7176	7181	Sh "3" R 200 450 0 0 2700
7177	7182	Dr 0 0 0
7178	7183	At SMD N 00888000
7179		Ne 105 "/fpga1/PROG_MISO2"
	7184	Ne 107 "/fpga1/PROG_MISO2"
7180	7185	Po 250 1050
7181	7186	$EndPAD
7182	7187	$PAD
...	...
9245	9250	Sh "1" R 157 236 0 0 0
9246	9251	Dr 0 0 0
9247	9252	At SMD N 00440001
9248		Ne 16 "/ether/ETH_PLL1.8V"
	9253	Ne 13 "/ether/ETH_PLL1.8V"
9249	9254	Po -176 0
9250	9255	$EndPAD
9251	9256	$PAD
...	...
9329	9334	Sh "1" R 157 236 0 0 1800
9330	9335	Dr 0 0 0
9331	9336	At SMD N 00440001
9332		Ne 15 "/ether/ETH_MDIO"
	9337	Ne 12 "/ether/ETH_MDIO"
9333	9338	Po -176 0
9334	9339	$EndPAD
9335	9340	$PAD
...	...
9357	9362	Sh "1" R 157 236 0 0 900
9358	9363	Dr 0 0 0
9359	9364	At SMD N 00440001
9360		Ne 295 "N-000125"
	9365	Ne 295 "N-000126"
9361	9366	Po -176 0
9362	9367	$EndPAD
9363	9368	$PAD
...	...
9392	9397	Sh "2" R 157 236 0 0 1800
9393	9398	Dr 0 0 0
9394	9399	At SMD N 00440001
9395		Ne 25 "/ether/MAG_TX+"
	9400	Ne 21 "/ether/MAG_TX+"
9396	9401	Po 176 0
9397	9402	$EndPAD
9398	9403	$EndMODULE 0402
...	...
9420	9425	Sh "2" R 157 236 0 0 1800
9421	9426	Dr 0 0 0
9422	9427	At SMD N 00440001
9423		Ne 26 "/ether/MAG_TX-"
	9428	Ne 22 "/ether/MAG_TX-"
9424	9429	Po 176 0
9425	9430	$EndPAD
9426	9431	$EndMODULE 0402
...	...
9448	9453	Sh "2" R 157 236 0 0 0
9449	9454	Dr 0 0 0
9450	9455	At SMD N 00440001
9451		Ne 22 "/ether/MAG_RX+"
	9456	Ne 18 "/ether/MAG_RX+"
9452	9457	Po 176 0
9453	9458	$EndPAD
9454	9459	$EndMODULE 0402
...	...
9476	9481	Sh "2" R 157 236 0 0 0
9477	9482	Dr 0 0 0
9478	9483	At SMD N 00440001
9479		Ne 23 "/ether/MAG_RX-"
	9484	Ne 19 "/ether/MAG_RX-"
9480	9485	Po 176 0
9481	9486	$EndPAD
9482	9487	$EndMODULE 0402
...	...
9497	9502	Sh "1" R 157 236 0 0 1800
9498	9503	Dr 0 0 0
9499	9504	At SMD N 00440001
9500		Ne 294 "N-000121"
	9505	Ne 293 "N-000121"
9501	9506	Po -176 0
9502	9507	$EndPAD
9503	9508	$PAD
9504	9509	Sh "2" R 157 236 0 0 1800
9505	9510	Dr 0 0 0
9506	9511	At SMD N 00440001
9507		Ne 12 "/ether/ETH_LED0"
	9512	Ne 10 "/ether/ETH_LED0"
9508	9513	Po 176 0
9509	9514	$EndPAD
9510	9515	$EndMODULE 0402
...	...
9525	9530	Sh "1" R 157 236 0 0 0
9526	9531	Dr 0 0 0
9527	9532	At SMD N 00440001
9528		Ne 293 "N-000120"
	9533	Ne 294 "N-000124"
9529	9534	Po -176 0
9530	9535	$EndPAD
9531	9536	$PAD
9532	9537	Sh "2" R 157 236 0 0 0
9533	9538	Dr 0 0 0
9534	9539	At SMD N 00440001
9535		Ne 13 "/ether/ETH_LED1"
	9540	Ne 11 "/ether/ETH_LED1"
9536	9541	Po 176 0
9537	9542	$EndPAD
9538	9543	$EndMODULE 0402
...	...
9561	9566	Sh "2" R 138 275 0 0 900
9562	9567	Dr 0 0 0
9563	9568	At SMD N 00888000
9564		Ne 124 "/fpga2/M0_DQ0"
	9569	Ne 248 "/sdram/M0_DQ0"
9565	9570	Po -3838 2176
9566	9571	$EndPAD
9567	9572	$PAD
...	...
9575	9580	Sh "4" R 138 275 0 0 900
9576	9581	Dr 0 0 0
9577	9582	At SMD N 00888000
9578		Ne 125 "/fpga2/M0_DQ1"
	9583	Ne 120 "/fpga2/M0_DQ1"
9579	9584	Po -3326 2176
9580	9585	$EndPAD
9581	9586	$PAD
9582	9587	Sh "5" R 137 275 0 0 900
9583	9588	Dr 0 0 0
9584	9589	At SMD N 00888000
9585		Ne 129 "/fpga2/M0_DQ2"
	9590	Ne 122 "/fpga2/M0_DQ2"
9586	9591	Po -3070 2176
9587	9592	$EndPAD
9588	9593	$PAD
...	...
9596	9601	Sh "7" R 137 275 0 0 900
9597	9602	Dr 0 0 0
9598	9603	At SMD N 00888000
9599		Ne 130 "/fpga2/M0_DQ3"
	9604	Ne 123 "/fpga2/M0_DQ3"
9600	9605	Po -2558 2176
9601	9606	$EndPAD
9602	9607	$PAD
9603	9608	Sh "8" R 138 275 0 0 900
9604	9609	Dr 0 0 0
9605	9610	At SMD N 00888000
9606		Ne 256 "/sdram/M0_DQ4"
	9611	Ne 254 "/sdram/M0_DQ4"
9607	9612	Po -2303 2176
9608	9613	$EndPAD
9609	9614	$PAD
...	...
9617	9622	Sh "10" R 138 275 0 0 900
9618	9623	Dr 0 0 0
9619	9624	At SMD N 00888000
9620		Ne 257 "/sdram/M0_DQ5"
	9625	Ne 124 "/fpga2/M0_DQ5"
9621	9626	Po -1791 2176
9622	9627	$EndPAD
9623	9628	$PAD
9624	9629	Sh "11" R 138 275 0 0 900
9625	9630	Dr 0 0 0
9626	9631	At SMD N 00888000
9627		Ne 131 "/fpga2/M0_DQ6"
	9632	Ne 255 "/sdram/M0_DQ6"
9628	9633	Po -1535 2176
9629	9634	$EndPAD
9630	9635	$PAD
...	...
9638	9643	Sh "13" R 138 275 0 0 900
9639	9644	Dr 0 0 0
9640	9645	At SMD N 00888000
9641		Ne 132 "/fpga2/M0_DQ7"
	9646	Ne 256 "/sdram/M0_DQ7"
9642	9647	Po -1023 2176
9643	9648	$EndPAD
9644	9649	$PAD
...	...
9659	9664	Sh "16" R 137 275 0 0 900
9660	9665	Dr 0 0 0
9661	9666	At SMD N 00888000
9662		Ne 135 "/fpga2/M0_LDQS"
	9667	Ne 257 "/sdram/M0_LDQS"
9663	9668	Po -255 2176
9664	9669	$EndPAD
9665	9670	$PAD
...	...
9687	9692	Sh "20" R 138 275 0 0 900
9688	9693	Dr 0 0 0
9689	9694	At SMD N 00888000
9690		Ne 134 "/fpga2/M0_LDM"
	9695	Ne 127 "/fpga2/M0_LDM"
9691	9696	Po 767 2176
9692	9697	$EndPAD
9693	9698	$PAD
...	...
9701	9706	Sh "22" R 138 275 0 0 900
9702	9707	Dr 0 0 0
9703	9708	At SMD N 00888000
9704		Ne 122 "/fpga2/M0_CAS#"
	9709	Ne 244 "/sdram/M0_CAS#"
9705	9710	Po 1279 2176
9706	9711	$EndPAD
9707	9712	$PAD
9708	9713	Sh "23" R 138 275 0 0 900
9709	9714	Dr 0 0 0
9710	9715	At SMD N 00888000
9711		Ne 259 "/sdram/M0_RAS#"
	9716	Ne 258 "/sdram/M0_RAS#"
9712	9717	Po 1535 2176
9713	9718	$EndPAD
9714	9719	$PAD
...	...
9729	9734	Sh "26" R 137 275 0 0 900
9730	9735	Dr 0 0 0
9731	9736	At SMD N 00888000
9732		Ne 121 "/fpga2/M0_BA0"
	9737	Ne 242 "/sdram/M0_BA0"
9733	9738	Po 2302 2176
9734	9739	$EndPAD
9735	9740	$PAD
9736	9741	Sh "27" R 137 275 0 0 900
9737	9742	Dr 0 0 0
9738	9743	At SMD N 00888000
9739		Ne 250 "/sdram/M0_BA1"
	9744	Ne 243 "/sdram/M0_BA1"
9740	9745	Po 2558 2176
9741	9746	$EndPAD
9742	9747	$PAD
...	...
9757	9762	Sh "30" R 138 275 0 0 900
9758	9763	Dr 0 0 0
9759	9764	At SMD N 00888000
9760		Ne 246 "/sdram/M0_A1"
	9765	Ne 237 "/sdram/M0_A1"
9761	9766	Po 3326 2176
9762	9767	$EndPAD
9763	9768	$PAD
9764	9769	Sh "31" R 138 275 0 0 900
9765	9770	Dr 0 0 0
9766	9771	At SMD N 00888000
9767		Ne 115 "/fpga2/M0_A2"
	9772	Ne 116 "/fpga2/M0_A2"
9768	9773	Po 3582 2176
9769	9774	$EndPAD
9770	9775	$PAD
9771	9776	Sh "32" R 138 275 0 0 900
9772	9777	Dr 0 0 0
9773	9778	At SMD N 00888000
9774		Ne 248 "/sdram/M0_A3"
	9779	Ne 238 "/sdram/M0_A3"
9775	9780	Po 3838 2176
9776	9781	$EndPAD
9777	9782	$PAD
...	...
9792	9797	Sh "35" R 138 275 0 0 900
9793	9798	Dr 0 0 0
9794	9799	At SMD N 00888000
9795		Ne 116 "/fpga2/M0_A4"
	9800	Ne 239 "/sdram/M0_A4"
9796	9801	Po 3838 -2176
9797	9802	$EndPAD
9798	9803	$PAD
...	...
9806	9811	Sh "37" R 138 275 0 0 900
9807	9812	Dr 0 0 0
9808	9813	At SMD N 00888000
9809		Ne 249 "/sdram/M0_A6"
	9814	Ne 240 "/sdram/M0_A6"
9810	9815	Po 3326 -2176
9811	9816	$EndPAD
9812	9817	$PAD
...	...
9820	9825	Sh "39" R 137 275 0 0 900
9821	9826	Dr 0 0 0
9822	9827	At SMD N 00888000
9823		Ne 119 "/fpga2/M0_A8"
	9828	Ne 241 "/sdram/M0_A8"
9824	9829	Po 2814 -2176
9825	9830	$EndPAD
9826	9831	$PAD
9827	9832	Sh "40" R 137 275 0 0 900
9828	9833	Dr 0 0 0
9829	9834	At SMD N 00888000
9830		Ne 120 "/fpga2/M0_A9"
	9835	Ne 119 "/fpga2/M0_A9"
9831	9836	Po 2558 -2176
9832	9837	$EndPAD
9833	9838	$PAD
9834	9839	Sh "41" R 138 275 0 0 900
9835	9840	Dr 0 0 0
9836	9841	At SMD N 00888000
9837		Ne 247 "/sdram/M0_A11"
	9842	Ne 114 "/fpga2/M0_A11"
9838	9843	Po 2303 -2176
9839	9844	$EndPAD
9840	9845	$PAD
9841	9846	Sh "42" R 138 275 0 0 900
9842	9847	Dr 0 0 0
9843	9848	At SMD N 00888000
9844		Ne 114 "/fpga2/M0_A12"
	9849	Ne 115 "/fpga2/M0_A12"
9845	9850	Po 2047 -2176
9846	9851	$EndPAD
9847	9852	$PAD
...	...
9855	9860	Sh "44" R 138 275 0 0 900
9856	9861	Dr 0 0 0
9857	9862	At SMD N 00888000
9858		Ne 252 "/sdram/M0_CLK#"
	9863	Ne 247 "/sdram/M0_CLK#"
9859	9864	Po 1535 -2176
9860	9865	$EndPAD
9861	9866	$PAD
9862	9867	Sh "45" R 138 275 0 0 900
9863	9868	Dr 0 0 0
9864	9869	At SMD N 00888000
9865		Ne 251 "/sdram/M0_CKE"
	9870	Ne 245 "/sdram/M0_CKE"
9866	9871	Po 1279 -2176
9867	9872	$EndPAD
9868	9873	$PAD
9869	9874	Sh "46" R 138 275 0 0 900
9870	9875	Dr 0 0 0
9871	9876	At SMD N 00888000
9872		Ne 123 "/fpga2/M0_CLK"
	9877	Ne 246 "/sdram/M0_CLK"
9873	9878	Po 1023 -2176
9874	9879	$EndPAD
9875	9880	$PAD
9876	9881	Sh "47" R 138 275 0 0 900
9877	9882	Dr 0 0 0
9878	9883	At SMD N 00888000
9879		Ne 136 "/fpga2/M0_UDM"
	9884	Ne 259 "/sdram/M0_UDM"
9880	9885	Po 767 -2176
9881	9886	$EndPAD
9882	9887	$PAD
...	...
9925	9930	Sh "54" R 138 275 0 0 900
9926	9931	Dr 0 0 0
9927	9932	At SMD N 00888000
9928		Ne 258 "/sdram/M0_DQ8"
	9933	Ne 125 "/fpga2/M0_DQ8"
9929	9934	Po -1023 -2176
9930	9935	$EndPAD
9931	9936	$PAD
...	...
9939	9944	Sh "56" R 138 275 0 0 900
9940	9945	Dr 0 0 0
9941	9946	At SMD N 00888000
9942		Ne 133 "/fpga2/M0_DQ9"
	9947	Ne 126 "/fpga2/M0_DQ9"
9943	9948	Po -1535 -2176
9944	9949	$EndPAD
9945	9950	$PAD
9946	9951	Sh "57" R 138 275 0 0 900
9947	9952	Dr 0 0 0
9948	9953	At SMD N 00888000
9949		Ne 126 "/fpga2/M0_DQ10"
	9954	Ne 249 "/sdram/M0_DQ10"
9950	9955	Po -1791 -2176
9951	9956	$EndPAD
9952	9957	$PAD
...	...
9960	9965	Sh "59" R 138 275 0 0 900
9961	9966	Dr 0 0 0
9962	9967	At SMD N 00888000
9963		Ne 127 "/fpga2/M0_DQ11"
	9968	Ne 121 "/fpga2/M0_DQ11"
9964	9969	Po -2303 -2176
9965	9970	$EndPAD
9966	9971	$PAD
9967	9972	Sh "60" R 137 275 0 0 900
9968	9973	Dr 0 0 0
9969	9974	At SMD N 00888000
9970		Ne 253 "/sdram/M0_DQ12"
	9975	Ne 250 "/sdram/M0_DQ12"
9971	9976	Po -2558 -2176
9972	9977	$EndPAD
9973	9978	$PAD
...	...
9981	9986	Sh "62" R 138 275 0 0 900
9982	9987	Dr 0 0 0
9983	9988	At SMD N 00888000
9984		Ne 254 "/sdram/M0_DQ13"
	9989	Ne 251 "/sdram/M0_DQ13"
9985	9990	Po -3070 -2176
9986	9991	$EndPAD
9987	9992	$PAD
9988	9993	Sh "63" R 138 275 0 0 900
9989	9994	Dr 0 0 0
9990	9995	At SMD N 00888000
9991		Ne 255 "/sdram/M0_DQ14"
	9996	Ne 252 "/sdram/M0_DQ14"
9992	9997	Po -3326 -2176
9993	9998	$EndPAD
9994	9999	$PAD
...	...
10002	10007	Sh "65" R 138 275 0 0 900
10003	10008	Dr 0 0 0
10004	10009	At SMD N 00888000
10005		Ne 128 "/fpga2/M0_DQ15"
	10010	Ne 253 "/sdram/M0_DQ15"
10006	10011	Po -3838 -2176
10007	10012	$EndPAD
10008	10013	$PAD
...	...
10038	10043	Sh "2" R 138 275 0 0 900
10039	10044	Dr 0 0 0
10040	10045	At SMD N 00888000
10041		Ne 149 "/fpga2/M1_DQ0"
	10046	Ne 139 "/fpga2/M1_DQ0"
10042	10047	Po -3838 2176
10043	10048	$EndPAD
10044	10049	$PAD
...	...
10052	10057	Sh "4" R 138 275 0 0 900
10053	10058	Dr 0 0 0
10054	10059	At SMD N 00888000
10055		Ne 271 "/sdram/M1_DQ1"
	10060	Ne 272 "/sdram/M1_DQ1"
10056	10061	Po -3326 2176
10057	10062	$EndPAD
10058	10063	$PAD
10059	10064	Sh "5" R 137 275 0 0 900
10060	10065	Dr 0 0 0
10061	10066	At SMD N 00888000
10062		Ne 154 "/fpga2/M1_DQ2"
	10067	Ne 275 "/sdram/M1_DQ2"
10063	10068	Po -3070 2176
10064	10069	$EndPAD
10065	10070	$PAD
...	...
10073	10078	Sh "7" R 137 275 0 0 900
10074	10079	Dr 0 0 0
10075	10080	At SMD N 00888000
10076		Ne 155 "/fpga2/M1_DQ3"
	10081	Ne 144 "/fpga2/M1_DQ3"
10077	10082	Po -2558 2176
10078	10083	$EndPAD
10079	10084	$PAD
10080	10085	Sh "8" R 138 275 0 0 900
10081	10086	Dr 0 0 0
10082	10087	At SMD N 00888000
10083		Ne 156 "/fpga2/M1_DQ4"
	10088	Ne 145 "/fpga2/M1_DQ4"
10084	10089	Po -2303 2176
10085	10090	$EndPAD
10086	10091	$PAD
...	...
10094	10099	Sh "10" R 138 275 0 0 900
10095	10100	Dr 0 0 0
10096	10101	At SMD N 00888000
10097		Ne 274 "/sdram/M1_DQ5"
	10102	Ne 146 "/fpga2/M1_DQ5"
10098	10103	Po -1791 2176
10099	10104	$EndPAD
10100	10105	$PAD
10101	10106	Sh "11" R 138 275 0 0 900
10102	10107	Dr 0 0 0
10103	10108	At SMD N 00888000
10104		Ne 275 "/sdram/M1_DQ6"
	10109	Ne 147 "/fpga2/M1_DQ6"
10105	10110	Po -1535 2176
10106	10111	$EndPAD
10107	10112	$PAD
...	...
10115	10120	Sh "13" R 138 275 0 0 900
10116	10121	Dr 0 0 0
10117	10122	At SMD N 00888000
10118		Ne 157 "/fpga2/M1_DQ7"
	10123	Ne 148 "/fpga2/M1_DQ7"
10119	10124	Po -1023 2176
10120	10125	$EndPAD
10121	10126	$PAD
...	...
10164	10169	Sh "20" R 138 275 0 0 900
10165	10170	Dr 0 0 0
10166	10171	At SMD N 00888000
10167		Ne 160 "/fpga2/M1_LDM"
	10172	Ne 151 "/fpga2/M1_LDM"
10168	10173	Po 767 2176
10169	10174	$EndPAD
10170	10175	$PAD
...	...
10178	10183	Sh "22" R 138 275 0 0 900
10179	10184	Dr 0 0 0
10180	10185	At SMD N 00888000
10181		Ne 270 "/sdram/M1_CAS#"
	10186	Ne 135 "/fpga2/M1_CAS#"
10182	10187	Po 1279 2176
10183	10188	$EndPAD
10184	10189	$PAD
10185	10190	Sh "23" R 138 275 0 0 900
10186	10191	Dr 0 0 0
10187	10192	At SMD N 00888000
10188		Ne 277 "/sdram/M1_RAS#"
	10193	Ne 152 "/fpga2/M1_RAS#"
10189	10194	Po 1535 2176
10190	10195	$EndPAD
10191	10196	$PAD
10192	10197	Sh "24" R 138 275 0 0 900
10193	10198	Dr 0 0 0
10194	10199	At SMD N 00888000
10195		Ne 148 "/fpga2/M1_CS#"
	10200	Ne 138 "/fpga2/M1_CS#"
10196	10201	Po 1791 2176
10197	10202	$EndPAD
10198	10203	$PAD
...	...
10206	10211	Sh "26" R 137 275 0 0 900
10207	10212	Dr 0 0 0
10208	10213	At SMD N 00888000
10209		Ne 269 "/sdram/M1_BA0"
	10214	Ne 270 "/sdram/M1_BA0"
10210	10215	Po 2302 2176
10211	10216	$EndPAD
10212	10217	$PAD
10213	10218	Sh "27" R 137 275 0 0 900
10214	10219	Dr 0 0 0
10215	10220	At SMD N 00888000
10216		Ne 144 "/fpga2/M1_BA1"
	10221	Ne 134 "/fpga2/M1_BA1"
10217	10222	Po 2558 2176
10218	10223	$EndPAD
10219	10224	$PAD
10220	10225	Sh "28" R 137 275 0 0 900
10221	10226	Dr 0 0 0
10222	10227	At SMD N 00888000
10223		Ne 264 "/sdram/M1_A10"
	10228	Ne 263 "/sdram/M1_A10"
10224	10229	Po 2814 2176
10225	10230	$EndPAD
10226	10231	$PAD
10227	10232	Sh "29" R 138 275 0 0 900
10228	10233	Dr 0 0 0
10229	10234	At SMD N 00888000
10230		Ne 137 "/fpga2/M1_A0"
	10235	Ne 128 "/fpga2/M1_A0"
10231	10236	Po 3070 2176
10232	10237	$EndPAD
10233	10238	$PAD
10234	10239	Sh "30" R 138 275 0 0 900
10235	10240	Dr 0 0 0
10236	10241	At SMD N 00888000
10237		Ne 263 "/sdram/M1_A1"
	10242	Ne 129 "/fpga2/M1_A1"
10238	10243	Po 3326 2176
10239	10244	$EndPAD
10240	10245	$PAD
10241	10246	Sh "31" R 138 275 0 0 900
10242	10247	Dr 0 0 0
10243	10248	At SMD N 00888000
10244		Ne 139 "/fpga2/M1_A2"
	10249	Ne 265 "/sdram/M1_A2"
10245	10250	Po 3582 2176
10246	10251	$EndPAD
10247	10252	$PAD
...	...
10276	10281	Sh "36" R 138 275 0 0 900
10277	10282	Dr 0 0 0
10278	10283	At SMD N 00888000
10279		Ne 268 "/sdram/M1_A5"
	10284	Ne 131 "/fpga2/M1_A5"
10280	10285	Po 3582 -2176
10281	10286	$EndPAD
10282	10287	$PAD
10283	10288	Sh "37" R 138 275 0 0 900
10284	10289	Dr 0 0 0
10285	10290	At SMD N 00888000
10286		Ne 140 "/fpga2/M1_A6"
	10291	Ne 132 "/fpga2/M1_A6"
10287	10292	Po 3326 -2176
10288	10293	$EndPAD
10289	10294	$PAD
10290	10295	Sh "38" R 138 275 0 0 900
10291	10296	Dr 0 0 0
10292	10297	At SMD N 00888000
10293		Ne 141 "/fpga2/M1_A7"
	10298	Ne 268 "/sdram/M1_A7"
10294	10299	Po 3070 -2176
10295	10300	$EndPAD
10296	10301	$PAD
10297	10302	Sh "39" R 137 275 0 0 900
10298	10303	Dr 0 0 0
10299	10304	At SMD N 00888000
10300		Ne 142 "/fpga2/M1_A8"
	10305	Ne 133 "/fpga2/M1_A8"
10301	10306	Po 2814 -2176
10302	10307	$EndPAD
10303	10308	$PAD
10304	10309	Sh "40" R 137 275 0 0 900
10305	10310	Dr 0 0 0
10306	10311	At SMD N 00888000
10307		Ne 143 "/fpga2/M1_A9"
	10312	Ne 269 "/sdram/M1_A9"
10308	10313	Po 2558 -2176
10309	10314	$EndPAD
10310	10315	$PAD
10311	10316	Sh "41" R 138 275 0 0 900
10312	10317	Dr 0 0 0
10313	10318	At SMD N 00888000
10314		Ne 138 "/fpga2/M1_A11"
	10319	Ne 264 "/sdram/M1_A11"
10315	10320	Po 2303 -2176
10316	10321	$EndPAD
10317	10322	$PAD
10318	10323	Sh "42" R 138 275 0 0 900
10319	10324	Dr 0 0 0
10320	10325	At SMD N 00888000
10321		Ne 265 "/sdram/M1_A12"
	10326	Ne 130 "/fpga2/M1_A12"
10322	10327	Po 2047 -2176
10323	10328	$EndPAD
10324	10329	$PAD
...	...
10332	10337	Sh "44" R 138 275 0 0 900
10333	10338	Dr 0 0 0
10334	10339	At SMD N 00888000
10335		Ne 147 "/fpga2/M1_CLK#"
	10340	Ne 137 "/fpga2/M1_CLK#"
10336	10341	Po 1535 -2176
10337	10342	$EndPAD
10338	10343	$PAD
10339	10344	Sh "45" R 138 275 0 0 900
10340	10345	Dr 0 0 0
10341	10346	At SMD N 00888000
10342		Ne 145 "/fpga2/M1_CKE"
	10347	Ne 271 "/sdram/M1_CKE"
10343	10348	Po 1279 -2176
10344	10349	$EndPAD
10345	10350	$PAD
10346	10351	Sh "46" R 138 275 0 0 900
10347	10352	Dr 0 0 0
10348	10353	At SMD N 00888000
10349		Ne 146 "/fpga2/M1_CLK"
	10354	Ne 136 "/fpga2/M1_CLK"
10350	10355	Po 1023 -2176
10351	10356	$EndPAD
10352	10357	$PAD
10353	10358	Sh "47" R 138 275 0 0 900
10354	10359	Dr 0 0 0
10355	10360	At SMD N 00888000
10356		Ne 278 "/sdram/M1_UDM"
	10361	Ne 277 "/sdram/M1_UDM"
10357	10362	Po 767 -2176
10358	10363	$EndPAD
10359	10364	$PAD
...	...
10381	10386	Sh "51" R 137 275 0 0 900
10382	10387	Dr 0 0 0
10383	10388	At SMD N 00888000
10384		Ne 161 "/fpga2/M1_UDQS"
	10389	Ne 278 "/sdram/M1_UDQS"
10385	10390	Po -255 -2176
10386	10391	$EndPAD
10387	10392	$PAD
...	...
10402	10407	Sh "54" R 138 275 0 0 900
10403	10408	Dr 0 0 0
10404	10409	At SMD N 00888000
10405		Ne 158 "/fpga2/M1_DQ8"
	10410	Ne 149 "/fpga2/M1_DQ8"
10406	10411	Po -1023 -2176
10407	10412	$EndPAD
10408	10413	$PAD
...	...
10416	10421	Sh "56" R 138 275 0 0 900
10417	10422	Dr 0 0 0
10418	10423	At SMD N 00888000
10419		Ne 159 "/fpga2/M1_DQ9"
	10424	Ne 150 "/fpga2/M1_DQ9"
10420	10425	Po -1535 -2176
10421	10426	$EndPAD
10422	10427	$PAD
10423	10428	Sh "57" R 138 275 0 0 900
10424	10429	Dr 0 0 0
10425	10430	At SMD N 00888000
10426		Ne 150 "/fpga2/M1_DQ10"
	10431	Ne 273 "/sdram/M1_DQ10"
10427	10432	Po -1791 -2176
10428	10433	$EndPAD
10429	10434	$PAD
...	...
10437	10442	Sh "59" R 138 275 0 0 900
10438	10443	Dr 0 0 0
10439	10444	At SMD N 00888000
10440		Ne 151 "/fpga2/M1_DQ11"
	10445	Ne 274 "/sdram/M1_DQ11"
10441	10446	Po -2303 -2176
10442	10447	$EndPAD
10443	10448	$PAD
10444	10449	Sh "60" R 137 275 0 0 900
10445	10450	Dr 0 0 0
10446	10451	At SMD N 00888000
10447		Ne 272 "/sdram/M1_DQ12"
	10452	Ne 140 "/fpga2/M1_DQ12"
10448	10453	Po -2558 -2176
10449	10454	$EndPAD
10450	10455	$PAD
...	...
10458	10463	Sh "62" R 138 275 0 0 900
10459	10464	Dr 0 0 0
10460	10465	At SMD N 00888000
10461		Ne 273 "/sdram/M1_DQ13"
	10466	Ne 141 "/fpga2/M1_DQ13"
10462	10467	Po -3070 -2176
10463	10468	$EndPAD
10464	10469	$PAD
10465	10470	Sh "63" R 138 275 0 0 900
10466	10471	Dr 0 0 0
10467	10472	At SMD N 00888000
10468		Ne 152 "/fpga2/M1_DQ14"
	10473	Ne 142 "/fpga2/M1_DQ14"
10469	10474	Po -3326 -2176
10470	10475	$EndPAD
10471	10476	$PAD
...	...
10479	10484	Sh "65" R 138 275 0 0 900
10480	10485	Dr 0 0 0
10481	10486	At SMD N 00888000
10482		Ne 153 "/fpga2/M1_DQ15"
	10487	Ne 143 "/fpga2/M1_DQ15"
10483	10488	Po -3838 -2176
10484	10489	$EndPAD
10485	10490	$PAD
...	...
10506	10511	Sh "13" C 1646 1646 0 0 1800
10507	10512	Dr 1252 0 0
10508	10513	At STD N 0CC0FFFF
10509		Ne 24 "/ether/MAG_SHIELD"
	10514	Ne 20 "/ether/MAG_SHIELD"
10510	10515	Po 2250 0
10511	10516	$EndPAD
10512	10517	$PAD
10513	10518	Sh "13" C 984 984 0 0 1800
10514	10519	Dr 640 0 0
10515	10520	At STD N 0CC0FFFF
10516		Ne 24 "/ether/MAG_SHIELD"
	10521	Ne 20 "/ether/MAG_SHIELD"
10517	10522	Po 3100 -1200
10518	10523	$EndPAD
10519	10524	$PAD
10520	10525	Sh "14" C 1646 1646 0 0 1800
10521	10526	Dr 1252 0 0
10522	10527	At STD N 0CC0FFFF
10523		Ne 24 "/ether/MAG_SHIELD"
	10528	Ne 20 "/ether/MAG_SHIELD"
10524	10529	Po -2250 0
10525	10530	$EndPAD
10526	10531	$PAD
10527	10532	Sh "14" C 984 984 0 0 1800
10528	10533	Dr 640 0 0
10529	10534	At STD N 0CC0FFFF
10530		Ne 24 "/ether/MAG_SHIELD"
	10535	Ne 20 "/ether/MAG_SHIELD"
10531	10536	Po -3100 -1200
10532	10537	$EndPAD
10533	10538	$PAD
10534	10539	Sh "1" R 540 540 0 0 1800
10535	10540	Dr 350 0 0
10536	10541	At STD N 0CC0FFFF
10537		Ne 25 "/ether/MAG_TX+"
	10542	Ne 21 "/ether/MAG_TX+"
10538	10543	Po -1750 -2500
10539	10544	$EndPAD
10540	10545	$PAD
...	...
10555	10560	Sh "7" C 540 540 0 0 1800
10556	10561	Dr 350 0 0
10557	10562	At STD N 0CC0FFFF
10558		Ne 22 "/ether/MAG_RX+"
	10563	Ne 18 "/ether/MAG_RX+"
10559	10564	Po 1250 -2500
10560	10565	$EndPAD
10561	10566	$PAD
10562	10567	Sh "2" C 540 540 0 0 1800
10563	10568	Dr 350 0 0
10564	10569	At STD N 0CC0FFFF
10565		Ne 26 "/ether/MAG_TX-"
	10570	Ne 22 "/ether/MAG_TX-"
10566	10571	Po -1250 -3500
10567	10572	$EndPAD
10568	10573	$PAD
...	...
10583	10588	Sh "8" C 540 540 0 0 1800
10584	10589	Dr 350 0 0
10585	10590	At STD N 0CC0FFFF
10586		Ne 23 "/ether/MAG_RX-"
	10591	Ne 19 "/ether/MAG_RX-"
10587	10592	Po 1750 -3500
10588	10593	$EndPAD
10589	10594	$PAD
...	...
10597	10602	Sh "10" C 540 540 0 0 1800
10598	10603	Dr 350 0 0
10599	10604	At STD N 0CC0FFFF
10600		Ne 294 "N-000121"
	10605	Ne 293 "N-000121"
10601	10606	Po -1150 -5400
10602	10607	$EndPAD
10603	10608	$PAD
...	...
10611	10616	Sh "12" C 540 540 0 0 1800
10612	10617	Dr 350 0 0
10613	10618	At STD N 0CC0FFFF
10614		Ne 293 "N-000120"
	10619	Ne 294 "N-000124"
10615	10620	Po 2150 -5400
10616	10621	$EndPAD
10617	10622	$EndMODULE SD-48025
...	...
10636	10641	Sh "1" R 315 590 0 0 0
10637	10642	Dr 0 0 0
10638	10643	At STD N 00440001
10639		Ne 60 "/flash/SD_DAT2"
	10644	Ne 111 "/fpga1/SD_DAT2"
10640	10645	Po -1299 0
10641	10646	$EndPAD
10642	10647	$PAD
10643	10648	Sh "2" R 315 590 0 0 0
10644	10649	Dr 0 0 0
10645	10650	At STD N 00440001
10646		Ne 111 "/fpga1/SD_DAT3"
	10651	Ne 53 "/flash/SD_DAT3"
10647	10652	Po -866 0
10648	10653	$EndPAD
10649	10654	$PAD
10650	10655	Sh "3" R 315 590 0 0 0
10651	10656	Dr 0 0 0
10652	10657	At STD N 00440001
10653		Ne 108 "/fpga1/SD_CMD"
	10658	Ne 109 "/fpga1/SD_CMD"
10654	10659	Po -433 0
10655	10660	$EndPAD
10656	10661	$PAD
...	...
10664	10669	Sh "5" R 315 590 0 0 0
10665	10670	Dr 0 0 0
10666	10671	At STD N 00440001
10667		Ne 107 "/fpga1/SD_CLK"
	10672	Ne 51 "/flash/SD_CLK"
10668	10673	Po 433 0
10669	10674	$EndPAD
10670	10675	$PAD
...	...
10678	10683	Sh "7" R 315 590 0 0 0
10679	10684	Dr 0 0 0
10680	10685	At STD N 00440001
10681		Ne 109 "/fpga1/SD_DAT0"
	10686	Ne 110 "/fpga1/SD_DAT0"
10682	10687	Po 1299 0
10683	10688	$EndPAD
10684	10689	$PAD
10685	10690	Sh "8" R 315 590 0 0 0
10686	10691	Dr 0 0 0
10687	10692	At STD N 00440001
10688		Ne 110 "/fpga1/SD_DAT1"
	10693	Ne 52 "/flash/SD_DAT1"
10689	10694	Po 1732 0
10690	10695	$EndPAD
10691	10696	$PAD
...	...
10977	10982	Sh "6" R 100 600 0 0 900
10978	10983	Dr 0 0 0
10979	10984	At SMD N 00888000
10980		Ne 99 "/fpga1/NF_RNB"
	10985	Ne 49 "/flash/NF_RNB"
10981	10986	Po -1280 3850
10982	10987	$EndPAD
10983	10988	$PAD
10984	10989	Sh "7" R 100 600 0 0 900
10985	10990	Dr 0 0 0
10986	10991	At SMD N 00888000
10987		Ne 99 "/fpga1/NF_RNB"
	10992	Ne 49 "/flash/NF_RNB"
10988	10993	Po -1090 3850
10989	10994	$EndPAD
10990	10995	$PAD
10991	10996	Sh "8" R 100 600 0 0 900
10992	10997	Dr 0 0 0
10993	10998	At SMD N 00888000
10994		Ne 59 "/flash/NF_RE_N"
	10999	Ne 102 "/fpga1/NF_RE_N"
10995	11000	Po -890 3850
10996	11001	$EndPAD
10997	11002	$PAD
10998	11003	Sh "9" R 100 600 0 0 900
10999	11004	Dr 0 0 0
11000	11005	At SMD N 00888000
11001		Ne 53 "/flash/NF_CS1_N"
	11006	Ne 94 "/fpga1/NF_CS1_N"
11002	11007	Po -690 3850
11003	11008	$EndPAD
11004	11009	$PAD
...	...
11047	11052	Sh "16" R 100 600 0 0 900
11048	11053	Dr 0 0 0
11049	11054	At SMD N 00888000
11050		Ne 52 "/flash/NF_CLE"
	11055	Ne 93 "/fpga1/NF_CLE"
11051	11056	Po 690 3850
11052	11057	$EndPAD
11053	11058	$PAD
11054	11059	Sh "17" R 100 600 0 0 900
11055	11060	Dr 0 0 0
11056	11061	At SMD N 00888000
11057		Ne 51 "/flash/NF_ALE"
	11062	Ne 92 "/fpga1/NF_ALE"
11058	11063	Po 880 3850
11059	11064	$EndPAD
11060	11065	$PAD
11061	11066	Sh "18" R 100 600 0 0 900
11062	11067	Dr 0 0 0
11063	11068	At SMD N 00888000
11064		Ne 100 "/fpga1/NF_WE_N"
	11069	Ne 50 "/flash/NF_WE_N"
11065	11070	Po 1080 3850
11066	11071	$EndPAD
11067	11072	$PAD
...	...
11138	11143	Sh "29" R 100 600 0 0 900
11139	11144	Dr 0 0 0
11140	11145	At SMD N 00888000
11141		Ne 54 "/flash/NF_D0"
	11146	Ne 95 "/fpga1/NF_D0"
11142	11147	Po 1470 -3850
11143	11148	$EndPAD
11144	11149	$PAD
11145	11150	Sh "30" R 100 600 0 0 900
11146	11151	Dr 0 0 0
11147	11152	At SMD N 00888000
11148		Ne 55 "/flash/NF_D1"
	11153	Ne 96 "/fpga1/NF_D1"
11149	11154	Po 1280 -3850
11150	11155	$EndPAD
11151	11156	$PAD
11152	11157	Sh "31" R 100 600 0 0 900
11153	11158	Dr 0 0 0
11154	11159	At SMD N 00888000
11155		Ne 96 "/fpga1/NF_D2"
	11160	Ne 48 "/flash/NF_D2"
11156	11161	Po 1080 -3850
11157	11162	$EndPAD
11158	11163	$PAD
11159	11164	Sh "32" R 100 600 0 0 900
11160	11165	Dr 0 0 0
11161	11166	At SMD N 00888000
11162		Ne 56 "/flash/NF_D3"
	11167	Ne 97 "/fpga1/NF_D3"
11163	11168	Po 880 -3850
11164	11169	$EndPAD
11165	11170	$PAD
...	...
11222	11227	Sh "41" R 100 600 0 0 900
11223	11228	Dr 0 0 0
11224	11229	At SMD N 00888000
11225		Ne 97 "/fpga1/NF_D4"
	11230	Ne 98 "/fpga1/NF_D4"
11226	11231	Po -890 -3850
11227	11232	$EndPAD
11228	11233	$PAD
11229	11234	Sh "42" R 100 600 0 0 900
11230	11235	Dr 0 0 0
11231	11236	At SMD N 00888000
11232		Ne 57 "/flash/NF_D5"
	11237	Ne 99 "/fpga1/NF_D5"
11233	11238	Po -1090 -3850
11234	11239	$EndPAD
11235	11240	$PAD
11236	11241	Sh "43" R 100 600 0 0 900
11237	11242	Dr 0 0 0
11238	11243	At SMD N 00888000
11239		Ne 98 "/fpga1/NF_D6"
	11244	Ne 100 "/fpga1/NF_D6"
11240	11245	Po -1280 -3850
11241	11246	$EndPAD
11242	11247	$PAD
11243	11248	Sh "44" R 100 600 0 0 900
11244	11249	Dr 0 0 0
11245	11250	At SMD N 00888000
11246		Ne 58 "/flash/NF_D7"
	11251	Ne 101 "/fpga1/NF_D7"
11247	11252	Po -1480 -3850
11248	11253	$EndPAD
11249	11254	$PAD
...	...
11300	11305	Sh "11" R 315 99 0 0 900
11301	11306	Dr 0 0 0
11302	11307	At SMD N 00888000
11303		Ne 66 "/fpga1/ETH_RXER"
	11308	Ne 15 "/ether/ETH_RXER"
11304	11309	Po -1613 885
11305	11310	$EndPAD
11306	11311	$PAD
11307	11312	Sh "10" R 315 99 0 0 900
11308	11313	Dr 0 0 0
11309	11314	At SMD N 00888000
11310		Ne 17 "/ether/ETH_RXC"
	11315	Ne 58 "/fpga1/ETH_RXC"
11311	11316	Po -1613 688
11312	11317	$EndPAD
11313	11318	$PAD
11314	11319	Sh "9" R 315 99 0 0 900
11315	11320	Dr 0 0 0
11316	11321	At SMD N 00888000
11317		Ne 18 "/ether/ETH_RXDV"
	11322	Ne 14 "/ether/ETH_RXDV"
11318	11323	Po -1613 491
11319	11324	$EndPAD
11320	11325	$PAD
...	...
11335	11340	Sh "6" R 315 98 0 0 900
11336	11341	Dr 0 0 0
11337	11342	At SMD N 00888000
11338		Ne 62 "/fpga1/ETH_RXD0"
	11343	Ne 59 "/fpga1/ETH_RXD0"
11339	11344	Po -1613 -98
11340	11345	$EndPAD
11341	11346	$PAD
11342	11347	Sh "5" R 315 98 0 0 900
11343	11348	Dr 0 0 0
11344	11349	At SMD N 00888000
11345		Ne 63 "/fpga1/ETH_RXD1"
	11350	Ne 60 "/fpga1/ETH_RXD1"
11346	11351	Po -1613 -295
11347	11352	$EndPAD
11348	11353	$PAD
11349	11354	Sh "4" R 315 99 0 0 900
11350	11355	Dr 0 0 0
11351	11356	At SMD N 00888000
11352		Ne 64 "/fpga1/ETH_RXD2"
	11357	Ne 61 "/fpga1/ETH_RXD2"
11353	11358	Po -1613 -491
11354	11359	$EndPAD
11355	11360	$PAD
11356	11361	Sh "3" R 315 99 0 0 900
11357	11362	Dr 0 0 0
11358	11363	At SMD N 00888000
11359		Ne 65 "/fpga1/ETH_RXD3"
	11364	Ne 62 "/fpga1/ETH_RXD3"
11360	11365	Po -1613 -688
11361	11366	$EndPAD
11362	11367	$PAD
11363	11368	Sh "2" R 315 99 0 0 900
11364	11369	Dr 0 0 0
11365	11370	At SMD N 00888000
11366		Ne 14 "/ether/ETH_MDC"
	11371	Ne 56 "/fpga1/ETH_MDC"
11367	11372	Po -1613 -885
11368	11373	$EndPAD
11369	11374	$PAD
11370	11375	Sh "1" R 315 98 0 0 900
11371	11376	Dr 0 0 0
11372	11377	At SMD N 00888000
11373		Ne 15 "/ether/ETH_MDIO"
	11378	Ne 12 "/ether/ETH_MDIO"
11374	11379	Po -1613 -1082
11375	11380	$EndPAD
11376	11381	$PAD
11377	11382	Sh "48" R 98 315 0 0 900
11378	11383	Dr 0 0 0
11379	11384	At SMD N 00888000
11380		Ne 61 "/fpga1/ETH_RESET_N"
	11385	Ne 57 "/fpga1/ETH_RESET_N"
11381	11386	Po -1082 -1613
11382	11387	$EndPAD
11383	11388	$PAD
11384	11389	Sh "47" R 99 315 0 0 900
11385	11390	Dr 0 0 0
11386	11391	At SMD N 00888000
11387		Ne 16 "/ether/ETH_PLL1.8V"
	11392	Ne 13 "/ether/ETH_PLL1.8V"
11388	11393	Po -885 -1613
11389	11394	$EndPAD
11390	11395	$PAD
11391	11396	Sh "46" R 99 315 0 0 900
11392	11397	Dr 0 0 0
11393	11398	At SMD N 00888000
11394		Ne 8 "/ether/ETH_CLK"
	11399	Ne 54 "/fpga1/ETH_CLK"
11395	11400	Po -688 -1613
11396	11401	$EndPAD
11397	11402	$PAD
...	...
11426	11431	Sh "41" R 98 315 0 0 900
11427	11432	Dr 0 0 0
11428	11433	At SMD N 00888000
11429		Ne 25 "/ether/MAG_TX+"
	11434	Ne 21 "/ether/MAG_TX+"
11430	11435	Po 295 -1613
11431	11436	$EndPAD
11432	11437	$PAD
11433	11438	Sh "40" R 99 315 0 0 900
11434	11439	Dr 0 0 0
11435	11440	At SMD N 00888000
11436		Ne 26 "/ether/MAG_TX-"
	11441	Ne 22 "/ether/MAG_TX-"
11437	11442	Po 491 -1613
11438	11443	$EndPAD
11439	11444	$PAD
...	...
11454	11459	Sh "37" R 98 315 0 0 900
11455	11460	Dr 0 0 0
11456	11461	At SMD N 00888000
11457		Ne 295 "N-000125"
	11462	Ne 295 "N-000126"
11458	11463	Po 1082 -1613
11459	11464	$EndPAD
11460	11465	$PAD
11461	11466	Sh "25" R 315 98 0 0 900
11462	11467	Dr 0 0 0
11463	11468	At SMD N 00888000
11464		Ne 11 "/ether/ETH_INT"
	11469	Ne 9 "/ether/ETH_INT"
11465	11470	Po 1613 1082
11466	11471	$EndPAD
11467	11472	$PAD
11468	11473	Sh "26" R 315 99 0 0 900
11469	11474	Dr 0 0 0
11470	11475	At SMD N 00888000
11471		Ne 12 "/ether/ETH_LED0"
	11476	Ne 10 "/ether/ETH_LED0"
11472	11477	Po 1613 885
11473	11478	$EndPAD
11474	11479	$PAD
11475	11480	Sh "27" R 315 99 0 0 900
11476	11481	Dr 0 0 0
11477	11482	At SMD N 00888000
11478		Ne 13 "/ether/ETH_LED1"
	11483	Ne 11 "/ether/ETH_LED1"
11479	11484	Po 1613 688
11480	11485	$EndPAD
11481	11486	$PAD
...	...
11510	11515	Sh "32" R 315 98 0 0 900
11511	11516	Dr 0 0 0
11512	11517	At SMD N 00888000
11513		Ne 23 "/ether/MAG_RX-"
	11518	Ne 19 "/ether/MAG_RX-"
11514	11519	Po 1613 -295
11515	11520	$EndPAD
11516	11521	$PAD
11517	11522	Sh "33" R 315 99 0 0 900
11518	11523	Dr 0 0 0
11519	11524	At SMD N 00888000
11520		Ne 22 "/ether/MAG_RX+"
	11525	Ne 18 "/ether/MAG_RX+"
11521	11526	Po 1613 -491
11522	11527	$EndPAD
11523	11528	$PAD
...	...
11552	11557	Sh "14" R 99 315 0 0 900
11553	11558	Dr 0 0 0
11554	11559	At SMD N 00888000
11555		Ne 21 "/ether/ETH_TXER"
	11560	Ne 17 "/ether/ETH_TXER"
11556	11561	Po -885 1613
11557	11562	$EndPAD
11558	11563	$PAD
11559	11564	Sh "15" R 99 315 0 0 900
11560	11565	Dr 0 0 0
11561	11566	At SMD N 00888000
11562		Ne 67 "/fpga1/ETH_TXC"
	11567	Ne 63 "/fpga1/ETH_TXC"
11563	11568	Po -688 1613
11564	11569	$EndPAD
11565	11570	$PAD
11566	11571	Sh "16" R 99 315 0 0 900
11567	11572	Dr 0 0 0
11568	11573	At SMD N 00888000
11569		Ne 70 "/fpga1/ETH_TXEN"
	11574	Ne 67 "/fpga1/ETH_TXEN"
11570	11575	Po -491 1613
11571	11576	$EndPAD
11572	11577	$PAD
11573	11578	Sh "17" R 98 315 0 0 900
11574	11579	Dr 0 0 0
11575	11580	At SMD N 00888000
11576		Ne 19 "/ether/ETH_TXD0"
	11581	Ne 64 "/fpga1/ETH_TXD0"
11577	11582	Po -295 1613
11578	11583	$EndPAD
11579	11584	$PAD
11580	11585	Sh "18" R 98 315 0 0 900
11581	11586	Dr 0 0 0
11582	11587	At SMD N 00888000
11583		Ne 68 "/fpga1/ETH_TXD1"
	11588	Ne 65 "/fpga1/ETH_TXD1"
11584	11589	Po -98 1613
11585	11590	$EndPAD
11586	11591	$PAD
11587	11592	Sh "19" R 98 315 0 0 900
11588	11593	Dr 0 0 0
11589	11594	At SMD N 00888000
11590		Ne 69 "/fpga1/ETH_TXD2"
	11595	Ne 16 "/ether/ETH_TXD2"
11591	11596	Po 98 1613
11592	11597	$EndPAD
11593	11598	$PAD
11594	11599	Sh "20" R 98 315 0 0 900
11595	11600	Dr 0 0 0
11596	11601	At SMD N 00888000
11597		Ne 20 "/ether/ETH_TXD3"
	11602	Ne 66 "/fpga1/ETH_TXD3"
11598	11603	Po 295 1613
11599	11604	$EndPAD
11600	11605	$PAD
11601	11606	Sh "21" R 99 315 0 0 900
11602	11607	Dr 0 0 0
11603	11608	At SMD N 00888000
11604		Ne 9 "/ether/ETH_COL"
	11609	Ne 8 "/ether/ETH_COL"
11605	11610	Po 491 1613
11606	11611	$EndPAD
11607	11612	$PAD
11608	11613	Sh "22" R 99 315 0 0 900
11609	11614	Dr 0 0 0
11610	11615	At SMD N 00888000
11611		Ne 10 "/ether/ETH_CRS"
	11616	Ne 55 "/fpga1/ETH_CRS"
11612	11617	Po 688 1613
11613	11618	$EndPAD
11614	11619	$PAD
...	...
11706	11711	Sh "2" R 157 236 0 0 1800
11707	11712	Dr 0 0 0
11708	11713	At SMD N 00440001
11709		Ne 335 "N-000365"
	11714	Ne 335 "N-000366"
11710	11715	Po 176 0
11711	11716	$EndPAD
11712	11717	$EndMODULE 0402
...	...
11734	11739	Sh "2" R 157 236 0 0 900
11735	11740	Dr 0 0 0
11736	11741	At SMD N 00440001
11737		Ne 334 "N-000362"
	11742	Ne 334 "N-000363"
11738	11743	Po 176 0
11739	11744	$EndPAD
11740	11745	$EndMODULE 0402
...	...
11770	11775	Sh "1" R 98 157 0 0 0
11771	11776	Dr 0 0 0
11772	11777	At SMD N 00440001
11773		Ne 289 "/usb/USBD_SPD"
	11778	Ne 288 "/usb/USBD_SPD"
11774	11779	Po -295 491
11775	11780	$EndPAD
11776	11781	$PAD
...	...
11784	11789	Sh "2" R 98 157 0 0 0
11785	11790	Dr 0 0 0
11786	11791	At SMD N 00440001
11787		Ne 243 "/fpga2/USBD_RCV"
	11792	Ne 235 "/fpga2/USBD_RCV"
11788	11793	Po -98 491
11789	11794	$EndPAD
11790	11795	$PAD
...	...
11798	11803	Sh "3" R 98 157 0 0 0
11799	11804	Dr 0 0 0
11800	11805	At SMD N 00440001
11801		Ne 245 "/fpga2/USBD_VP"
	11806	Ne 236 "/fpga2/USBD_VP"
11802	11807	Po 98 491
11803	11808	$EndPAD
11804	11809	$PAD
11805	11810	Sh "9" R 98 157 0 0 0
11806	11811	Dr 0 0 0
11807	11812	At SMD N 00440001
11808		Ne 288 "/usb/USBD_OE_N"
	11813	Ne 234 "/fpga2/USBD_OE_N"
11809	11814	Po 295 -491
11810	11815	$EndPAD
11811	11816	$PAD
11812	11817	Sh "4" R 98 157 0 0 0
11813	11818	Dr 0 0 0
11814	11819	At SMD N 00440001
11815		Ne 244 "/fpga2/USBD_VM"
	11820	Ne 289 "/usb/USBD_VM"
11816	11821	Po 295 491
11817	11822	$EndPAD
11818	11823	$PAD
...	...
11918	11923	Sh "2" R 98 157 0 0 0
11919	11924	Dr 0 0 0
11920	11925	At SMD N 00440001
11921		Ne 241 "/fpga2/USBA_RCV"
	11926	Ne 232 "/fpga2/USBA_RCV"
11922	11927	Po -98 491
11923	11928	$EndPAD
11924	11929	$PAD
...	...
11932	11937	Sh "3" R 98 157 0 0 0
11933	11938	Dr 0 0 0
11934	11939	At SMD N 00440001
11935		Ne 242 "/fpga2/USBA_VP"
	11940	Ne 233 "/fpga2/USBA_VP"
11936	11941	Po 98 491
11937	11942	$EndPAD
11938	11943	$PAD
...	...
12707	12712	Sh "1" R 355 668 0 0 2700
12708	12713	Dr 0 0 0
12709	12714	At SMD N 00888000
12710		Ne 24 "/ether/MAG_SHIELD"
	12715	Ne 20 "/ether/MAG_SHIELD"
12711	12716	Po -570 0
12712	12717	$EndPAD
12713	12718	$PAD
...	...
12736	12741	Sh "1" R 394 1181 0 0 0
12737	12742	Dr 0 0 0
12738	12743	At SMD N 00440001
12739		Ne 95 "/fpga1/FPGA_BANK0_IO_8"
	12744	Ne 91 "/fpga1/FPGA_BANK0_IO_8"
12740	12745	Po 9448 -747
12741	12746	$EndPAD
12742	12747	$PAD
...	...
12757	12762	Sh "7" R 394 1181 0 0 0
12758	12763	Dr 0 0 0
12759	12764	At SMD N 00440001
12760		Ne 28 "/expansion/FPGA_BANK0_IO_10"
	12765	Ne 69 "/fpga1/FPGA_BANK0_IO_10"
12761	12766	Po 7086 -747
12762	12767	$EndPAD
12763	12768	$PAD
12764	12769	Sh "9" R 394 1181 0 0 0
12765	12770	Dr 0 0 0
12766	12771	At SMD N 00440001
12767		Ne 29 "/expansion/FPGA_BANK0_IO_11"
	12772	Ne 23 "/expansion/FPGA_BANK0_IO_11"
12768	12773	Po 6299 -747
12769	12774	$EndPAD
12770	12775	$PAD
12771	12776	Sh "11" R 394 1181 0 0 0
12772	12777	Dr 0 0 0
12773	12778	At SMD N 00440001
12774		Ne 45 "/expansion/FPGA_BANK0_IO_5"
	12779	Ne 43 "/expansion/FPGA_BANK0_IO_5"
12775	12780	Po 5511 -747
12776	12781	$EndPAD
12777	12782	$PAD
12778	12783	Sh "13" R 394 1181 0 0 0
12779	12784	Dr 0 0 0
12780	12785	At SMD N 00440001
12781		Ne 31 "/expansion/FPGA_BANK0_IO_17"
	12786	Ne 70 "/fpga1/FPGA_BANK0_IO_17"
12782	12787	Po 4724 -747
12783	12788	$EndPAD
12784	12789	$PAD
12785	12790	Sh "15" R 393 1181 0 0 0
12786	12791	Dr 0 0 0
12787	12792	At SMD N 00440001
12788		Ne 33 "/expansion/FPGA_BANK0_IO_20"
	12793	Ne 73 "/fpga1/FPGA_BANK0_IO_20"
12789	12794	Po 3936 -747
12790	12795	$EndPAD
12791	12796	$PAD
12792	12797	Sh "17" R 394 1181 0 0 0
12793	12798	Dr 0 0 0
12794	12799	At SMD N 00440001
12795		Ne 78 "/fpga1/FPGA_BANK0_IO_28"
	12800	Ne 29 "/expansion/FPGA_BANK0_IO_28"
12796	12801	Po 3149 -747
12797	12802	$EndPAD
12798	12803	$PAD
12799	12804	Sh "19" R 394 1181 0 0 0
12800	12805	Dr 0 0 0
12801	12806	At SMD N 00440001
12802		Ne 74 "/fpga1/FPGA_BANK0_IO_22"
	12807	Ne 27 "/expansion/FPGA_BANK0_IO_22"
12803	12808	Po 2362 -747
12804	12809	$EndPAD
12805	12810	$PAD
12806	12811	Sh "21" R 394 1181 0 0 0
12807	12812	Dr 0 0 0
12808	12813	At SMD N 00440001
12809		Ne 77 "/fpga1/FPGA_BANK0_IO_27"
	12814	Ne 76 "/fpga1/FPGA_BANK0_IO_27"
12810	12815	Po 1574 -747
12811	12816	$EndPAD
12812	12817	$PAD
12813	12818	Sh "23" R 394 1181 0 0 0
12814	12819	Dr 0 0 0
12815	12820	At SMD N 00440001
12816		Ne 40 "/expansion/FPGA_BANK0_IO_39"
	12821	Ne 35 "/expansion/FPGA_BANK0_IO_39"
12817	12822	Po 787 -747
12818	12823	$EndPAD
12819	12824	$PAD
12820	12825	Sh "25" R 392 1181 0 0 0
12821	12826	Dr 0 0 0
12822	12827	At SMD N 00440001
12823		Ne 32 "/expansion/FPGA_BANK0_IO_2"
	12828	Ne 72 "/fpga1/FPGA_BANK0_IO_2"
12824	12829	Po 0 -747
12825	12830	$EndPAD
12826	12831	$PAD
12827	12832	Sh "27" R 394 1181 0 0 0
12828	12833	Dr 0 0 0
12829	12834	At SMD N 00440001
12830		Ne 49 "/expansion/FPGA_BANK0_IO_7"
	12835	Ne 46 "/expansion/FPGA_BANK0_IO_7"
12831	12836	Po -787 -747
12832	12837	$EndPAD
12833	12838	$PAD
12834	12839	Sh "29" R 394 1181 0 0 0
12835	12840	Dr 0 0 0
12836	12841	At SMD N 00440001
12837		Ne 71 "/fpga1/FPGA_BANK0_IO_12"
	12842	Ne 24 "/expansion/FPGA_BANK0_IO_12"
12838	12843	Po -1574 -747
12839	12844	$EndPAD
12840	12845	$PAD
12841	12846	Sh "31" R 394 1181 0 0 0
12842	12847	Dr 0 0 0
12843	12848	At SMD N 00440001
12844		Ne 82 "/fpga1/FPGA_BANK0_IO_44"
	12849	Ne 38 "/expansion/FPGA_BANK0_IO_44"
12845	12850	Po -2362 -747
12846	12851	$EndPAD
12847	12852	$PAD
12848	12853	Sh "33" R 394 1181 0 0 0
12849	12854	Dr 0 0 0
12850	12855	At SMD N 00440001
12851		Ne 44 "/expansion/FPGA_BANK0_IO_47"
	12856	Ne 41 "/expansion/FPGA_BANK0_IO_47"
12852	12857	Po -3149 -747
12853	12858	$EndPAD
12854	12859	$PAD
12855	12860	Sh "35" R 393 1181 0 0 0
12856	12861	Dr 0 0 0
12857	12862	At SMD N 00440001
12858		Ne 83 "/fpga1/FPGA_BANK0_IO_45"
	12863	Ne 39 "/expansion/FPGA_BANK0_IO_45"
12859	12864	Po -3936 -747
12860	12865	$EndPAD
12861	12866	$PAD
12862	12867	Sh "37" R 394 1181 0 0 0
12863	12868	Dr 0 0 0
12864	12869	At SMD N 00440001
12865		Ne 87 "/fpga1/FPGA_BANK0_IO_52"
	12870	Ne 82 "/fpga1/FPGA_BANK0_IO_52"
12866	12871	Po -4724 -747
12867	12872	$EndPAD
12868	12873	$PAD
12869	12874	Sh "39" R 394 1181 0 0 0
12870	12875	Dr 0 0 0
12871	12876	At SMD N 00440001
12872		Ne 89 "/fpga1/FPGA_BANK0_IO_56"
	12877	Ne 85 "/fpga1/FPGA_BANK0_IO_56"
12873	12878	Po -5511 -747
12874	12879	$EndPAD
12875	12880	$PAD
12876	12881	Sh "41" R 394 1181 0 0 0
12877	12882	Dr 0 0 0
12878	12883	At SMD N 00440001
12879		Ne 86 "/fpga1/FPGA_BANK0_IO_51"
	12884	Ne 44 "/expansion/FPGA_BANK0_IO_51"
12880	12885	Po -6299 -747
12881	12886	$EndPAD
12882	12887	$PAD
12883	12888	Sh "43" R 394 1181 0 0 0
12884	12889	Dr 0 0 0
12885	12890	At SMD N 00440001
12886		Ne 47 "/expansion/FPGA_BANK0_IO_54"
	12891	Ne 84 "/fpga1/FPGA_BANK0_IO_54"
12887	12892	Po -7086 -747
12888	12893	$EndPAD
12889	12894	$PAD
12890	12895	Sh "45" R 393 1181 0 0 0
12891	12896	Dr 0 0 0
12892	12897	At SMD N 00440001
12893		Ne 94 "/fpga1/FPGA_BANK0_IO_63"
	12898	Ne 90 "/fpga1/FPGA_BANK0_IO_63"
12894	12899	Po -7873 -747
12895	12900	$EndPAD
12896	12901	$PAD
12897	12902	Sh "47" R 394 1181 0 0 0
12898	12903	Dr 0 0 0
12899	12904	At SMD N 00440001
12900		Ne 88 "/fpga1/FPGA_BANK0_IO_53"
	12905	Ne 83 "/fpga1/FPGA_BANK0_IO_53"
12901	12906	Po -8661 -747
12902	12907	$EndPAD
12903	12908	$PAD
12904	12909	Sh "49" R 394 1181 0 0 0
12905	12910	Dr 0 0 0
12906	12911	At SMD N 00440001
12907		Ne 91 "/fpga1/FPGA_BANK0_IO_58"
	12912	Ne 87 "/fpga1/FPGA_BANK0_IO_58"
12908	12913	Po -9448 -747
12909	12914	$EndPAD
12910	12915	$PAD
12911	12916	Sh "2" R 394 1181 0 0 0
12912	12917	Dr 0 0 0
12913	12918	At SMD N 00400001
12914		Ne 27 "/expansion/FPGA_BANK0_IO_1"
	12919	Ne 68 "/fpga1/FPGA_BANK0_IO_1"
12915	12920	Po 9448 747
12916	12921	$EndPAD
12917	12922	$PAD
12918	12923	Sh "4" R 394 1181 0 0 0
12919	12924	Dr 0 0 0
12920	12925	At SMD N 00400001
12921		Ne 50 "/expansion/FPGA_BANK0_IO_9"
	12926	Ne 47 "/expansion/FPGA_BANK0_IO_9"
12922	12927	Po 8661 747
12923	12928	$EndPAD
12924	12929	$PAD
12925	12930	Sh "6" R 393 1181 0 0 0
12926	12931	Dr 0 0 0
12927	12932	At SMD N 00400001
12928		Ne 72 "/fpga1/FPGA_BANK0_IO_14"
	12933	Ne 25 "/expansion/FPGA_BANK0_IO_14"
12929	12934	Po 7873 747
12930	12935	$EndPAD
12931	12936	$PAD
12932	12937	Sh "8" R 394 1181 0 0 0
12933	12938	Dr 0 0 0
12934	12939	At SMD N 00400001
12935		Ne 30 "/expansion/FPGA_BANK0_IO_15"
	12940	Ne 26 "/expansion/FPGA_BANK0_IO_15"
12936	12941	Po 7086 747
12937	12942	$EndPAD
12938	12943	$PAD
12939	12944	Sh "10" R 394 1181 0 0 0
12940	12945	Dr 0 0 0
12941	12946	At SMD N 00400001
12942		Ne 36 "/expansion/FPGA_BANK0_IO_3"
	12947	Ne 30 "/expansion/FPGA_BANK0_IO_3"
12943	12948	Po 6299 747
12944	12949	$EndPAD
12945	12950	$PAD
12946	12951	Sh "12" R 394 1181 0 0 0
12947	12952	Dr 0 0 0
12948	12953	At SMD N 00400001
12949		Ne 73 "/fpga1/FPGA_BANK0_IO_18"
	12954	Ne 71 "/fpga1/FPGA_BANK0_IO_18"
12950	12955	Po 5511 747
12951	12956	$EndPAD
12952	12957	$PAD
12953	12958	Sh "14" R 394 1181 0 0 0
12954	12959	Dr 0 0 0
12955	12960	At SMD N 00400001
12956		Ne 34 "/expansion/FPGA_BANK0_IO_21"
	12961	Ne 74 "/fpga1/FPGA_BANK0_IO_21"
12957	12962	Po 4724 747
12958	12963	$EndPAD
12959	12964	$PAD
12960	12965	Sh "16" R 393 1181 0 0 0
12961	12966	Dr 0 0 0
12962	12967	At SMD N 00400001
12963		Ne 75 "/fpga1/FPGA_BANK0_IO_24"
	12968	Ne 28 "/expansion/FPGA_BANK0_IO_24"
12964	12969	Po 3936 747
12965	12970	$EndPAD
12966	12971	$PAD
12967	12972	Sh "18" R 394 1181 0 0 0
12968	12973	Dr 0 0 0
12969	12974	At SMD N 00400001
12970		Ne 35 "/expansion/FPGA_BANK0_IO_29"
	12975	Ne 77 "/fpga1/FPGA_BANK0_IO_29"
12971	12976	Po 3149 747
12972	12977	$EndPAD
12973	12978	$PAD
12974	12979	Sh "20" R 394 1181 0 0 0
12975	12980	Dr 0 0 0
12976	12981	At SMD N 00400001
12977		Ne 79 "/fpga1/FPGA_BANK0_IO_30"
	12982	Ne 78 "/fpga1/FPGA_BANK0_IO_30"
12978	12983	Po 2362 747
12979	12984	$EndPAD
12980	12985	$PAD
12981	12986	Sh "22" R 394 1181 0 0 0
12982	12987	Dr 0 0 0
12983	12988	At SMD N 00400001
12984		Ne 76 "/fpga1/FPGA_BANK0_IO_25"
	12989	Ne 75 "/fpga1/FPGA_BANK0_IO_25"
12985	12990	Po 1574 747
12986	12991	$EndPAD
12987	12992	$PAD
12988	12993	Sh "24" R 394 1181 0 0 0
12989	12994	Dr 0 0 0
12990	12995	At SMD N 00400001
12991		Ne 80 "/fpga1/FPGA_BANK0_IO_33"
	12996	Ne 31 "/expansion/FPGA_BANK0_IO_33"
12992	12997	Po 787 747
12993	12998	$EndPAD
12994	12999	$PAD
12995	13000	Sh "26" R 392 1181 0 0 0
12996	13001	Dr 0 0 0
12997	13002	At SMD N 00400001
12998		Ne 37 "/expansion/FPGA_BANK0_IO_32"
	13003	Ne 79 "/fpga1/FPGA_BANK0_IO_32"
12999	13004	Po 0 747
13000	13005	$EndPAD
13001	13006	$PAD
13002	13007	Sh "28" R 394 1181 0 0 0
13003	13008	Dr 0 0 0
13004	13009	At SMD N 00400001
13005		Ne 48 "/expansion/FPGA_BANK0_IO_6"
	13010	Ne 88 "/fpga1/FPGA_BANK0_IO_6"
13006	13011	Po -787 747
13007	13012	$EndPAD
13008	13013	$PAD
13009	13014	Sh "30" R 394 1181 0 0 0
13010	13015	Dr 0 0 0
13011	13016	At SMD N 00400001
13012		Ne 81 "/fpga1/FPGA_BANK0_IO_36"
	13017	Ne 33 "/expansion/FPGA_BANK0_IO_36"
13013	13018	Po -1574 747
13014	13019	$EndPAD
13015	13020	$PAD
13016	13021	Sh "32" R 394 1181 0 0 0
13017	13022	Dr 0 0 0
13018	13023	At SMD N 00400001
13019		Ne 41 "/expansion/FPGA_BANK0_IO_40"
	13024	Ne 36 "/expansion/FPGA_BANK0_IO_40"
13020	13025	Po -2362 747
13021	13026	$EndPAD
13022	13027	$PAD
13023	13028	Sh "34" R 394 1181 0 0 0
13024	13029	Dr 0 0 0
13025	13030	At SMD N 00400001
13026		Ne 42 "/expansion/FPGA_BANK0_IO_43"
	13031	Ne 37 "/expansion/FPGA_BANK0_IO_43"
13027	13032	Po -3149 747
13028	13033	$EndPAD
13029	13034	$PAD
13030	13035	Sh "36" R 393 1181 0 0 0
13031	13036	Dr 0 0 0
13032	13037	At SMD N 00400001
13033		Ne 43 "/expansion/FPGA_BANK0_IO_46"
	13038	Ne 40 "/expansion/FPGA_BANK0_IO_46"
13034	13039	Po -3936 747
13035	13040	$EndPAD
13036	13041	$PAD
13037	13042	Sh "38" R 394 1181 0 0 0
13038	13043	Dr 0 0 0
13039	13044	At SMD N 00400001
13040		Ne 46 "/expansion/FPGA_BANK0_IO_50"
	13045	Ne 81 "/fpga1/FPGA_BANK0_IO_50"
13041	13046	Po -4724 747
13042	13047	$EndPAD
13043	13048	$PAD
13044	13049	Sh "40" R 394 1181 0 0 0
13045	13050	Dr 0 0 0
13046	13051	At SMD N 00400001
13047		Ne 84 "/fpga1/FPGA_BANK0_IO_48"
	13052	Ne 42 "/expansion/FPGA_BANK0_IO_48"
13048	13053	Po -5511 747
13049	13054	$EndPAD
13050	13055	$PAD
13051	13056	Sh "42" R 394 1181 0 0 0
13052	13057	Dr 0 0 0
13053	13058	At SMD N 00400001
13054		Ne 38 "/expansion/FPGA_BANK0_IO_34"
	13059	Ne 32 "/expansion/FPGA_BANK0_IO_34"
13055	13060	Po -6299 747
13056	13061	$EndPAD
13057	13062	$PAD
13058	13063	Sh "44" R 394 1181 0 0 0
13059	13064	Dr 0 0 0
13060	13065	At SMD N 00400001
13061		Ne 85 "/fpga1/FPGA_BANK0_IO_49"
	13066	Ne 80 "/fpga1/FPGA_BANK0_IO_49"
13062	13067	Po -7086 747
13063	13068	$EndPAD
13064	13069	$PAD
13065	13070	Sh "46" R 393 1181 0 0 0
13066	13071	Dr 0 0 0
13067	13072	At SMD N 00400001
13068		Ne 93 "/fpga1/FPGA_BANK0_IO_62"
	13073	Ne 45 "/expansion/FPGA_BANK0_IO_62"
13069	13074	Po -7873 747
13070	13075	$EndPAD