Xué video camera
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Xué video camera Git Source Tree
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Source at commit 1deb259 created 13 years 5 months ago. By Juan64Bits, Placing image sensor and sources | |
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1 | EESchema Schematic File Version 2 date Tue 05 Oct 2010 10:46:54 AM COT |
2 | LIBS:power |
3 | LIBS:r_pack2 |
4 | LIBS:v0402mhs03 |
5 | LIBS:usb-48204-0001 |
6 | LIBS:microsmd075f |
7 | LIBS:mic2550 |
8 | LIBS:rj45-48025 |
9 | LIBS:xue-nv |
10 | LIBS:xc6slx75fgg484 |
11 | LIBS:xc6slx45fgg484 |
12 | LIBS:micron_mobile_ddr |
13 | LIBS:micron_ddr_512Mb |
14 | LIBS:k8001 |
15 | LIBS:device |
16 | LIBS:transistors |
17 | LIBS:conn |
18 | LIBS:linear |
19 | LIBS:regul |
20 | LIBS:74xx |
21 | LIBS:cmos4000 |
22 | LIBS:adc-dac |
23 | LIBS:memory |
24 | LIBS:xilinx |
25 | LIBS:special |
26 | LIBS:microcontrollers |
27 | LIBS:dsp |
28 | LIBS:microchip |
29 | LIBS:analog_switches |
30 | LIBS:motorola |
31 | LIBS:texas |
32 | LIBS:intel |
33 | LIBS:audio |
34 | LIBS:interface |
35 | LIBS:digital-audio |
36 | LIBS:philips |
37 | LIBS:display |
38 | LIBS:cypress |
39 | LIBS:siliconi |
40 | LIBS:opto |
41 | LIBS:atmel |
42 | LIBS:contrib |
43 | LIBS:valves |
44 | LIBS:pasives-connectors |
45 | LIBS:x25x64mb |
46 | LIBS:attiny |
47 | LIBS:PSU |
48 | LIBS:tps793xx |
49 | LIBS:reg102 |
50 | LIBS:mt9m033 |
51 | LIBS:xue-rnc-cache |
52 | EELAYER 24 0 |
53 | EELAYER END |
54 | $Descr A4 11700 8267 |
55 | Sheet 4 11 |
56 | Title "" |
57 | Date "5 oct 2010" |
58 | Rev "" |
59 | Comp "" |
60 | Comment1 "" |
61 | Comment2 "" |
62 | Comment3 "" |
63 | Comment4 "" |
64 | $EndDescr |
65 | $Comp |
66 | L CONN_8X2 J6 |
67 | U 1 1 4C716CAB |
68 | P 2550 2350 |
69 | F 0 "J6" H 2550 2800 60 0000 C CNN |
70 | F 1 "CONN_8X2" V 2550 2350 50 0000 C CNN |
71 | 1 2550 2350 |
72 | 1 0 0 -1 |
73 | $EndComp |
74 | Wire Wire Line |
75 | 2150 2200 1900 2200 |
76 | Text HLabel 1900 2200 0 60 BiDi ~ 0 |
77 | FPGA_TDO |
78 | Text HLabel 1900 2300 0 60 BiDi ~ 0 |
79 | FPGA_TDI |
80 | Wire Wire Line |
81 | 2150 2300 1900 2300 |
82 | Wire Wire Line |
83 | 2150 2100 1900 2100 |
84 | Text HLabel 1900 2100 0 60 BiDi ~ 0 |
85 | FPGA_TMS |
86 | Text HLabel 1900 2000 0 60 BiDi ~ 0 |
87 | FPGA_TCK |
88 | Wire Wire Line |
89 | 2150 2000 1900 2000 |
90 | $EndSCHEMATC |
91 |
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