Root/kicad/xue-rnc/xue-rnc.sch

Source at commit 2db4e52 created 13 years 4 months ago.
By Juan64Bits, Revition...
1EESchema Schematic File Version 2 date Mon 01 Nov 2010 03:50:06 PM COT
2LIBS:power
3LIBS:r_pack2
4LIBS:v0402mhs03
5LIBS:usb-48204-0001
6LIBS:microsmd075f
7LIBS:mic2550
8LIBS:rj45-48025
9LIBS:xue-nv
10LIBS:xc6slx75fgg484
11LIBS:xc6slx45fgg484
12LIBS:micron_mobile_ddr
13LIBS:micron_ddr_512Mb
14LIBS:k8001
15LIBS:device
16LIBS:transistors
17LIBS:conn
18LIBS:linear
19LIBS:regul
20LIBS:74xx
21LIBS:cmos4000
22LIBS:adc-dac
23LIBS:memory
24LIBS:xilinx
25LIBS:special
26LIBS:microcontrollers
27LIBS:dsp
28LIBS:microchip
29LIBS:analog_switches
30LIBS:motorola
31LIBS:texas
32LIBS:intel
33LIBS:audio
34LIBS:interface
35LIBS:digital-audio
36LIBS:philips
37LIBS:display
38LIBS:cypress
39LIBS:siliconi
40LIBS:opto
41LIBS:atmel
42LIBS:contrib
43LIBS:valves
44LIBS:pasives-connectors
45LIBS:x25x64mb
46LIBS:attiny
47LIBS:PSU
48LIBS:tps793xx
49LIBS:reg102
50LIBS:mt9m033
51LIBS:m12-tu400a
52LIBS:ft2232c
53LIBS:xue-rnc-cache
54EELAYER 24 0
55EELAYER END
56$Descr A3 16535 11700
57Sheet 1 12
58Title ""
59Date "1 nov 2010"
60Rev ""
61Comp ""
62Comment1 ""
63Comment2 ""
64Comment3 ""
65Comment4 ""
66$EndDescr
67Wire Wire Line
68    4000 1250 3550 1250
69Wire Wire Line
70    3550 1250 3550 2400
71Wire Wire Line
72    3550 2400 4000 2400
73Wire Wire Line
74    4000 1450 3750 1450
75Wire Wire Line
76    3750 1450 3750 2200
77Wire Wire Line
78    3750 2200 4000 2200
79Wire Bus Line
80    9550 5600 10900 5600
81Wire Wire Line
82    5200 4050 6200 4050
83Wire Wire Line
84    5200 3050 6200 3050
85Wire Wire Line
86    5200 3850 6200 3850
87Wire Wire Line
88    5200 3650 6200 3650
89Wire Wire Line
90    6200 3450 5200 3450
91Wire Wire Line
92    5200 3250 6200 3250
93Wire Bus Line
94    6200 4550 5200 4550
95Wire Wire Line
96    3400 4750 3650 4750
97Wire Wire Line
98    3400 4450 3650 4450
99Wire Wire Line
100    3400 4150 3650 4150
101Wire Wire Line
102    10850 10100 9500 10100
103Wire Wire Line
104    10850 9900 9500 9900
105Wire Wire Line
106    6200 2400 5200 2400
107Wire Wire Line
108    6200 2200 5200 2200
109Wire Wire Line
110    10900 4600 9550 4600
111Wire Wire Line
112    10900 4500 9550 4500
113Wire Wire Line
114    10900 4150 9550 4150
115Wire Wire Line
116    10900 3950 9550 3950
117Wire Wire Line
118    10900 3850 9550 3850
119Wire Bus Line
120    10900 4250 9550 4250
121Wire Wire Line
122    10850 1300 9550 1300
123Wire Wire Line
124    9550 3200 10900 3200
125Wire Bus Line
126    10850 1800 9550 1800
127Wire Bus Line
128    9550 2200 10850 2200
129Wire Wire Line
130    10850 9500 9500 9500
131Wire Wire Line
132    10850 9300 9500 9300
133Wire Wire Line
134    9550 2500 10850 2500
135Wire Wire Line
136    9550 2300 10850 2300
137Wire Wire Line
138    9550 2100 10850 2100
139Wire Wire Line
140    9550 1900 10850 1900
141Wire Wire Line
142    9550 1600 10850 1600
143Wire Wire Line
144    9550 1200 10850 1200
145Wire Wire Line
146    9550 950 10850 950
147Wire Bus Line
148    4950 6800 6200 6800
149Wire Wire Line
150    4950 7200 6200 7200
151Wire Wire Line
152    4950 7300 6200 7300
153Wire Wire Line
154    4950 7500 6200 7500
155Wire Wire Line
156    4950 8350 6200 8350
157Wire Wire Line
158    4950 8200 6200 8200
159Wire Wire Line
160    4950 8750 6200 8750
161Wire Wire Line
162    4950 10250 6200 10250
163Wire Wire Line
164    4950 9350 6200 9350
165Wire Wire Line
166    4950 9650 6200 9650
167Wire Bus Line
168    4950 9000 6200 9000
169Wire Wire Line
170    4950 7850 6200 7850
171Wire Wire Line
172    4950 9900 6200 9900
173Wire Bus Line
174    4950 8900 6200 8900
175Wire Bus Line
176    6200 8900 6200 8950
177Wire Wire Line
178    4950 10000 6200 10000
179Wire Wire Line
180    6200 7950 4950 7950
181Wire Bus Line
182    4950 6900 6200 6900
183Wire Wire Line
184    4950 9250 6200 9250
185Wire Wire Line
186    4950 9550 6200 9550
187Wire Wire Line
188    4950 10150 6200 10150
189Wire Bus Line
190    4950 9100 6200 9100
191Wire Wire Line
192    4950 10400 6200 10400
193Wire Wire Line
194    4950 9800 6200 9800
195Wire Wire Line
196    4950 8100 6200 8100
197Wire Wire Line
198    4950 7750 6200 7750
199Wire Wire Line
200    4950 7600 6200 7600
201Wire Wire Line
202    4950 6650 6200 6650
203Wire Bus Line
204    4950 7000 6200 7000
205Wire Wire Line
206    9550 1100 10850 1100
207Wire Wire Line
208    10850 1500 9550 1500
209Wire Wire Line
210    9550 2000 10850 2000
211Wire Wire Line
212    9550 2400 10850 2400
213Wire Wire Line
214    10850 9200 9500 9200
215Wire Wire Line
216    10850 9400 9500 9400
217Wire Wire Line
218    10850 9600 9500 9600
219Wire Wire Line
220    9550 3100 10900 3100
221Wire Bus Line
222    9550 3300 10900 3300
223Wire Wire Line
224    10850 1400 9550 1400
225Wire Wire Line
226    9550 3750 10900 3750
227Wire Wire Line
228    10900 4050 9550 4050
229Wire Wire Line
230    10900 3650 9550 3650
231Wire Bus Line
232    10900 4700 9550 4700
233Wire Wire Line
234    6200 2100 5200 2100
235Wire Wire Line
236    5200 2300 6200 2300
237Wire Wire Line
238    10850 9800 9500 9800
239Wire Wire Line
240    10850 10000 9500 10000
241Wire Wire Line
242    10850 10200 9500 10200
243Wire Wire Line
244    3400 4300 3650 4300
245Wire Wire Line
246    3400 4600 3650 4600
247Wire Wire Line
248    6200 3150 5200 3150
249Wire Wire Line
250    5200 3350 6200 3350
251Wire Wire Line
252    5200 3550 6200 3550
253Wire Wire Line
254    5200 3750 6200 3750
255Wire Wire Line
256    6200 2950 5200 2950
257Wire Wire Line
258    5200 3950 6200 3950
259Wire Wire Line
260    5200 4150 6200 4150
261Wire Wire Line
262    4000 2100 3850 2100
263Wire Wire Line
264    3850 2100 3850 1550
265Wire Wire Line
266    3850 1550 4000 1550
267Wire Wire Line
268    4000 2300 3650 2300
269Wire Wire Line
270    3650 2300 3650 1350
271Wire Wire Line
272    3650 1350 4000 1350
273$Sheet
274S 10900 5250 1320 700
275U 4CB0D95D
276F0 "FPGA GPIOS" 60
277F1 "expantion.sch" 60
278F2 "FPGA_BANK0_IO_[0..64]" B L 10900 5600 60
279$EndSheet
280$Sheet
281S 3650 2850 1550 2050
282U 4C9E2AF4
283F0 "Image Sensor" 60
284F1 "sensor.sch" 60
285F2 "+2.8_VDDIO" B L 3650 4300 60
286F3 "+1.8_VDD" B L 3650 4450 60
287F4 "+2.8_VAA" B L 3650 4750 60
288F5 "+2.8_VAAPIX" B L 3650 4600 60
289F6 "+2.8_VDDPLL" B L 3650 4150 60
290F7 "IS_TRIGGER" I R 5200 2950 60
291F8 "IS_FLASH" O R 5200 3050 60
292F9 "IS_SDA" B R 5200 3150 60
293F10 "IS_SCL" B R 5200 3250 60
294F11 "IS_I2C_ADDR" I R 5200 3350 60
295F12 "IS_EXTCLK" I R 5200 3450 60
296F13 "IS_RESET_N" I R 5200 3550 60
297F14 "IS_OE_N" I R 5200 3650 60
298F15 "IS_STANDBY" I R 5200 3750 60
299F16 "IS_TEST" I R 5200 3850 60
300F17 "IS_PIXEL" O R 5200 3950 60
301F18 "IS_LINE" O R 5200 4050 60
302F19 "IS_FRAME" O R 5200 4150 60
303F20 "IS_DOUT[0..11]" O R 5200 4550 60
304$EndSheet
305$Sheet
306S 2300 3850 1100 1000
307U 4C9E2B0F
308F0 "Snesor PSU" 60
309F1 "sensor_psu.sch" 60
310F2 "+2.8_VDDPLL" B R 3400 4150 60
311F3 "+2.8_VDDIO" B R 3400 4300 60
312F4 "+1.8_VDD" B R 3400 4450 60
313F5 "+2.8_VAAPIX" B R 3400 4600 60
314F6 "+2.8_VAA" B R 3400 4750 60
315$EndSheet
316$Sheet
317S 6200 700 3350 5450
318U 4C7BC2B2
319F0 "FPGA, Port0, Port2, PROG IF" 60
320F1 "FPGA_0_2_PROG.sch" 60
321F2 "S6_TCK" I L 6200 2100 60
322F3 "S6_TDI" I L 6200 2200 60
323F4 "S6_TDO" O L 6200 2300 60
324F5 "S6_TMS" I L 6200 2400 60
325F6 "PROG_MISO[0..3]" B R 9550 4700 60
326F7 "PROG_CCLK" O R 9550 4600 60
327F8 "PROG_CSO" O R 9550 4500 60
328F9 "NF_D[0..7]" B R 9550 4250 60
329F10 "ETH_COL" B R 9550 1400 60
330F11 "ETH_CRS" B R 9550 1300 60
331F12 "NF_WE_N" O R 9550 3950 60
332F13 "NF_ALE" O R 9550 3750 60
333F14 "NF_CLE" O R 9550 3850 60
334F15 "NF_CS1_N" O R 9550 3650 60
335F16 "NF_RE_N" O R 9550 4050 60
336F17 "NF_RNB" B R 9550 4150 60
337F18 "SD_CLK" B R 9550 3100 60
338F19 "SD_CMD" B R 9550 3200 60
339F20 "SD_DAT[0..3]" B R 9550 3300 60
340F21 "ETH_CLK" B R 9550 2500 60
341F22 "ETH_RXC" B R 9550 1100 60
342F23 "ETH_TXC" B R 9550 2100 60
343F24 "ETH_TXD[0..3]" O R 9550 2200 60
344F25 "ETH_TXEN" B R 9550 2300 60
345F26 "ETH_TXER" B R 9550 2400 60
346F27 "ETH_RXER" B R 9550 2000 60
347F28 "ETH_RXDV" B R 9550 1900 60
348F29 "ETH_RXD[0..3]" I R 9550 1800 60
349F30 "ETH_RESET_N" B R 9550 1200 60
350F31 "ETH_MDIO" B R 9550 1500 60
351F32 "ETH_MDC" B R 9550 1600 60
352F33 "ETH_INT" B R 9550 950 60
353F34 "IS_DOUT[0..11]" I L 6200 4550 60
354F35 "IS_TEST" O L 6200 3850 60
355F36 "IS_STANDBY" O L 6200 3750 60
356F37 "IS_OE_N" O L 6200 3650 60
357F38 "IS_RESET_N" O L 6200 3550 60
358F39 "IS_EXTCLK" O L 6200 3450 60
359F40 "IS_I2C_ADDR" O L 6200 3350 60
360F41 "IS_SCL" B L 6200 3250 60
361F42 "IS_SDA" B L 6200 3150 60
362F43 "IS_FRAME" I L 6200 4150 60
363F44 "IS_LINE" I L 6200 4050 60
364F45 "IS_PIXEL" I L 6200 3950 60
365F46 "IS_FLASH" I L 6200 3050 60
366F47 "IS_TRIGGER" O L 6200 2950 60
367F48 "FPGA_BANK0_IO_[0..64]" B R 9550 5600 60
368$EndSheet
369$Sheet
370S 6200 6400 3300 4350
371U 4C7BC2A2
372F0 "FPGA Port 1, Port 3 DDR, USB" 60
373F1 "FPGA_1_3.sch" 60
374F2 "USBD_VP" B R 9500 10100 60
375F3 "USBD_SPD" B R 9500 9800 60
376F4 "USBD_OE_N" B R 9500 9900 60
377F5 "USBD_RCV" B R 9500 10000 60
378F6 "USBD_VM" B R 9500 10200 60
379F7 "M0_CKE" O L 6200 9800 60
380F8 "M0_UDM" O L 6200 9550 60
381F9 "M0_UDQS" O L 6200 9250 60
382F10 "M0_BA[0..1]" O L 6200 9100 60
383F11 "M0_CAS#" O L 6200 10150 60
384F12 "M0_RAS#" O L 6200 10250 60
385F13 "M0_WE#" O L 6200 10400 60
386F14 "M0_LDM" O L 6200 9650 60
387F15 "M0_LDQS" O L 6200 9350 60
388F16 "M1_UDQS" O L 6200 7200 60
389F17 "M1_UDM" O L 6200 7500 60
390F18 "M1_LDQS" O L 6200 7300 60
391F19 "M1_LDM" O L 6200 7600 60
392F20 "M1_WE#" O L 6200 8350 60
393F21 "M1_CKE" O L 6200 7750 60
394F22 "M1_RAS#" O L 6200 8200 60
395F23 "M1_CAS#" O L 6200 8100 60
396F24 "M1_BA[0..1]" O L 6200 7000 60
397F25 "M1_CS#" O L 6200 6650 60
398F26 "USBA_VM" B R 9500 9600 60
399F27 "USBA_VP" B R 9500 9500 60
400F28 "USBA_RCV" B R 9500 9400 60
401F29 "USBA_OE_N" B R 9500 9300 60
402F30 "USBA_SPD" B R 9500 9200 60
403F31 "M1_DQ[0..15]" B L 6200 6800 60
404F32 "M0_CS#" O L 6200 8750 60
405F33 "M0_DQ[0..15]" B L 6200 8900 60
406F34 "M0_A[0..12]" O L 6200 9000 60
407F35 "M1_A[0..12]" O L 6200 6900 60
408F36 "M1_CLK" O L 6200 7850 60
409F37 "M1_CLK#" O L 6200 7950 60
410F38 "M0_CLK" O L 6200 9900 60
411F39 "M0_CLK#" O L 6200 10000 60
412$EndSheet
413$Sheet
414S 4000 1900 1200 700
415U 4C716A4D
416F0 "DBG_PRG" 60
417F1 "DBG_PRG.sch" 60
418F2 "FPGA_TDO" B R 5200 2300 60
419F3 "FPGA_TDI" B R 5200 2200 60
420F4 "FPGA_TMS" B R 5200 2400 60
421F5 "FPGA_TCK" B R 5200 2100 60
422F6 "AVR_SCK" B L 4000 2100 60
423F7 "AVR_RST" B L 4000 2400 60
424F8 "AVR_MOSI" B L 4000 2200 60
425F9 "AVR_MISO" B L 4000 2300 60
426$EndSheet
427$Sheet
428S 4000 950 1200 750
429U 4C69ED5F
430F0 "PSU" 60
431F1 "PSU.sch" 60
432F2 "AVR_SCK" B L 4000 1550 60
433F3 "AVR_MISO" B L 4000 1350 60
434F4 "AVR_MOSI" B L 4000 1450 60
435F5 "AVR_RST" B L 4000 1250 60
436$EndSheet
437$Sheet
438S 10900 2900 1050 1950
439U 4C4227FE
440F0 "Non volatile memories" 60
441F1 "NV_MEMORIES.sch" 60
442F2 "SD_CMD" I L 10900 3200 60
443F3 "SD_CLK" I L 10900 3100 60
444F4 "SD_DAT[0..3]" B L 10900 3300 60
445F5 "NF_D[0..7]" B L 10900 4250 60
446F6 "NF_ALE" B L 10900 3750 60
447F7 "NF_CLE" B L 10900 3850 60
448F8 "NF_WE_N" B L 10900 3950 60
449F9 "NF_CS1_N" B L 10900 3650 60
450F10 "NF_RE_N" B L 10900 4050 60
451F11 "NF_RNB" B L 10900 4150 60
452F12 "SPI_CLK" I L 10900 4600 60
453F13 "SPI_FLASH_CS#" I L 10900 4500 60
454F14 "SPI_DQ[0..3]" B L 10900 4700 60
455$EndSheet
456$Sheet
457S 10850 9150 1100 1150
458U 4C5F1EDC
459F0 "USB" 60
460F1 "USB.sch" 60
461F2 "USBA_SPD" B L 10850 9200 60
462F3 "USBA_OE_N" B L 10850 9300 60
463F4 "USBA_RCV" B L 10850 9400 60
464F5 "USBA_VP" B L 10850 9500 60
465F6 "USBA_VM" B L 10850 9600 60
466F7 "USBD_SPD" B L 10850 9800 60
467F8 "USBD_OE_N" B L 10850 9900 60
468F9 "USBD_RCV" B L 10850 10000 60
469F10 "USBD_VP" B L 10850 10100 60
470F11 "USBD_VM" B L 10850 10200 60
471$EndSheet
472Text Notes 19700 15650 0 60 ~ 0
473Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
474$Sheet
475S 10850 850 1300 1800
476U 4C4320F3
477F0 "Ethernet Phy" 60
478F1 "eth_phy.sch" 60
479F2 "ETH_RXC" O L 10850 1100 60
480F3 "ETH_RST_N" I L 10850 1200 60
481F4 "ETH_CRS" O L 10850 1300 60
482F5 "ETH_COL" O L 10850 1400 60
483F6 "ETH_MDIO" B L 10850 1500 60
484F7 "ETH_MDC" I L 10850 1600 60
485F8 "ETH_RXD[0..3]" O L 10850 1800 60
486F9 "ETH_RXDV" O L 10850 1900 60
487F10 "ETH_RXER" O L 10850 2000 60
488F11 "ETH_TXC" B L 10850 2100 60
489F12 "ETH_TXD[0..3]" I L 10850 2200 60
490F13 "ETH_TXEN" I L 10850 2300 60
491F14 "ETH_TXER" I L 10850 2400 60
492F15 "ETH_CLK" I L 10850 2500 60
493F16 "ETH_INT" O L 10850 950 60
494$EndSheet
495$Sheet
496S 3850 6550 1100 4000
497U 4C421DD3
498F0 "DDR Banks" 60
499F1 "DRAM.sch" 60
500F2 "M0_BA[0..1]" I R 4950 9100 60
501F3 "M1_BA[0..1]" I R 4950 7000 60
502F4 "M0_WE#" I R 4950 10400 60
503F5 "M0_RAS#" I R 4950 10250 60
504F6 "M1_RAS#" I R 4950 8200 60
505F7 "M1_WE#" I R 4950 8350 60
506F8 "M0_CAS#" I R 4950 10150 60
507F9 "M0_CKE" I R 4950 9800 60
508F10 "M0_CLK" I R 4950 9900 60
509F11 "M0_CLK#" I R 4950 10000 60
510F12 "M0_CS#" I R 4950 8750 60
511F13 "M1_CLK#" I R 4950 7950 60
512F14 "M1_CLK" I R 4950 7850 60
513F15 "M1_CKE" I R 4950 7750 60
514F16 "M1_CAS#" I R 4950 8100 60
515F17 "M0_DQ[0..15]" B R 4950 8900 60
516F18 "M0_UDM" I R 4950 9550 60
517F19 "M0_LDQS" I R 4950 9350 60
518F20 "M0_A[0..12]" I R 4950 9000 60
519F21 "M0_LDM" I R 4950 9650 60
520F22 "M0_UDQS" I R 4950 9250 60
521F23 "M1_UDQS" I R 4950 7200 60
522F24 "M1_LDM" I R 4950 7600 60
523F25 "M1_LDQS" I R 4950 7300 60
524F26 "M1_UDM" I R 4950 7500 60
525F27 "M1_CS#" I R 4950 6650 60
526F28 "M1_A[0..12]" I R 4950 6900 60
527F29 "M1_DQ[0..15]" B R 4950 6800 60
528$EndSheet
529$EndSCHEMATC
530

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