Xué video camera
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Xué video camera Git Source Tree
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Source at commit 2db4e52 created 13 years 4 months ago. By Juan64Bits, Revition... | |
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1 | EESchema Schematic File Version 2 date Mon 01 Nov 2010 03:50:06 PM COT |
2 | LIBS:power |
3 | LIBS:r_pack2 |
4 | LIBS:v0402mhs03 |
5 | LIBS:usb-48204-0001 |
6 | LIBS:microsmd075f |
7 | LIBS:mic2550 |
8 | LIBS:rj45-48025 |
9 | LIBS:xue-nv |
10 | LIBS:xc6slx75fgg484 |
11 | LIBS:xc6slx45fgg484 |
12 | LIBS:micron_mobile_ddr |
13 | LIBS:micron_ddr_512Mb |
14 | LIBS:k8001 |
15 | LIBS:device |
16 | LIBS:transistors |
17 | LIBS:conn |
18 | LIBS:linear |
19 | LIBS:regul |
20 | LIBS:74xx |
21 | LIBS:cmos4000 |
22 | LIBS:adc-dac |
23 | LIBS:memory |
24 | LIBS:xilinx |
25 | LIBS:special |
26 | LIBS:microcontrollers |
27 | LIBS:dsp |
28 | LIBS:microchip |
29 | LIBS:analog_switches |
30 | LIBS:motorola |
31 | LIBS:texas |
32 | LIBS:intel |
33 | LIBS:audio |
34 | LIBS:interface |
35 | LIBS:digital-audio |
36 | LIBS:philips |
37 | LIBS:display |
38 | LIBS:cypress |
39 | LIBS:siliconi |
40 | LIBS:opto |
41 | LIBS:atmel |
42 | LIBS:contrib |
43 | LIBS:valves |
44 | LIBS:pasives-connectors |
45 | LIBS:x25x64mb |
46 | LIBS:attiny |
47 | LIBS:PSU |
48 | LIBS:tps793xx |
49 | LIBS:reg102 |
50 | LIBS:mt9m033 |
51 | LIBS:m12-tu400a |
52 | LIBS:ft2232c |
53 | LIBS:xue-rnc-cache |
54 | EELAYER 24 0 |
55 | EELAYER END |
56 | $Descr A3 16535 11700 |
57 | Sheet 1 12 |
58 | Title "" |
59 | Date "1 nov 2010" |
60 | Rev "" |
61 | Comp "" |
62 | Comment1 "" |
63 | Comment2 "" |
64 | Comment3 "" |
65 | Comment4 "" |
66 | $EndDescr |
67 | Wire Wire Line |
68 | 4000 1250 3550 1250 |
69 | Wire Wire Line |
70 | 3550 1250 3550 2400 |
71 | Wire Wire Line |
72 | 3550 2400 4000 2400 |
73 | Wire Wire Line |
74 | 4000 1450 3750 1450 |
75 | Wire Wire Line |
76 | 3750 1450 3750 2200 |
77 | Wire Wire Line |
78 | 3750 2200 4000 2200 |
79 | Wire Bus Line |
80 | 9550 5600 10900 5600 |
81 | Wire Wire Line |
82 | 5200 4050 6200 4050 |
83 | Wire Wire Line |
84 | 5200 3050 6200 3050 |
85 | Wire Wire Line |
86 | 5200 3850 6200 3850 |
87 | Wire Wire Line |
88 | 5200 3650 6200 3650 |
89 | Wire Wire Line |
90 | 6200 3450 5200 3450 |
91 | Wire Wire Line |
92 | 5200 3250 6200 3250 |
93 | Wire Bus Line |
94 | 6200 4550 5200 4550 |
95 | Wire Wire Line |
96 | 3400 4750 3650 4750 |
97 | Wire Wire Line |
98 | 3400 4450 3650 4450 |
99 | Wire Wire Line |
100 | 3400 4150 3650 4150 |
101 | Wire Wire Line |
102 | 10850 10100 9500 10100 |
103 | Wire Wire Line |
104 | 10850 9900 9500 9900 |
105 | Wire Wire Line |
106 | 6200 2400 5200 2400 |
107 | Wire Wire Line |
108 | 6200 2200 5200 2200 |
109 | Wire Wire Line |
110 | 10900 4600 9550 4600 |
111 | Wire Wire Line |
112 | 10900 4500 9550 4500 |
113 | Wire Wire Line |
114 | 10900 4150 9550 4150 |
115 | Wire Wire Line |
116 | 10900 3950 9550 3950 |
117 | Wire Wire Line |
118 | 10900 3850 9550 3850 |
119 | Wire Bus Line |
120 | 10900 4250 9550 4250 |
121 | Wire Wire Line |
122 | 10850 1300 9550 1300 |
123 | Wire Wire Line |
124 | 9550 3200 10900 3200 |
125 | Wire Bus Line |
126 | 10850 1800 9550 1800 |
127 | Wire Bus Line |
128 | 9550 2200 10850 2200 |
129 | Wire Wire Line |
130 | 10850 9500 9500 9500 |
131 | Wire Wire Line |
132 | 10850 9300 9500 9300 |
133 | Wire Wire Line |
134 | 9550 2500 10850 2500 |
135 | Wire Wire Line |
136 | 9550 2300 10850 2300 |
137 | Wire Wire Line |
138 | 9550 2100 10850 2100 |
139 | Wire Wire Line |
140 | 9550 1900 10850 1900 |
141 | Wire Wire Line |
142 | 9550 1600 10850 1600 |
143 | Wire Wire Line |
144 | 9550 1200 10850 1200 |
145 | Wire Wire Line |
146 | 9550 950 10850 950 |
147 | Wire Bus Line |
148 | 4950 6800 6200 6800 |
149 | Wire Wire Line |
150 | 4950 7200 6200 7200 |
151 | Wire Wire Line |
152 | 4950 7300 6200 7300 |
153 | Wire Wire Line |
154 | 4950 7500 6200 7500 |
155 | Wire Wire Line |
156 | 4950 8350 6200 8350 |
157 | Wire Wire Line |
158 | 4950 8200 6200 8200 |
159 | Wire Wire Line |
160 | 4950 8750 6200 8750 |
161 | Wire Wire Line |
162 | 4950 10250 6200 10250 |
163 | Wire Wire Line |
164 | 4950 9350 6200 9350 |
165 | Wire Wire Line |
166 | 4950 9650 6200 9650 |
167 | Wire Bus Line |
168 | 4950 9000 6200 9000 |
169 | Wire Wire Line |
170 | 4950 7850 6200 7850 |
171 | Wire Wire Line |
172 | 4950 9900 6200 9900 |
173 | Wire Bus Line |
174 | 4950 8900 6200 8900 |
175 | Wire Bus Line |
176 | 6200 8900 6200 8950 |
177 | Wire Wire Line |
178 | 4950 10000 6200 10000 |
179 | Wire Wire Line |
180 | 6200 7950 4950 7950 |
181 | Wire Bus Line |
182 | 4950 6900 6200 6900 |
183 | Wire Wire Line |
184 | 4950 9250 6200 9250 |
185 | Wire Wire Line |
186 | 4950 9550 6200 9550 |
187 | Wire Wire Line |
188 | 4950 10150 6200 10150 |
189 | Wire Bus Line |
190 | 4950 9100 6200 9100 |
191 | Wire Wire Line |
192 | 4950 10400 6200 10400 |
193 | Wire Wire Line |
194 | 4950 9800 6200 9800 |
195 | Wire Wire Line |
196 | 4950 8100 6200 8100 |
197 | Wire Wire Line |
198 | 4950 7750 6200 7750 |
199 | Wire Wire Line |
200 | 4950 7600 6200 7600 |
201 | Wire Wire Line |
202 | 4950 6650 6200 6650 |
203 | Wire Bus Line |
204 | 4950 7000 6200 7000 |
205 | Wire Wire Line |
206 | 9550 1100 10850 1100 |
207 | Wire Wire Line |
208 | 10850 1500 9550 1500 |
209 | Wire Wire Line |
210 | 9550 2000 10850 2000 |
211 | Wire Wire Line |
212 | 9550 2400 10850 2400 |
213 | Wire Wire Line |
214 | 10850 9200 9500 9200 |
215 | Wire Wire Line |
216 | 10850 9400 9500 9400 |
217 | Wire Wire Line |
218 | 10850 9600 9500 9600 |
219 | Wire Wire Line |
220 | 9550 3100 10900 3100 |
221 | Wire Bus Line |
222 | 9550 3300 10900 3300 |
223 | Wire Wire Line |
224 | 10850 1400 9550 1400 |
225 | Wire Wire Line |
226 | 9550 3750 10900 3750 |
227 | Wire Wire Line |
228 | 10900 4050 9550 4050 |
229 | Wire Wire Line |
230 | 10900 3650 9550 3650 |
231 | Wire Bus Line |
232 | 10900 4700 9550 4700 |
233 | Wire Wire Line |
234 | 6200 2100 5200 2100 |
235 | Wire Wire Line |
236 | 5200 2300 6200 2300 |
237 | Wire Wire Line |
238 | 10850 9800 9500 9800 |
239 | Wire Wire Line |
240 | 10850 10000 9500 10000 |
241 | Wire Wire Line |
242 | 10850 10200 9500 10200 |
243 | Wire Wire Line |
244 | 3400 4300 3650 4300 |
245 | Wire Wire Line |
246 | 3400 4600 3650 4600 |
247 | Wire Wire Line |
248 | 6200 3150 5200 3150 |
249 | Wire Wire Line |
250 | 5200 3350 6200 3350 |
251 | Wire Wire Line |
252 | 5200 3550 6200 3550 |
253 | Wire Wire Line |
254 | 5200 3750 6200 3750 |
255 | Wire Wire Line |
256 | 6200 2950 5200 2950 |
257 | Wire Wire Line |
258 | 5200 3950 6200 3950 |
259 | Wire Wire Line |
260 | 5200 4150 6200 4150 |
261 | Wire Wire Line |
262 | 4000 2100 3850 2100 |
263 | Wire Wire Line |
264 | 3850 2100 3850 1550 |
265 | Wire Wire Line |
266 | 3850 1550 4000 1550 |
267 | Wire Wire Line |
268 | 4000 2300 3650 2300 |
269 | Wire Wire Line |
270 | 3650 2300 3650 1350 |
271 | Wire Wire Line |
272 | 3650 1350 4000 1350 |
273 | $Sheet |
274 | S 10900 5250 1320 700 |
275 | U 4CB0D95D |
276 | F0 "FPGA GPIOS" 60 |
277 | F1 "expantion.sch" 60 |
278 | F2 "FPGA_BANK0_IO_[0..64]" B L 10900 5600 60 |
279 | $EndSheet |
280 | $Sheet |
281 | S 3650 2850 1550 2050 |
282 | U 4C9E2AF4 |
283 | F0 "Image Sensor" 60 |
284 | F1 "sensor.sch" 60 |
285 | F2 "+2.8_VDDIO" B L 3650 4300 60 |
286 | F3 "+1.8_VDD" B L 3650 4450 60 |
287 | F4 "+2.8_VAA" B L 3650 4750 60 |
288 | F5 "+2.8_VAAPIX" B L 3650 4600 60 |
289 | F6 "+2.8_VDDPLL" B L 3650 4150 60 |
290 | F7 "IS_TRIGGER" I R 5200 2950 60 |
291 | F8 "IS_FLASH" O R 5200 3050 60 |
292 | F9 "IS_SDA" B R 5200 3150 60 |
293 | F10 "IS_SCL" B R 5200 3250 60 |
294 | F11 "IS_I2C_ADDR" I R 5200 3350 60 |
295 | F12 "IS_EXTCLK" I R 5200 3450 60 |
296 | F13 "IS_RESET_N" I R 5200 3550 60 |
297 | F14 "IS_OE_N" I R 5200 3650 60 |
298 | F15 "IS_STANDBY" I R 5200 3750 60 |
299 | F16 "IS_TEST" I R 5200 3850 60 |
300 | F17 "IS_PIXEL" O R 5200 3950 60 |
301 | F18 "IS_LINE" O R 5200 4050 60 |
302 | F19 "IS_FRAME" O R 5200 4150 60 |
303 | F20 "IS_DOUT[0..11]" O R 5200 4550 60 |
304 | $EndSheet |
305 | $Sheet |
306 | S 2300 3850 1100 1000 |
307 | U 4C9E2B0F |
308 | F0 "Snesor PSU" 60 |
309 | F1 "sensor_psu.sch" 60 |
310 | F2 "+2.8_VDDPLL" B R 3400 4150 60 |
311 | F3 "+2.8_VDDIO" B R 3400 4300 60 |
312 | F4 "+1.8_VDD" B R 3400 4450 60 |
313 | F5 "+2.8_VAAPIX" B R 3400 4600 60 |
314 | F6 "+2.8_VAA" B R 3400 4750 60 |
315 | $EndSheet |
316 | $Sheet |
317 | S 6200 700 3350 5450 |
318 | U 4C7BC2B2 |
319 | F0 "FPGA, Port0, Port2, PROG IF" 60 |
320 | F1 "FPGA_0_2_PROG.sch" 60 |
321 | F2 "S6_TCK" I L 6200 2100 60 |
322 | F3 "S6_TDI" I L 6200 2200 60 |
323 | F4 "S6_TDO" O L 6200 2300 60 |
324 | F5 "S6_TMS" I L 6200 2400 60 |
325 | F6 "PROG_MISO[0..3]" B R 9550 4700 60 |
326 | F7 "PROG_CCLK" O R 9550 4600 60 |
327 | F8 "PROG_CSO" O R 9550 4500 60 |
328 | F9 "NF_D[0..7]" B R 9550 4250 60 |
329 | F10 "ETH_COL" B R 9550 1400 60 |
330 | F11 "ETH_CRS" B R 9550 1300 60 |
331 | F12 "NF_WE_N" O R 9550 3950 60 |
332 | F13 "NF_ALE" O R 9550 3750 60 |
333 | F14 "NF_CLE" O R 9550 3850 60 |
334 | F15 "NF_CS1_N" O R 9550 3650 60 |
335 | F16 "NF_RE_N" O R 9550 4050 60 |
336 | F17 "NF_RNB" B R 9550 4150 60 |
337 | F18 "SD_CLK" B R 9550 3100 60 |
338 | F19 "SD_CMD" B R 9550 3200 60 |
339 | F20 "SD_DAT[0..3]" B R 9550 3300 60 |
340 | F21 "ETH_CLK" B R 9550 2500 60 |
341 | F22 "ETH_RXC" B R 9550 1100 60 |
342 | F23 "ETH_TXC" B R 9550 2100 60 |
343 | F24 "ETH_TXD[0..3]" O R 9550 2200 60 |
344 | F25 "ETH_TXEN" B R 9550 2300 60 |
345 | F26 "ETH_TXER" B R 9550 2400 60 |
346 | F27 "ETH_RXER" B R 9550 2000 60 |
347 | F28 "ETH_RXDV" B R 9550 1900 60 |
348 | F29 "ETH_RXD[0..3]" I R 9550 1800 60 |
349 | F30 "ETH_RESET_N" B R 9550 1200 60 |
350 | F31 "ETH_MDIO" B R 9550 1500 60 |
351 | F32 "ETH_MDC" B R 9550 1600 60 |
352 | F33 "ETH_INT" B R 9550 950 60 |
353 | F34 "IS_DOUT[0..11]" I L 6200 4550 60 |
354 | F35 "IS_TEST" O L 6200 3850 60 |
355 | F36 "IS_STANDBY" O L 6200 3750 60 |
356 | F37 "IS_OE_N" O L 6200 3650 60 |
357 | F38 "IS_RESET_N" O L 6200 3550 60 |
358 | F39 "IS_EXTCLK" O L 6200 3450 60 |
359 | F40 "IS_I2C_ADDR" O L 6200 3350 60 |
360 | F41 "IS_SCL" B L 6200 3250 60 |
361 | F42 "IS_SDA" B L 6200 3150 60 |
362 | F43 "IS_FRAME" I L 6200 4150 60 |
363 | F44 "IS_LINE" I L 6200 4050 60 |
364 | F45 "IS_PIXEL" I L 6200 3950 60 |
365 | F46 "IS_FLASH" I L 6200 3050 60 |
366 | F47 "IS_TRIGGER" O L 6200 2950 60 |
367 | F48 "FPGA_BANK0_IO_[0..64]" B R 9550 5600 60 |
368 | $EndSheet |
369 | $Sheet |
370 | S 6200 6400 3300 4350 |
371 | U 4C7BC2A2 |
372 | F0 "FPGA Port 1, Port 3 DDR, USB" 60 |
373 | F1 "FPGA_1_3.sch" 60 |
374 | F2 "USBD_VP" B R 9500 10100 60 |
375 | F3 "USBD_SPD" B R 9500 9800 60 |
376 | F4 "USBD_OE_N" B R 9500 9900 60 |
377 | F5 "USBD_RCV" B R 9500 10000 60 |
378 | F6 "USBD_VM" B R 9500 10200 60 |
379 | F7 "M0_CKE" O L 6200 9800 60 |
380 | F8 "M0_UDM" O L 6200 9550 60 |
381 | F9 "M0_UDQS" O L 6200 9250 60 |
382 | F10 "M0_BA[0..1]" O L 6200 9100 60 |
383 | F11 "M0_CAS#" O L 6200 10150 60 |
384 | F12 "M0_RAS#" O L 6200 10250 60 |
385 | F13 "M0_WE#" O L 6200 10400 60 |
386 | F14 "M0_LDM" O L 6200 9650 60 |
387 | F15 "M0_LDQS" O L 6200 9350 60 |
388 | F16 "M1_UDQS" O L 6200 7200 60 |
389 | F17 "M1_UDM" O L 6200 7500 60 |
390 | F18 "M1_LDQS" O L 6200 7300 60 |
391 | F19 "M1_LDM" O L 6200 7600 60 |
392 | F20 "M1_WE#" O L 6200 8350 60 |
393 | F21 "M1_CKE" O L 6200 7750 60 |
394 | F22 "M1_RAS#" O L 6200 8200 60 |
395 | F23 "M1_CAS#" O L 6200 8100 60 |
396 | F24 "M1_BA[0..1]" O L 6200 7000 60 |
397 | F25 "M1_CS#" O L 6200 6650 60 |
398 | F26 "USBA_VM" B R 9500 9600 60 |
399 | F27 "USBA_VP" B R 9500 9500 60 |
400 | F28 "USBA_RCV" B R 9500 9400 60 |
401 | F29 "USBA_OE_N" B R 9500 9300 60 |
402 | F30 "USBA_SPD" B R 9500 9200 60 |
403 | F31 "M1_DQ[0..15]" B L 6200 6800 60 |
404 | F32 "M0_CS#" O L 6200 8750 60 |
405 | F33 "M0_DQ[0..15]" B L 6200 8900 60 |
406 | F34 "M0_A[0..12]" O L 6200 9000 60 |
407 | F35 "M1_A[0..12]" O L 6200 6900 60 |
408 | F36 "M1_CLK" O L 6200 7850 60 |
409 | F37 "M1_CLK#" O L 6200 7950 60 |
410 | F38 "M0_CLK" O L 6200 9900 60 |
411 | F39 "M0_CLK#" O L 6200 10000 60 |
412 | $EndSheet |
413 | $Sheet |
414 | S 4000 1900 1200 700 |
415 | U 4C716A4D |
416 | F0 "DBG_PRG" 60 |
417 | F1 "DBG_PRG.sch" 60 |
418 | F2 "FPGA_TDO" B R 5200 2300 60 |
419 | F3 "FPGA_TDI" B R 5200 2200 60 |
420 | F4 "FPGA_TMS" B R 5200 2400 60 |
421 | F5 "FPGA_TCK" B R 5200 2100 60 |
422 | F6 "AVR_SCK" B L 4000 2100 60 |
423 | F7 "AVR_RST" B L 4000 2400 60 |
424 | F8 "AVR_MOSI" B L 4000 2200 60 |
425 | F9 "AVR_MISO" B L 4000 2300 60 |
426 | $EndSheet |
427 | $Sheet |
428 | S 4000 950 1200 750 |
429 | U 4C69ED5F |
430 | F0 "PSU" 60 |
431 | F1 "PSU.sch" 60 |
432 | F2 "AVR_SCK" B L 4000 1550 60 |
433 | F3 "AVR_MISO" B L 4000 1350 60 |
434 | F4 "AVR_MOSI" B L 4000 1450 60 |
435 | F5 "AVR_RST" B L 4000 1250 60 |
436 | $EndSheet |
437 | $Sheet |
438 | S 10900 2900 1050 1950 |
439 | U 4C4227FE |
440 | F0 "Non volatile memories" 60 |
441 | F1 "NV_MEMORIES.sch" 60 |
442 | F2 "SD_CMD" I L 10900 3200 60 |
443 | F3 "SD_CLK" I L 10900 3100 60 |
444 | F4 "SD_DAT[0..3]" B L 10900 3300 60 |
445 | F5 "NF_D[0..7]" B L 10900 4250 60 |
446 | F6 "NF_ALE" B L 10900 3750 60 |
447 | F7 "NF_CLE" B L 10900 3850 60 |
448 | F8 "NF_WE_N" B L 10900 3950 60 |
449 | F9 "NF_CS1_N" B L 10900 3650 60 |
450 | F10 "NF_RE_N" B L 10900 4050 60 |
451 | F11 "NF_RNB" B L 10900 4150 60 |
452 | F12 "SPI_CLK" I L 10900 4600 60 |
453 | F13 "SPI_FLASH_CS#" I L 10900 4500 60 |
454 | F14 "SPI_DQ[0..3]" B L 10900 4700 60 |
455 | $EndSheet |
456 | $Sheet |
457 | S 10850 9150 1100 1150 |
458 | U 4C5F1EDC |
459 | F0 "USB" 60 |
460 | F1 "USB.sch" 60 |
461 | F2 "USBA_SPD" B L 10850 9200 60 |
462 | F3 "USBA_OE_N" B L 10850 9300 60 |
463 | F4 "USBA_RCV" B L 10850 9400 60 |
464 | F5 "USBA_VP" B L 10850 9500 60 |
465 | F6 "USBA_VM" B L 10850 9600 60 |
466 | F7 "USBD_SPD" B L 10850 9800 60 |
467 | F8 "USBD_OE_N" B L 10850 9900 60 |
468 | F9 "USBD_RCV" B L 10850 10000 60 |
469 | F10 "USBD_VP" B L 10850 10100 60 |
470 | F11 "USBD_VM" B L 10850 10200 60 |
471 | $EndSheet |
472 | Text Notes 19700 15650 0 60 ~ 0 |
473 | Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com |
474 | $Sheet |
475 | S 10850 850 1300 1800 |
476 | U 4C4320F3 |
477 | F0 "Ethernet Phy" 60 |
478 | F1 "eth_phy.sch" 60 |
479 | F2 "ETH_RXC" O L 10850 1100 60 |
480 | F3 "ETH_RST_N" I L 10850 1200 60 |
481 | F4 "ETH_CRS" O L 10850 1300 60 |
482 | F5 "ETH_COL" O L 10850 1400 60 |
483 | F6 "ETH_MDIO" B L 10850 1500 60 |
484 | F7 "ETH_MDC" I L 10850 1600 60 |
485 | F8 "ETH_RXD[0..3]" O L 10850 1800 60 |
486 | F9 "ETH_RXDV" O L 10850 1900 60 |
487 | F10 "ETH_RXER" O L 10850 2000 60 |
488 | F11 "ETH_TXC" B L 10850 2100 60 |
489 | F12 "ETH_TXD[0..3]" I L 10850 2200 60 |
490 | F13 "ETH_TXEN" I L 10850 2300 60 |
491 | F14 "ETH_TXER" I L 10850 2400 60 |
492 | F15 "ETH_CLK" I L 10850 2500 60 |
493 | F16 "ETH_INT" O L 10850 950 60 |
494 | $EndSheet |
495 | $Sheet |
496 | S 3850 6550 1100 4000 |
497 | U 4C421DD3 |
498 | F0 "DDR Banks" 60 |
499 | F1 "DRAM.sch" 60 |
500 | F2 "M0_BA[0..1]" I R 4950 9100 60 |
501 | F3 "M1_BA[0..1]" I R 4950 7000 60 |
502 | F4 "M0_WE#" I R 4950 10400 60 |
503 | F5 "M0_RAS#" I R 4950 10250 60 |
504 | F6 "M1_RAS#" I R 4950 8200 60 |
505 | F7 "M1_WE#" I R 4950 8350 60 |
506 | F8 "M0_CAS#" I R 4950 10150 60 |
507 | F9 "M0_CKE" I R 4950 9800 60 |
508 | F10 "M0_CLK" I R 4950 9900 60 |
509 | F11 "M0_CLK#" I R 4950 10000 60 |
510 | F12 "M0_CS#" I R 4950 8750 60 |
511 | F13 "M1_CLK#" I R 4950 7950 60 |
512 | F14 "M1_CLK" I R 4950 7850 60 |
513 | F15 "M1_CKE" I R 4950 7750 60 |
514 | F16 "M1_CAS#" I R 4950 8100 60 |
515 | F17 "M0_DQ[0..15]" B R 4950 8900 60 |
516 | F18 "M0_UDM" I R 4950 9550 60 |
517 | F19 "M0_LDQS" I R 4950 9350 60 |
518 | F20 "M0_A[0..12]" I R 4950 9000 60 |
519 | F21 "M0_LDM" I R 4950 9650 60 |
520 | F22 "M0_UDQS" I R 4950 9250 60 |
521 | F23 "M1_UDQS" I R 4950 7200 60 |
522 | F24 "M1_LDM" I R 4950 7600 60 |
523 | F25 "M1_LDQS" I R 4950 7300 60 |
524 | F26 "M1_UDM" I R 4950 7500 60 |
525 | F27 "M1_CS#" I R 4950 6650 60 |
526 | F28 "M1_A[0..12]" I R 4950 6900 60 |
527 | F29 "M1_DQ[0..15]" B R 4950 6800 60 |
528 | $EndSheet |
529 | $EndSCHEMATC |
530 |
Branches:
master