Xué video camera
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Xué video camera Git Source Tree
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Source at commit 3e25e8d created 13 years 7 months ago. By Andres Calderon, ddr mobile replaced by ddr | |
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1 | EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT |
2 | LIBS:power |
3 | LIBS:device |
4 | LIBS:transistors |
5 | LIBS:conn |
6 | LIBS:linear |
7 | LIBS:regul |
8 | LIBS:74xx |
9 | LIBS:cmos4000 |
10 | LIBS:adc-dac |
11 | LIBS:memory |
12 | LIBS:xilinx |
13 | LIBS:special |
14 | LIBS:microcontrollers |
15 | LIBS:dsp |
16 | LIBS:microchip |
17 | LIBS:analog_switches |
18 | LIBS:motorola |
19 | LIBS:texas |
20 | LIBS:intel |
21 | LIBS:audio |
22 | LIBS:interface |
23 | LIBS:digital-audio |
24 | LIBS:philips |
25 | LIBS:display |
26 | LIBS:cypress |
27 | LIBS:siliconi |
28 | LIBS:opto |
29 | LIBS:atmel |
30 | LIBS:contrib |
31 | LIBS:valves |
32 | LIBS:micron_ddr_512Mb |
33 | LIBS:xue-rnc-cache |
34 | EELAYER 24 0 |
35 | EELAYER END |
36 | $Descr A4 11700 8267 |
37 | Sheet 1 5 |
38 | Title "" |
39 | Date "4 aug 2010" |
40 | Rev "" |
41 | Comp "" |
42 | Comment1 "" |
43 | Comment2 "" |
44 | Comment3 "" |
45 | Comment4 "" |
46 | $EndDescr |
47 | Wire Wire Line |
48 | 4000 2300 2750 2300 |
49 | Wire Wire Line |
50 | 2750 4350 4000 4350 |
51 | Wire Wire Line |
52 | 7800 4550 7350 4550 |
53 | Wire Bus Line |
54 | 4000 3300 4000 3250 |
55 | Wire Bus Line |
56 | 4000 3250 2750 3250 |
57 | Wire Bus Line |
58 | 4000 1200 4000 1150 |
59 | Wire Wire Line |
60 | 2750 4250 4000 4250 |
61 | Wire Wire Line |
62 | 2750 2200 4000 2200 |
63 | Wire Bus Line |
64 | 4000 1150 2750 1150 |
65 | $Sheet |
66 | S 7800 4450 1450 2200 |
67 | U 4C4320F3 |
68 | F0 "Ethernet Phy" 60 |
69 | F1 "eth_phy.sch" 60 |
70 | F2 "ETH_RXC" O L 7800 4700 60 |
71 | F3 "ETH_RST_N" I L 7800 4800 60 |
72 | F4 "ETH_CRS" O L 7800 4900 60 |
73 | F5 "ETH_COL" O L 7800 5000 60 |
74 | F6 "ETH_INT" O L 7800 4550 60 |
75 | F7 "ETH_MDIO" B L 7800 5100 60 |
76 | F8 "ETH_MDC" I L 7800 5200 60 |
77 | F9 "ETH_RXD[0..3]" O L 7800 5400 60 |
78 | F10 "ETH_RXDV" O L 7800 5500 60 |
79 | F11 "ETH_RXER" O L 7800 5600 60 |
80 | F12 "ETH_TXC" B L 7800 5700 60 |
81 | F13 "ETH_TXD[0..3]" I L 7800 5800 60 |
82 | F14 "ETH_TXEN" I L 7800 5900 60 |
83 | F15 "ETH_TXER" I L 7800 6000 60 |
84 | F16 "ETH_CLK" I L 7800 6100 60 |
85 | $EndSheet |
86 | $Sheet |
87 | S 4000 900 3350 5800 |
88 | U 4C431A63 |
89 | F0 "FPGA Spartan6" 60 |
90 | F1 "FPGA.sch" 60 |
91 | F2 "M1_CLK" O L 4000 2200 60 |
92 | F3 "M1_CLK#" O L 4000 2300 60 |
93 | F4 "M0_CLK" O L 4000 4250 60 |
94 | F5 "M0_CLK#" O L 4000 4350 60 |
95 | F6 "ETH_INT" I R 7350 4550 60 |
96 | $EndSheet |
97 | $Sheet |
98 | S 8700 900 1150 1850 |
99 | U 4C4227FE |
100 | F0 "Non volatile memories" 60 |
101 | F1 "NV_MEMORIES.sch" 60 |
102 | $EndSheet |
103 | $Sheet |
104 | S 1650 900 1100 4000 |
105 | U 4C421DD3 |
106 | F0 "DDR Banks" 60 |
107 | F1 "DRAM.sch" 60 |
108 | F2 "M0_BA[0..1]" I R 2750 3450 60 |
109 | F3 "M1_BA[0..1]" I R 2750 1350 60 |
110 | F4 "M0_WE#" I R 2750 4750 60 |
111 | F5 "M0_RAS#" I R 2750 4600 60 |
112 | F6 "M1_RAS#" I R 2750 2550 60 |
113 | F7 "M1_WE#" I R 2750 2700 60 |
114 | F8 "M0_CAS#" I R 2750 4500 60 |
115 | F9 "M0_CKE" I R 2750 4150 60 |
116 | F10 "M0_CLK" I R 2750 4250 60 |
117 | F11 "M0_CLK#" I R 2750 4350 60 |
118 | F12 "M0_CS#" I R 2750 3100 60 |
119 | F13 "M1_CLK#" I R 2750 2300 60 |
120 | F14 "M1_CLK" I R 2750 2200 60 |
121 | F15 "M1_CKE" I R 2750 2100 60 |
122 | F16 "M1_CAS#" I R 2750 2450 60 |
123 | F17 "M0_DQ[0..15]" B R 2750 3250 60 |
124 | F18 "M0_UDM" I R 2750 3900 60 |
125 | F19 "M0_LDQS" I R 2750 3700 60 |
126 | F20 "M0_A[0..12]" I R 2750 3350 60 |
127 | F21 "M0_LDM" I R 2750 4000 60 |
128 | F22 "M0_UDQS" I R 2750 3600 60 |
129 | F23 "M1_UDQS" I R 2750 1550 60 |
130 | F24 "M1_LDM" I R 2750 1950 60 |
131 | F25 "M1_LDQS" I R 2750 1650 60 |
132 | F26 "M1_UDM" I R 2750 1850 60 |
133 | F27 "M1_CS#" I R 2750 1000 60 |
134 | F28 "M1_A[0..12]" I R 2750 1250 60 |
135 | F29 "M1_DQ[0..15]" B R 2750 1150 60 |
136 | $EndSheet |
137 | $EndSCHEMATC |
138 |
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