Root/kicad/xue-rnc/xue-rnc.sch

Source at commit 3e25e8d created 13 years 7 months ago.
By Andres Calderon, ddr mobile replaced by ddr
1EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
2LIBS:power
3LIBS:device
4LIBS:transistors
5LIBS:conn
6LIBS:linear
7LIBS:regul
8LIBS:74xx
9LIBS:cmos4000
10LIBS:adc-dac
11LIBS:memory
12LIBS:xilinx
13LIBS:special
14LIBS:microcontrollers
15LIBS:dsp
16LIBS:microchip
17LIBS:analog_switches
18LIBS:motorola
19LIBS:texas
20LIBS:intel
21LIBS:audio
22LIBS:interface
23LIBS:digital-audio
24LIBS:philips
25LIBS:display
26LIBS:cypress
27LIBS:siliconi
28LIBS:opto
29LIBS:atmel
30LIBS:contrib
31LIBS:valves
32LIBS:micron_ddr_512Mb
33LIBS:xue-rnc-cache
34EELAYER 24 0
35EELAYER END
36$Descr A4 11700 8267
37Sheet 1 5
38Title ""
39Date "4 aug 2010"
40Rev ""
41Comp ""
42Comment1 ""
43Comment2 ""
44Comment3 ""
45Comment4 ""
46$EndDescr
47Wire Wire Line
48    4000 2300 2750 2300
49Wire Wire Line
50    2750 4350 4000 4350
51Wire Wire Line
52    7800 4550 7350 4550
53Wire Bus Line
54    4000 3300 4000 3250
55Wire Bus Line
56    4000 3250 2750 3250
57Wire Bus Line
58    4000 1200 4000 1150
59Wire Wire Line
60    2750 4250 4000 4250
61Wire Wire Line
62    2750 2200 4000 2200
63Wire Bus Line
64    4000 1150 2750 1150
65$Sheet
66S 7800 4450 1450 2200
67U 4C4320F3
68F0 "Ethernet Phy" 60
69F1 "eth_phy.sch" 60
70F2 "ETH_RXC" O L 7800 4700 60
71F3 "ETH_RST_N" I L 7800 4800 60
72F4 "ETH_CRS" O L 7800 4900 60
73F5 "ETH_COL" O L 7800 5000 60
74F6 "ETH_INT" O L 7800 4550 60
75F7 "ETH_MDIO" B L 7800 5100 60
76F8 "ETH_MDC" I L 7800 5200 60
77F9 "ETH_RXD[0..3]" O L 7800 5400 60
78F10 "ETH_RXDV" O L 7800 5500 60
79F11 "ETH_RXER" O L 7800 5600 60
80F12 "ETH_TXC" B L 7800 5700 60
81F13 "ETH_TXD[0..3]" I L 7800 5800 60
82F14 "ETH_TXEN" I L 7800 5900 60
83F15 "ETH_TXER" I L 7800 6000 60
84F16 "ETH_CLK" I L 7800 6100 60
85$EndSheet
86$Sheet
87S 4000 900 3350 5800
88U 4C431A63
89F0 "FPGA Spartan6" 60
90F1 "FPGA.sch" 60
91F2 "M1_CLK" O L 4000 2200 60
92F3 "M1_CLK#" O L 4000 2300 60
93F4 "M0_CLK" O L 4000 4250 60
94F5 "M0_CLK#" O L 4000 4350 60
95F6 "ETH_INT" I R 7350 4550 60
96$EndSheet
97$Sheet
98S 8700 900 1150 1850
99U 4C4227FE
100F0 "Non volatile memories" 60
101F1 "NV_MEMORIES.sch" 60
102$EndSheet
103$Sheet
104S 1650 900 1100 4000
105U 4C421DD3
106F0 "DDR Banks" 60
107F1 "DRAM.sch" 60
108F2 "M0_BA[0..1]" I R 2750 3450 60
109F3 "M1_BA[0..1]" I R 2750 1350 60
110F4 "M0_WE#" I R 2750 4750 60
111F5 "M0_RAS#" I R 2750 4600 60
112F6 "M1_RAS#" I R 2750 2550 60
113F7 "M1_WE#" I R 2750 2700 60
114F8 "M0_CAS#" I R 2750 4500 60
115F9 "M0_CKE" I R 2750 4150 60
116F10 "M0_CLK" I R 2750 4250 60
117F11 "M0_CLK#" I R 2750 4350 60
118F12 "M0_CS#" I R 2750 3100 60
119F13 "M1_CLK#" I R 2750 2300 60
120F14 "M1_CLK" I R 2750 2200 60
121F15 "M1_CKE" I R 2750 2100 60
122F16 "M1_CAS#" I R 2750 2450 60
123F17 "M0_DQ[0..15]" B R 2750 3250 60
124F18 "M0_UDM" I R 2750 3900 60
125F19 "M0_LDQS" I R 2750 3700 60
126F20 "M0_A[0..12]" I R 2750 3350 60
127F21 "M0_LDM" I R 2750 4000 60
128F22 "M0_UDQS" I R 2750 3600 60
129F23 "M1_UDQS" I R 2750 1550 60
130F24 "M1_LDM" I R 2750 1950 60
131F25 "M1_LDQS" I R 2750 1650 60
132F26 "M1_UDM" I R 2750 1850 60
133F27 "M1_CS#" I R 2750 1000 60
134F28 "M1_A[0..12]" I R 2750 1250 60
135F29 "M1_DQ[0..15]" B R 2750 1150 60
136$EndSheet
137$EndSCHEMATC
138

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