Root/kicad/xue-rnc/xue-rnc.sch

Source at commit cac88e3 created 13 years 7 months ago.
By Andres Calderon, DDR de-coupling caps. added
1EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT
2LIBS:power
3LIBS:v0402mhs03
4LIBS:usb-48204-0001
5LIBS:microsmd075f
6LIBS:mic2550ayts
7LIBS:rj45-48025
8LIBS:xue-nv
9LIBS:xc6slx75fgg484
10LIBS:xc6slx45fgg484
11LIBS:micron_mobile_ddr
12LIBS:micron_ddr_512Mb
13LIBS:k8001
14LIBS:device
15LIBS:transistors
16LIBS:conn
17LIBS:linear
18LIBS:regul
19LIBS:74xx
20LIBS:cmos4000
21LIBS:adc-dac
22LIBS:memory
23LIBS:xilinx
24LIBS:special
25LIBS:microcontrollers
26LIBS:dsp
27LIBS:microchip
28LIBS:analog_switches
29LIBS:motorola
30LIBS:texas
31LIBS:intel
32LIBS:audio
33LIBS:interface
34LIBS:digital-audio
35LIBS:philips
36LIBS:display
37LIBS:cypress
38LIBS:siliconi
39LIBS:opto
40LIBS:atmel
41LIBS:contrib
42LIBS:valves
43LIBS:pasives-connectors
44LIBS:xue-rnc-cache
45EELAYER 24 0
46EELAYER END
47$Descr A3 16535 11700
48Sheet 1 6
49Title ""
50Date "10 aug 2010"
51Rev ""
52Comp ""
53Comment1 ""
54Comment2 ""
55Comment3 ""
56Comment4 ""
57$EndDescr
58Wire Bus Line
59    10600 7200 9300 7200
60Wire Bus Line
61    9300 7600 10600 7600
62Wire Wire Line
63    10650 5300 9300 5300
64Wire Wire Line
65    10650 5100 9300 5100
66Wire Wire Line
67    9300 7900 10600 7900
68Wire Wire Line
69    9300 7700 10600 7700
70Wire Wire Line
71    9300 7500 10600 7500
72Wire Wire Line
73    9300 7300 10600 7300
74Wire Wire Line
75    9300 7000 10600 7000
76Wire Wire Line
77    9300 6800 10600 6800
78Wire Wire Line
79    9300 6600 10600 6600
80Wire Wire Line
81    9300 6350 10600 6350
82Wire Bus Line
83    4700 2950 5950 2950
84Wire Wire Line
85    4700 3350 5950 3350
86Wire Wire Line
87    4700 3450 5950 3450
88Wire Wire Line
89    4700 3650 5950 3650
90Wire Wire Line
91    4700 4500 5950 4500
92Wire Wire Line
93    4700 4350 5950 4350
94Wire Wire Line
95    4700 4900 5950 4900
96Wire Wire Line
97    4700 6400 5950 6400
98Wire Wire Line
99    4700 5500 5950 5500
100Wire Wire Line
101    4700 5800 5950 5800
102Wire Bus Line
103    4700 5150 5950 5150
104Wire Wire Line
105    4700 4000 5950 4000
106Wire Wire Line
107    4700 6050 5950 6050
108Wire Bus Line
109    4700 5050 5950 5050
110Wire Bus Line
111    5950 5050 5950 5100
112Wire Wire Line
113    4700 6150 5950 6150
114Wire Wire Line
115    5950 4100 4700 4100
116Wire Bus Line
117    4700 3050 5950 3050
118Wire Wire Line
119    4700 5400 5950 5400
120Wire Wire Line
121    4700 5700 5950 5700
122Wire Wire Line
123    4700 6300 5950 6300
124Wire Bus Line
125    4700 5250 5950 5250
126Wire Wire Line
127    4700 6550 5950 6550
128Wire Wire Line
129    4700 5950 5950 5950
130Wire Wire Line
131    4700 4250 5950 4250
132Wire Wire Line
133    4700 3900 5950 3900
134Wire Wire Line
135    4700 3750 5950 3750
136Wire Wire Line
137    4700 2800 5950 2800
138Wire Bus Line
139    4700 3150 5950 3150
140Wire Wire Line
141    9300 6500 10600 6500
142Wire Wire Line
143    9300 6700 10600 6700
144Wire Wire Line
145    10600 6900 9300 6900
146Wire Wire Line
147    9300 7400 10600 7400
148Wire Wire Line
149    9300 7800 10600 7800
150Wire Wire Line
151    10650 5000 9300 5000
152Wire Wire Line
153    10650 5200 9300 5200
154Wire Wire Line
155    10650 5400 9300 5400
156$Sheet
157S 5950 2700 3350 5800
158U 4C431A63
159F0 "FPGA Spartan6" 60
160F1 "FPGA.sch" 60
161F2 "M1_CLK" O L 5950 4000 60
162F3 "M1_CLK#" O L 5950 4100 60
163F4 "M0_CLK" O L 5950 6050 60
164F5 "M0_CLK#" O L 5950 6150 60
165F6 "M0_A[0..12]" O L 5950 5150 60
166F7 "M1_A[0..12]" O L 5950 3050 60
167F8 "M0_DQ[0..15]" B L 5950 5050 60
168F9 "M0_UDQS" O L 5950 5400 60
169F10 "M0_LDM" O L 5950 5800 60
170F11 "M0_LDQS" O L 5950 5500 60
171F12 "M0_UDM" O L 5950 5700 60
172F13 "M0_RAS#" O L 5950 6400 60
173F14 "M0_WE#" O L 5950 6550 60
174F15 "M0_CKE" O L 5950 5950 60
175F16 "M0_CAS#" O L 5950 6300 60
176F17 "M1_CAS#" O L 5950 4250 60
177F18 "M1_CKE" O L 5950 3900 60
178F19 "M0_CS#" O L 5950 4900 60
179F20 "M1_CS#" O L 5950 2800 60
180F21 "M1_WE#" O L 5950 4500 60
181F22 "M1_RAS#" O L 5950 4350 60
182F23 "M1_UDM" O L 5950 3650 60
183F24 "M1_LDQS" O L 5950 3450 60
184F25 "M1_LDM" O L 5950 3750 60
185F26 "M1_UDQS" O L 5950 3350 60
186F27 "M1_DQ[0..15]" B L 5950 2950 60
187F28 "M1_BA[0..1]" O L 5950 3150 60
188F29 "M0_BA[0..1]" O L 5950 5250 60
189F30 "USBA_VM" B R 9300 5400 60
190F31 "USBA_VP" B R 9300 5300 60
191F32 "USBA_RCV" B R 9300 5200 60
192F33 "USBA_OE_N" B R 9300 5100 60
193F34 "USBA_SPD" B R 9300 5000 60
194F35 "ETH_CLK" B R 9300 7900 60
195F36 "ETH_RXC" B R 9300 6500 60
196F37 "ETH_TXC" B R 9300 7500 60
197F38 "ETH_TXD[0..3]" O R 9300 7600 60
198F39 "ETH_TXEN" B R 9300 7700 60
199F40 "ETH_TXER" B R 9300 7800 60
200F41 "ETH_RXER" B R 9300 7400 60
201F42 "ETH_RXDV" B R 9300 7300 60
202F43 "ETH_RXD[0..3]" I R 9300 7200 60
203F44 "ETH_RESET_N" B R 9300 6600 60
204F45 "ETH_MDIO" B R 9300 6900 60
205F46 "ETH_MDC" B R 9300 7000 60
206F47 "ETH_INT" B R 9300 6350 60
207$EndSheet
208Text HLabel 10650 5400 2 60 BiDi ~ 0
209USBA_VM
210Text HLabel 10650 5300 2 60 BiDi ~ 0
211USBA_VP
212Text HLabel 10650 5200 2 60 BiDi ~ 0
213USBA_RCV
214Text HLabel 10650 5100 2 60 BiDi ~ 0
215USBA_OE_N
216Text HLabel 10650 5000 2 60 BiDi ~ 0
217USBA_SPD
218$Sheet
219S 10650 4900 1150 650
220U 4C5F1EDC
221F0 "USB" 60
222F1 "USB.sch" 60
223$EndSheet
224$Sheet
225S 10600 6250 1300 1800
226U 4C4320F3
227F0 "Ethernet Phy" 60
228F1 "eth_phy.sch" 60
229F2 "ETH_RXC" O L 10600 6500 60
230F3 "ETH_RST_N" I L 10600 6600 60
231F4 "ETH_CRS" O L 10600 6700 60
232F5 "ETH_COL" O L 10600 6800 60
233F6 "ETH_MDIO" B L 10600 6900 60
234F7 "ETH_MDC" I L 10600 7000 60
235F8 "ETH_RXD[0..3]" O L 10600 7200 60
236F9 "ETH_RXDV" O L 10600 7300 60
237F10 "ETH_RXER" O L 10600 7400 60
238F11 "ETH_TXC" B L 10600 7500 60
239F12 "ETH_TXD[0..3]" I L 10600 7600 60
240F13 "ETH_TXEN" I L 10600 7700 60
241F14 "ETH_TXER" I L 10600 7800 60
242F15 "ETH_CLK" I L 10600 7900 60
243F16 "ETH_INT" O L 10600 6350 60
244$EndSheet
245$Sheet
246S 10650 2700 1150 1850
247U 4C4227FE
248F0 "Non volatile memories" 60
249F1 "NV_MEMORIES.sch" 60
250$EndSheet
251$Sheet
252S 3600 2700 1100 4000
253U 4C421DD3
254F0 "DDR Banks" 60
255F1 "DRAM.sch" 60
256F2 "M0_BA[0..1]" I R 4700 5250 60
257F3 "M1_BA[0..1]" I R 4700 3150 60
258F4 "M0_WE#" I R 4700 6550 60
259F5 "M0_RAS#" I R 4700 6400 60
260F6 "M1_RAS#" I R 4700 4350 60
261F7 "M1_WE#" I R 4700 4500 60
262F8 "M0_CAS#" I R 4700 6300 60
263F9 "M0_CKE" I R 4700 5950 60
264F10 "M0_CLK" I R 4700 6050 60
265F11 "M0_CLK#" I R 4700 6150 60
266F12 "M0_CS#" I R 4700 4900 60
267F13 "M1_CLK#" I R 4700 4100 60
268F14 "M1_CLK" I R 4700 4000 60
269F15 "M1_CKE" I R 4700 3900 60
270F16 "M1_CAS#" I R 4700 4250 60
271F17 "M0_DQ[0..15]" B R 4700 5050 60
272F18 "M0_UDM" I R 4700 5700 60
273F19 "M0_LDQS" I R 4700 5500 60
274F20 "M0_A[0..12]" I R 4700 5150 60
275F21 "M0_LDM" I R 4700 5800 60
276F22 "M0_UDQS" I R 4700 5400 60
277F23 "M1_UDQS" I R 4700 3350 60
278F24 "M1_LDM" I R 4700 3750 60
279F25 "M1_LDQS" I R 4700 3450 60
280F26 "M1_UDM" I R 4700 3650 60
281F27 "M1_CS#" I R 4700 2800 60
282F28 "M1_A[0..12]" I R 4700 3050 60
283F29 "M1_DQ[0..15]" B R 4700 2950 60
284$EndSheet
285$EndSCHEMATC
286

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