Xué video camera
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Xué video camera Git Source Tree
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Source at commit cb21a9a99fad714fd7d56ca88741174ca2c263e9 created 13 years 6 months ago. By Juan64Bits, Routing current sensors. | |
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1 | EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT |
2 | LIBS:power |
3 | LIBS:r_pack2 |
4 | LIBS:v0402mhs03 |
5 | LIBS:usb-48204-0001 |
6 | LIBS:microsmd075f |
7 | LIBS:mic2550 |
8 | LIBS:rj45-48025 |
9 | LIBS:xue-nv |
10 | LIBS:xc6slx75fgg484 |
11 | LIBS:xc6slx45fgg484 |
12 | LIBS:micron_mobile_ddr |
13 | LIBS:micron_ddr_512Mb |
14 | LIBS:k8001 |
15 | LIBS:device |
16 | LIBS:transistors |
17 | LIBS:conn |
18 | LIBS:linear |
19 | LIBS:regul |
20 | LIBS:74xx |
21 | LIBS:cmos4000 |
22 | LIBS:adc-dac |
23 | LIBS:memory |
24 | LIBS:xilinx |
25 | LIBS:special |
26 | LIBS:microcontrollers |
27 | LIBS:dsp |
28 | LIBS:microchip |
29 | LIBS:analog_switches |
30 | LIBS:motorola |
31 | LIBS:texas |
32 | LIBS:intel |
33 | LIBS:audio |
34 | LIBS:interface |
35 | LIBS:digital-audio |
36 | LIBS:philips |
37 | LIBS:display |
38 | LIBS:cypress |
39 | LIBS:siliconi |
40 | LIBS:opto |
41 | LIBS:atmel |
42 | LIBS:contrib |
43 | LIBS:valves |
44 | LIBS:pasives-connectors |
45 | LIBS:x25x64mb |
46 | LIBS:attiny |
47 | LIBS:PSU |
48 | LIBS:xue-rnc-cache |
49 | EELAYER 24 0 |
50 | EELAYER END |
51 | $Descr A3 16535 11700 |
52 | Sheet 1 9 |
53 | Title "" |
54 | Date "3 sep 2010" |
55 | Rev "" |
56 | Comp "" |
57 | Comment1 "" |
58 | Comment2 "" |
59 | Comment3 "" |
60 | Comment4 "" |
61 | $EndDescr |
62 | $Sheet |
63 | S 5950 5150 3350 4150 |
64 | U 4C7BC2B2 |
65 | F0 "FPGA, Port0, Port2, PROG IF" 60 |
66 | F1 "FPGA_0_2_PROG.sch" 60 |
67 | F2 "S6_TCK" I L 5950 6450 60 |
68 | F3 "S6_TDI" I L 5950 6550 60 |
69 | F4 "S6_TDO" O L 5950 6650 60 |
70 | F5 "S6_TMS" I L 5950 6750 60 |
71 | F6 "PROG_MISO[0..3]" B R 9300 9150 60 |
72 | F7 "PROG_CCLK" O R 9300 9050 60 |
73 | F8 "PROG_CSO" O R 9300 8950 60 |
74 | F9 "NF_D[0..7]" B R 9300 8700 60 |
75 | F10 "ETH_COL" B R 9300 5850 60 |
76 | F11 "ETH_CRS" B R 9300 5750 60 |
77 | F12 "NF_WE_N" O R 9300 8400 60 |
78 | F13 "NF_ALE" O R 9300 8200 60 |
79 | F14 "NF_CLE" O R 9300 8300 60 |
80 | F15 "NF_CS1_N" O R 9300 8100 60 |
81 | F16 "NF_RE_N" O R 9300 8500 60 |
82 | F17 "NF_RNB" B R 9300 8600 60 |
83 | F18 "SD_CLK" B R 9300 7550 60 |
84 | F19 "SD_CMD" B R 9300 7650 60 |
85 | F20 "SD_DAT[0..3]" B R 9300 7750 60 |
86 | F21 "ETH_CLK" B R 9300 6950 60 |
87 | F22 "ETH_RXC" B R 9300 5550 60 |
88 | F23 "ETH_TXC" B R 9300 6550 60 |
89 | F24 "ETH_TXD[0..3]" O R 9300 6650 60 |
90 | F25 "ETH_TXEN" B R 9300 6750 60 |
91 | F26 "ETH_TXER" B R 9300 6850 60 |
92 | F27 "ETH_RXER" B R 9300 6450 60 |
93 | F28 "ETH_RXDV" B R 9300 6350 60 |
94 | F29 "ETH_RXD[0..3]" I R 9300 6250 60 |
95 | F30 "ETH_RESET_N" B R 9300 5650 60 |
96 | F31 "ETH_MDIO" B R 9300 5950 60 |
97 | F32 "ETH_MDC" B R 9300 6050 60 |
98 | F33 "ETH_INT" B R 9300 5400 60 |
99 | $EndSheet |
100 | $Sheet |
101 | S 5950 700 3300 4200 |
102 | U 4C7BC2A2 |
103 | F0 "FPGA Port 1, Port 3 (DDR, USB)" 60 |
104 | F1 "FPGA_1_3.sch" 60 |
105 | F2 "USBD_VP" B R 9250 1850 60 |
106 | F3 "USBD_SPD" B R 9250 1550 60 |
107 | F4 "USBD_OE_N" B R 9250 1650 60 |
108 | F5 "USBD_RCV" B R 9250 1750 60 |
109 | F6 "USBD_VM" B R 9250 1950 60 |
110 | F7 "M0_CKE" O L 5950 4100 60 |
111 | F8 "M0_UDM" O L 5950 3850 60 |
112 | F9 "M0_UDQS" O L 5950 3550 60 |
113 | F10 "M0_BA[0..1]" O L 5950 3400 60 |
114 | F11 "M0_CAS#" O L 5950 4450 60 |
115 | F12 "M0_RAS#" O L 5950 4550 60 |
116 | F13 "M0_WE#" O L 5950 4700 60 |
117 | F14 "M0_LDM" O L 5950 3950 60 |
118 | F15 "M0_LDQS" O L 5950 3650 60 |
119 | F16 "M1_UDQS" O L 5950 1500 60 |
120 | F17 "M1_UDM" O L 5950 1800 60 |
121 | F18 "M1_LDQS" O L 5950 1600 60 |
122 | F19 "M1_LDM" O L 5950 1900 60 |
123 | F20 "M1_WE#" O L 5950 2650 60 |
124 | F21 "M1_CKE" O L 5950 2050 60 |
125 | F22 "M1_RAS#" O L 5950 2500 60 |
126 | F23 "M1_CAS#" O L 5950 2400 60 |
127 | F24 "M1_BA[0..1]" O L 5950 1300 60 |
128 | F25 "M1_CS#" O L 5950 950 60 |
129 | F26 "USBA_VM" B R 9250 1350 60 |
130 | F27 "USBA_VP" B R 9250 1250 60 |
131 | F28 "USBA_RCV" B R 9250 1150 60 |
132 | F29 "USBA_OE_N" B R 9250 1050 60 |
133 | F30 "USBA_SPD" B R 9250 950 60 |
134 | F31 "M1_DQ[0..15]" B L 5950 1100 60 |
135 | F32 "M0_CS#" O L 5950 3050 60 |
136 | F33 "M0_DQ[0..15]" B L 5950 3200 60 |
137 | F34 "M0_A[0..12]" O L 5950 3300 60 |
138 | F35 "M1_A[0..12]" O L 5950 1200 60 |
139 | F36 "M1_CLK" O L 5950 2150 60 |
140 | F37 "M1_CLK#" O L 5950 2250 60 |
141 | F38 "M0_CLK" O L 5950 4200 60 |
142 | F39 "M0_CLK#" O L 5950 4300 60 |
143 | $EndSheet |
144 | Wire Wire Line |
145 | 10600 1950 9250 1950 |
146 | Wire Wire Line |
147 | 10600 1750 9250 1750 |
148 | Wire Wire Line |
149 | 10600 1550 9250 1550 |
150 | Wire Wire Line |
151 | 4950 6650 5950 6650 |
152 | Wire Wire Line |
153 | 5950 6450 4950 6450 |
154 | Wire Bus Line |
155 | 10650 9150 9300 9150 |
156 | Wire Wire Line |
157 | 10650 8100 9300 8100 |
158 | Wire Wire Line |
159 | 10650 8500 9300 8500 |
160 | Wire Wire Line |
161 | 9300 8200 10650 8200 |
162 | Wire Wire Line |
163 | 10600 5850 9300 5850 |
164 | Wire Bus Line |
165 | 9300 7750 10650 7750 |
166 | Wire Wire Line |
167 | 9300 7550 10650 7550 |
168 | Wire Wire Line |
169 | 10600 1350 9250 1350 |
170 | Wire Wire Line |
171 | 10600 1150 9250 1150 |
172 | Wire Wire Line |
173 | 10600 950 9250 950 |
174 | Wire Wire Line |
175 | 9300 6850 10600 6850 |
176 | Wire Wire Line |
177 | 9300 6450 10600 6450 |
178 | Wire Wire Line |
179 | 10600 5950 9300 5950 |
180 | Wire Wire Line |
181 | 9300 5550 10600 5550 |
182 | Wire Bus Line |
183 | 4700 1300 5950 1300 |
184 | Wire Wire Line |
185 | 4700 950 5950 950 |
186 | Wire Wire Line |
187 | 4700 1900 5950 1900 |
188 | Wire Wire Line |
189 | 4700 2050 5950 2050 |
190 | Wire Wire Line |
191 | 4700 2400 5950 2400 |
192 | Wire Wire Line |
193 | 4700 4100 5950 4100 |
194 | Wire Wire Line |
195 | 4700 4700 5950 4700 |
196 | Wire Bus Line |
197 | 4700 3400 5950 3400 |
198 | Wire Wire Line |
199 | 4700 4450 5950 4450 |
200 | Wire Wire Line |
201 | 4700 3850 5950 3850 |
202 | Wire Wire Line |
203 | 4700 3550 5950 3550 |
204 | Wire Bus Line |
205 | 4700 1200 5950 1200 |
206 | Wire Wire Line |
207 | 5950 2250 4700 2250 |
208 | Wire Wire Line |
209 | 4700 4300 5950 4300 |
210 | Wire Bus Line |
211 | 5950 3250 5950 3200 |
212 | Wire Bus Line |
213 | 5950 3200 4700 3200 |
214 | Wire Wire Line |
215 | 4700 4200 5950 4200 |
216 | Wire Wire Line |
217 | 4700 2150 5950 2150 |
218 | Wire Bus Line |
219 | 4700 3300 5950 3300 |
220 | Wire Wire Line |
221 | 4700 3950 5950 3950 |
222 | Wire Wire Line |
223 | 4700 3650 5950 3650 |
224 | Wire Wire Line |
225 | 4700 4550 5950 4550 |
226 | Wire Wire Line |
227 | 4700 3050 5950 3050 |
228 | Wire Wire Line |
229 | 4700 2500 5950 2500 |
230 | Wire Wire Line |
231 | 4700 2650 5950 2650 |
232 | Wire Wire Line |
233 | 4700 1800 5950 1800 |
234 | Wire Wire Line |
235 | 4700 1600 5950 1600 |
236 | Wire Wire Line |
237 | 4700 1500 5950 1500 |
238 | Wire Bus Line |
239 | 4700 1100 5950 1100 |
240 | Wire Wire Line |
241 | 9300 5400 10600 5400 |
242 | Wire Wire Line |
243 | 9300 5650 10600 5650 |
244 | Wire Wire Line |
245 | 9300 6050 10600 6050 |
246 | Wire Wire Line |
247 | 9300 6350 10600 6350 |
248 | Wire Wire Line |
249 | 9300 6550 10600 6550 |
250 | Wire Wire Line |
251 | 9300 6750 10600 6750 |
252 | Wire Wire Line |
253 | 9300 6950 10600 6950 |
254 | Wire Wire Line |
255 | 10600 1050 9250 1050 |
256 | Wire Wire Line |
257 | 10600 1250 9250 1250 |
258 | Wire Bus Line |
259 | 9300 6650 10600 6650 |
260 | Wire Bus Line |
261 | 10600 6250 9300 6250 |
262 | Wire Wire Line |
263 | 9300 7650 10650 7650 |
264 | Wire Wire Line |
265 | 10600 5750 9300 5750 |
266 | Wire Bus Line |
267 | 10650 8700 9300 8700 |
268 | Wire Wire Line |
269 | 10650 8300 9300 8300 |
270 | Wire Wire Line |
271 | 10650 8400 9300 8400 |
272 | Wire Wire Line |
273 | 10650 8600 9300 8600 |
274 | Wire Wire Line |
275 | 10650 8950 9300 8950 |
276 | Wire Wire Line |
277 | 10650 9050 9300 9050 |
278 | Wire Wire Line |
279 | 5950 6550 4950 6550 |
280 | Wire Wire Line |
281 | 5950 6750 4950 6750 |
282 | Wire Wire Line |
283 | 10600 1650 9250 1650 |
284 | Wire Wire Line |
285 | 10600 1850 9250 1850 |
286 | $Sheet |
287 | S 3750 6400 1200 700 |
288 | U 4C716A4D |
289 | F0 "DBG_PRG" 60 |
290 | F1 "DBG_PRG.sch" 60 |
291 | F2 "FPGA_TDO" B R 4950 6650 60 |
292 | F3 "FPGA_TDI" B R 4950 6550 60 |
293 | F4 "FPGA_TMS" B R 4950 6750 60 |
294 | F5 "FPGA_TCK" B R 4950 6450 60 |
295 | $EndSheet |
296 | $Sheet |
297 | S 3750 8000 1100 1300 |
298 | U 4C69ED5F |
299 | F0 "PSU" 60 |
300 | F1 "PSU.sch" 60 |
301 | $EndSheet |
302 | $Sheet |
303 | S 10650 7350 1050 1950 |
304 | U 4C4227FE |
305 | F0 "Non volatile memories" 60 |
306 | F1 "NV_MEMORIES.sch" 60 |
307 | F2 "SD_CMD" I L 10650 7650 60 |
308 | F3 "SD_CLK" I L 10650 7550 60 |
309 | F4 "SD_DAT[0..3]" B L 10650 7750 60 |
310 | F5 "NF_D[0..7]" B L 10650 8700 60 |
311 | F6 "NF_ALE" B L 10650 8200 60 |
312 | F7 "NF_CLE" B L 10650 8300 60 |
313 | F8 "NF_WE_N" B L 10650 8400 60 |
314 | F9 "NF_CS1_N" B L 10650 8100 60 |
315 | F10 "NF_RE_N" B L 10650 8500 60 |
316 | F11 "NF_RNB" B L 10650 8600 60 |
317 | F12 "SPI_CLK" I L 10650 9050 60 |
318 | F13 "SPI_FLASH_CS#" I L 10650 8950 60 |
319 | F14 "SPI_DQ[0..3]" B L 10650 9150 60 |
320 | $EndSheet |
321 | $Sheet |
322 | S 10600 900 1100 1150 |
323 | U 4C5F1EDC |
324 | F0 "USB" 60 |
325 | F1 "USB.sch" 60 |
326 | F2 "USBA_SPD" B L 10600 950 60 |
327 | F3 "USBA_OE_N" B L 10600 1050 60 |
328 | F4 "USBA_RCV" B L 10600 1150 60 |
329 | F5 "USBA_VP" B L 10600 1250 60 |
330 | F6 "USBA_VM" B L 10600 1350 60 |
331 | F7 "USBD_SPD" B L 10600 1550 60 |
332 | F8 "USBD_OE_N" B L 10600 1650 60 |
333 | F9 "USBD_RCV" B L 10600 1750 60 |
334 | F10 "USBD_VP" B L 10600 1850 60 |
335 | F11 "USBD_VM" B L 10600 1950 60 |
336 | $EndSheet |
337 | Text Notes 12850 10750 0 60 ~ 0 |
338 | Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com |
339 | $Sheet |
340 | S 10600 5300 1300 1800 |
341 | U 4C4320F3 |
342 | F0 "Ethernet Phy" 60 |
343 | F1 "eth_phy.sch" 60 |
344 | F2 "ETH_RXC" O L 10600 5550 60 |
345 | F3 "ETH_RST_N" I L 10600 5650 60 |
346 | F4 "ETH_CRS" O L 10600 5750 60 |
347 | F5 "ETH_COL" O L 10600 5850 60 |
348 | F6 "ETH_MDIO" B L 10600 5950 60 |
349 | F7 "ETH_MDC" I L 10600 6050 60 |
350 | F8 "ETH_RXD[0..3]" O L 10600 6250 60 |
351 | F9 "ETH_RXDV" O L 10600 6350 60 |
352 | F10 "ETH_RXER" O L 10600 6450 60 |
353 | F11 "ETH_TXC" B L 10600 6550 60 |
354 | F12 "ETH_TXD[0..3]" I L 10600 6650 60 |
355 | F13 "ETH_TXEN" I L 10600 6750 60 |
356 | F14 "ETH_TXER" I L 10600 6850 60 |
357 | F15 "ETH_CLK" I L 10600 6950 60 |
358 | F16 "ETH_INT" O L 10600 5400 60 |
359 | $EndSheet |
360 | $Sheet |
361 | S 3600 850 1100 4000 |
362 | U 4C421DD3 |
363 | F0 "DDR Banks" 60 |
364 | F1 "DRAM.sch" 60 |
365 | F2 "M0_BA[0..1]" I R 4700 3400 60 |
366 | F3 "M1_BA[0..1]" I R 4700 1300 60 |
367 | F4 "M0_WE#" I R 4700 4700 60 |
368 | F5 "M0_RAS#" I R 4700 4550 60 |
369 | F6 "M1_RAS#" I R 4700 2500 60 |
370 | F7 "M1_WE#" I R 4700 2650 60 |
371 | F8 "M0_CAS#" I R 4700 4450 60 |
372 | F9 "M0_CKE" I R 4700 4100 60 |
373 | F10 "M0_CLK" I R 4700 4200 60 |
374 | F11 "M0_CLK#" I R 4700 4300 60 |
375 | F12 "M0_CS#" I R 4700 3050 60 |
376 | F13 "M1_CLK#" I R 4700 2250 60 |
377 | F14 "M1_CLK" I R 4700 2150 60 |
378 | F15 "M1_CKE" I R 4700 2050 60 |
379 | F16 "M1_CAS#" I R 4700 2400 60 |
380 | F17 "M0_DQ[0..15]" B R 4700 3200 60 |
381 | F18 "M0_UDM" I R 4700 3850 60 |
382 | F19 "M0_LDQS" I R 4700 3650 60 |
383 | F20 "M0_A[0..12]" I R 4700 3300 60 |
384 | F21 "M0_LDM" I R 4700 3950 60 |
385 | F22 "M0_UDQS" I R 4700 3550 60 |
386 | F23 "M1_UDQS" I R 4700 1500 60 |
387 | F24 "M1_LDM" I R 4700 1900 60 |
388 | F25 "M1_LDQS" I R 4700 1600 60 |
389 | F26 "M1_UDM" I R 4700 1800 60 |
390 | F27 "M1_CS#" I R 4700 950 60 |
391 | F28 "M1_A[0..12]" I R 4700 1200 60 |
392 | F29 "M1_DQ[0..15]" B R 4700 1100 60 |
393 | $EndSheet |
394 | $EndSCHEMATC |
395 |
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