Root/kicad/xue-rnc/xue-rnc.sch

Source at commit cb21a9a99fad714fd7d56ca88741174ca2c263e9 created 13 years 6 months ago.
By Juan64Bits, Routing current sensors.
1EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
2LIBS:power
3LIBS:r_pack2
4LIBS:v0402mhs03
5LIBS:usb-48204-0001
6LIBS:microsmd075f
7LIBS:mic2550
8LIBS:rj45-48025
9LIBS:xue-nv
10LIBS:xc6slx75fgg484
11LIBS:xc6slx45fgg484
12LIBS:micron_mobile_ddr
13LIBS:micron_ddr_512Mb
14LIBS:k8001
15LIBS:device
16LIBS:transistors
17LIBS:conn
18LIBS:linear
19LIBS:regul
20LIBS:74xx
21LIBS:cmos4000
22LIBS:adc-dac
23LIBS:memory
24LIBS:xilinx
25LIBS:special
26LIBS:microcontrollers
27LIBS:dsp
28LIBS:microchip
29LIBS:analog_switches
30LIBS:motorola
31LIBS:texas
32LIBS:intel
33LIBS:audio
34LIBS:interface
35LIBS:digital-audio
36LIBS:philips
37LIBS:display
38LIBS:cypress
39LIBS:siliconi
40LIBS:opto
41LIBS:atmel
42LIBS:contrib
43LIBS:valves
44LIBS:pasives-connectors
45LIBS:x25x64mb
46LIBS:attiny
47LIBS:PSU
48LIBS:xue-rnc-cache
49EELAYER 24 0
50EELAYER END
51$Descr A3 16535 11700
52Sheet 1 9
53Title ""
54Date "3 sep 2010"
55Rev ""
56Comp ""
57Comment1 ""
58Comment2 ""
59Comment3 ""
60Comment4 ""
61$EndDescr
62$Sheet
63S 5950 5150 3350 4150
64U 4C7BC2B2
65F0 "FPGA, Port0, Port2, PROG IF" 60
66F1 "FPGA_0_2_PROG.sch" 60
67F2 "S6_TCK" I L 5950 6450 60
68F3 "S6_TDI" I L 5950 6550 60
69F4 "S6_TDO" O L 5950 6650 60
70F5 "S6_TMS" I L 5950 6750 60
71F6 "PROG_MISO[0..3]" B R 9300 9150 60
72F7 "PROG_CCLK" O R 9300 9050 60
73F8 "PROG_CSO" O R 9300 8950 60
74F9 "NF_D[0..7]" B R 9300 8700 60
75F10 "ETH_COL" B R 9300 5850 60
76F11 "ETH_CRS" B R 9300 5750 60
77F12 "NF_WE_N" O R 9300 8400 60
78F13 "NF_ALE" O R 9300 8200 60
79F14 "NF_CLE" O R 9300 8300 60
80F15 "NF_CS1_N" O R 9300 8100 60
81F16 "NF_RE_N" O R 9300 8500 60
82F17 "NF_RNB" B R 9300 8600 60
83F18 "SD_CLK" B R 9300 7550 60
84F19 "SD_CMD" B R 9300 7650 60
85F20 "SD_DAT[0..3]" B R 9300 7750 60
86F21 "ETH_CLK" B R 9300 6950 60
87F22 "ETH_RXC" B R 9300 5550 60
88F23 "ETH_TXC" B R 9300 6550 60
89F24 "ETH_TXD[0..3]" O R 9300 6650 60
90F25 "ETH_TXEN" B R 9300 6750 60
91F26 "ETH_TXER" B R 9300 6850 60
92F27 "ETH_RXER" B R 9300 6450 60
93F28 "ETH_RXDV" B R 9300 6350 60
94F29 "ETH_RXD[0..3]" I R 9300 6250 60
95F30 "ETH_RESET_N" B R 9300 5650 60
96F31 "ETH_MDIO" B R 9300 5950 60
97F32 "ETH_MDC" B R 9300 6050 60
98F33 "ETH_INT" B R 9300 5400 60
99$EndSheet
100$Sheet
101S 5950 700 3300 4200
102U 4C7BC2A2
103F0 "FPGA Port 1, Port 3 (DDR, USB)" 60
104F1 "FPGA_1_3.sch" 60
105F2 "USBD_VP" B R 9250 1850 60
106F3 "USBD_SPD" B R 9250 1550 60
107F4 "USBD_OE_N" B R 9250 1650 60
108F5 "USBD_RCV" B R 9250 1750 60
109F6 "USBD_VM" B R 9250 1950 60
110F7 "M0_CKE" O L 5950 4100 60
111F8 "M0_UDM" O L 5950 3850 60
112F9 "M0_UDQS" O L 5950 3550 60
113F10 "M0_BA[0..1]" O L 5950 3400 60
114F11 "M0_CAS#" O L 5950 4450 60
115F12 "M0_RAS#" O L 5950 4550 60
116F13 "M0_WE#" O L 5950 4700 60
117F14 "M0_LDM" O L 5950 3950 60
118F15 "M0_LDQS" O L 5950 3650 60
119F16 "M1_UDQS" O L 5950 1500 60
120F17 "M1_UDM" O L 5950 1800 60
121F18 "M1_LDQS" O L 5950 1600 60
122F19 "M1_LDM" O L 5950 1900 60
123F20 "M1_WE#" O L 5950 2650 60
124F21 "M1_CKE" O L 5950 2050 60
125F22 "M1_RAS#" O L 5950 2500 60
126F23 "M1_CAS#" O L 5950 2400 60
127F24 "M1_BA[0..1]" O L 5950 1300 60
128F25 "M1_CS#" O L 5950 950 60
129F26 "USBA_VM" B R 9250 1350 60
130F27 "USBA_VP" B R 9250 1250 60
131F28 "USBA_RCV" B R 9250 1150 60
132F29 "USBA_OE_N" B R 9250 1050 60
133F30 "USBA_SPD" B R 9250 950 60
134F31 "M1_DQ[0..15]" B L 5950 1100 60
135F32 "M0_CS#" O L 5950 3050 60
136F33 "M0_DQ[0..15]" B L 5950 3200 60
137F34 "M0_A[0..12]" O L 5950 3300 60
138F35 "M1_A[0..12]" O L 5950 1200 60
139F36 "M1_CLK" O L 5950 2150 60
140F37 "M1_CLK#" O L 5950 2250 60
141F38 "M0_CLK" O L 5950 4200 60
142F39 "M0_CLK#" O L 5950 4300 60
143$EndSheet
144Wire Wire Line
145    10600 1950 9250 1950
146Wire Wire Line
147    10600 1750 9250 1750
148Wire Wire Line
149    10600 1550 9250 1550
150Wire Wire Line
151    4950 6650 5950 6650
152Wire Wire Line
153    5950 6450 4950 6450
154Wire Bus Line
155    10650 9150 9300 9150
156Wire Wire Line
157    10650 8100 9300 8100
158Wire Wire Line
159    10650 8500 9300 8500
160Wire Wire Line
161    9300 8200 10650 8200
162Wire Wire Line
163    10600 5850 9300 5850
164Wire Bus Line
165    9300 7750 10650 7750
166Wire Wire Line
167    9300 7550 10650 7550
168Wire Wire Line
169    10600 1350 9250 1350
170Wire Wire Line
171    10600 1150 9250 1150
172Wire Wire Line
173    10600 950 9250 950
174Wire Wire Line
175    9300 6850 10600 6850
176Wire Wire Line
177    9300 6450 10600 6450
178Wire Wire Line
179    10600 5950 9300 5950
180Wire Wire Line
181    9300 5550 10600 5550
182Wire Bus Line
183    4700 1300 5950 1300
184Wire Wire Line
185    4700 950 5950 950
186Wire Wire Line
187    4700 1900 5950 1900
188Wire Wire Line
189    4700 2050 5950 2050
190Wire Wire Line
191    4700 2400 5950 2400
192Wire Wire Line
193    4700 4100 5950 4100
194Wire Wire Line
195    4700 4700 5950 4700
196Wire Bus Line
197    4700 3400 5950 3400
198Wire Wire Line
199    4700 4450 5950 4450
200Wire Wire Line
201    4700 3850 5950 3850
202Wire Wire Line
203    4700 3550 5950 3550
204Wire Bus Line
205    4700 1200 5950 1200
206Wire Wire Line
207    5950 2250 4700 2250
208Wire Wire Line
209    4700 4300 5950 4300
210Wire Bus Line
211    5950 3250 5950 3200
212Wire Bus Line
213    5950 3200 4700 3200
214Wire Wire Line
215    4700 4200 5950 4200
216Wire Wire Line
217    4700 2150 5950 2150
218Wire Bus Line
219    4700 3300 5950 3300
220Wire Wire Line
221    4700 3950 5950 3950
222Wire Wire Line
223    4700 3650 5950 3650
224Wire Wire Line
225    4700 4550 5950 4550
226Wire Wire Line
227    4700 3050 5950 3050
228Wire Wire Line
229    4700 2500 5950 2500
230Wire Wire Line
231    4700 2650 5950 2650
232Wire Wire Line
233    4700 1800 5950 1800
234Wire Wire Line
235    4700 1600 5950 1600
236Wire Wire Line
237    4700 1500 5950 1500
238Wire Bus Line
239    4700 1100 5950 1100
240Wire Wire Line
241    9300 5400 10600 5400
242Wire Wire Line
243    9300 5650 10600 5650
244Wire Wire Line
245    9300 6050 10600 6050
246Wire Wire Line
247    9300 6350 10600 6350
248Wire Wire Line
249    9300 6550 10600 6550
250Wire Wire Line
251    9300 6750 10600 6750
252Wire Wire Line
253    9300 6950 10600 6950
254Wire Wire Line
255    10600 1050 9250 1050
256Wire Wire Line
257    10600 1250 9250 1250
258Wire Bus Line
259    9300 6650 10600 6650
260Wire Bus Line
261    10600 6250 9300 6250
262Wire Wire Line
263    9300 7650 10650 7650
264Wire Wire Line
265    10600 5750 9300 5750
266Wire Bus Line
267    10650 8700 9300 8700
268Wire Wire Line
269    10650 8300 9300 8300
270Wire Wire Line
271    10650 8400 9300 8400
272Wire Wire Line
273    10650 8600 9300 8600
274Wire Wire Line
275    10650 8950 9300 8950
276Wire Wire Line
277    10650 9050 9300 9050
278Wire Wire Line
279    5950 6550 4950 6550
280Wire Wire Line
281    5950 6750 4950 6750
282Wire Wire Line
283    10600 1650 9250 1650
284Wire Wire Line
285    10600 1850 9250 1850
286$Sheet
287S 3750 6400 1200 700
288U 4C716A4D
289F0 "DBG_PRG" 60
290F1 "DBG_PRG.sch" 60
291F2 "FPGA_TDO" B R 4950 6650 60
292F3 "FPGA_TDI" B R 4950 6550 60
293F4 "FPGA_TMS" B R 4950 6750 60
294F5 "FPGA_TCK" B R 4950 6450 60
295$EndSheet
296$Sheet
297S 3750 8000 1100 1300
298U 4C69ED5F
299F0 "PSU" 60
300F1 "PSU.sch" 60
301$EndSheet
302$Sheet
303S 10650 7350 1050 1950
304U 4C4227FE
305F0 "Non volatile memories" 60
306F1 "NV_MEMORIES.sch" 60
307F2 "SD_CMD" I L 10650 7650 60
308F3 "SD_CLK" I L 10650 7550 60
309F4 "SD_DAT[0..3]" B L 10650 7750 60
310F5 "NF_D[0..7]" B L 10650 8700 60
311F6 "NF_ALE" B L 10650 8200 60
312F7 "NF_CLE" B L 10650 8300 60
313F8 "NF_WE_N" B L 10650 8400 60
314F9 "NF_CS1_N" B L 10650 8100 60
315F10 "NF_RE_N" B L 10650 8500 60
316F11 "NF_RNB" B L 10650 8600 60
317F12 "SPI_CLK" I L 10650 9050 60
318F13 "SPI_FLASH_CS#" I L 10650 8950 60
319F14 "SPI_DQ[0..3]" B L 10650 9150 60
320$EndSheet
321$Sheet
322S 10600 900 1100 1150
323U 4C5F1EDC
324F0 "USB" 60
325F1 "USB.sch" 60
326F2 "USBA_SPD" B L 10600 950 60
327F3 "USBA_OE_N" B L 10600 1050 60
328F4 "USBA_RCV" B L 10600 1150 60
329F5 "USBA_VP" B L 10600 1250 60
330F6 "USBA_VM" B L 10600 1350 60
331F7 "USBD_SPD" B L 10600 1550 60
332F8 "USBD_OE_N" B L 10600 1650 60
333F9 "USBD_RCV" B L 10600 1750 60
334F10 "USBD_VP" B L 10600 1850 60
335F11 "USBD_VM" B L 10600 1950 60
336$EndSheet
337Text Notes 12850 10750 0 60 ~ 0
338Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
339$Sheet
340S 10600 5300 1300 1800
341U 4C4320F3
342F0 "Ethernet Phy" 60
343F1 "eth_phy.sch" 60
344F2 "ETH_RXC" O L 10600 5550 60
345F3 "ETH_RST_N" I L 10600 5650 60
346F4 "ETH_CRS" O L 10600 5750 60
347F5 "ETH_COL" O L 10600 5850 60
348F6 "ETH_MDIO" B L 10600 5950 60
349F7 "ETH_MDC" I L 10600 6050 60
350F8 "ETH_RXD[0..3]" O L 10600 6250 60
351F9 "ETH_RXDV" O L 10600 6350 60
352F10 "ETH_RXER" O L 10600 6450 60
353F11 "ETH_TXC" B L 10600 6550 60
354F12 "ETH_TXD[0..3]" I L 10600 6650 60
355F13 "ETH_TXEN" I L 10600 6750 60
356F14 "ETH_TXER" I L 10600 6850 60
357F15 "ETH_CLK" I L 10600 6950 60
358F16 "ETH_INT" O L 10600 5400 60
359$EndSheet
360$Sheet
361S 3600 850 1100 4000
362U 4C421DD3
363F0 "DDR Banks" 60
364F1 "DRAM.sch" 60
365F2 "M0_BA[0..1]" I R 4700 3400 60
366F3 "M1_BA[0..1]" I R 4700 1300 60
367F4 "M0_WE#" I R 4700 4700 60
368F5 "M0_RAS#" I R 4700 4550 60
369F6 "M1_RAS#" I R 4700 2500 60
370F7 "M1_WE#" I R 4700 2650 60
371F8 "M0_CAS#" I R 4700 4450 60
372F9 "M0_CKE" I R 4700 4100 60
373F10 "M0_CLK" I R 4700 4200 60
374F11 "M0_CLK#" I R 4700 4300 60
375F12 "M0_CS#" I R 4700 3050 60
376F13 "M1_CLK#" I R 4700 2250 60
377F14 "M1_CLK" I R 4700 2150 60
378F15 "M1_CKE" I R 4700 2050 60
379F16 "M1_CAS#" I R 4700 2400 60
380F17 "M0_DQ[0..15]" B R 4700 3200 60
381F18 "M0_UDM" I R 4700 3850 60
382F19 "M0_LDQS" I R 4700 3650 60
383F20 "M0_A[0..12]" I R 4700 3300 60
384F21 "M0_LDM" I R 4700 3950 60
385F22 "M0_UDQS" I R 4700 3550 60
386F23 "M1_UDQS" I R 4700 1500 60
387F24 "M1_LDM" I R 4700 1900 60
388F25 "M1_LDQS" I R 4700 1600 60
389F26 "M1_UDM" I R 4700 1800 60
390F27 "M1_CS#" I R 4700 950 60
391F28 "M1_A[0..12]" I R 4700 1200 60
392F29 "M1_DQ[0..15]" B R 4700 1100 60
393$EndSheet
394$EndSCHEMATC
395

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