Root/kicad/xue-rnc/xue-rnc.sch

Source at commit ef75347 created 13 years 7 months ago.
By Andres Calderon, spi memory added
1EESchema Schematic File Version 2 date Fri 13 Aug 2010 03:41:42 PM COT
2LIBS:power
3LIBS:v0402mhs03
4LIBS:usb-48204-0001
5LIBS:microsmd075f
6LIBS:mic2550ayts
7LIBS:rj45-48025
8LIBS:xue-nv
9LIBS:xc6slx75fgg484
10LIBS:xc6slx45fgg484
11LIBS:micron_mobile_ddr
12LIBS:micron_ddr_512Mb
13LIBS:k8001
14LIBS:device
15LIBS:transistors
16LIBS:conn
17LIBS:linear
18LIBS:regul
19LIBS:74xx
20LIBS:cmos4000
21LIBS:adc-dac
22LIBS:memory
23LIBS:xilinx
24LIBS:special
25LIBS:microcontrollers
26LIBS:dsp
27LIBS:microchip
28LIBS:analog_switches
29LIBS:motorola
30LIBS:texas
31LIBS:intel
32LIBS:audio
33LIBS:interface
34LIBS:digital-audio
35LIBS:philips
36LIBS:display
37LIBS:cypress
38LIBS:siliconi
39LIBS:opto
40LIBS:atmel
41LIBS:contrib
42LIBS:valves
43LIBS:pasives-connectors
44LIBS:x25x64mb
45LIBS:xue-rnc-cache
46EELAYER 24 0
47EELAYER END
48$Descr A3 16535 11700
49Sheet 1 6
50Title ""
51Date "13 aug 2010"
52Rev ""
53Comp ""
54Comment1 ""
55Comment2 ""
56Comment3 ""
57Comment4 ""
58$EndDescr
59Wire Wire Line
60    10650 3450 9300 3450
61Wire Wire Line
62    10650 3850 9300 3850
63Wire Wire Line
64    9300 3550 10650 3550
65Wire Wire Line
66    10600 6800 9300 6800
67Wire Bus Line
68    9300 3100 10650 3100
69Wire Wire Line
70    9300 2900 10650 2900
71Wire Wire Line
72    10650 5400 9300 5400
73Wire Wire Line
74    10650 5200 9300 5200
75Wire Wire Line
76    10650 5000 9300 5000
77Wire Wire Line
78    9300 7800 10600 7800
79Wire Wire Line
80    9300 7400 10600 7400
81Wire Wire Line
82    10600 6900 9300 6900
83Wire Wire Line
84    9300 6500 10600 6500
85Wire Bus Line
86    4700 3150 5950 3150
87Wire Wire Line
88    4700 2800 5950 2800
89Wire Wire Line
90    4700 3750 5950 3750
91Wire Wire Line
92    4700 3900 5950 3900
93Wire Wire Line
94    4700 4250 5950 4250
95Wire Wire Line
96    4700 5950 5950 5950
97Wire Wire Line
98    4700 6550 5950 6550
99Wire Bus Line
100    4700 5250 5950 5250
101Wire Wire Line
102    4700 6300 5950 6300
103Wire Wire Line
104    4700 5700 5950 5700
105Wire Wire Line
106    4700 5400 5950 5400
107Wire Bus Line
108    4700 3050 5950 3050
109Wire Wire Line
110    5950 4100 4700 4100
111Wire Wire Line
112    4700 6150 5950 6150
113Wire Bus Line
114    5950 5100 5950 5050
115Wire Bus Line
116    5950 5050 4700 5050
117Wire Wire Line
118    4700 6050 5950 6050
119Wire Wire Line
120    4700 4000 5950 4000
121Wire Bus Line
122    4700 5150 5950 5150
123Wire Wire Line
124    4700 5800 5950 5800
125Wire Wire Line
126    4700 5500 5950 5500
127Wire Wire Line
128    4700 6400 5950 6400
129Wire Wire Line
130    4700 4900 5950 4900
131Wire Wire Line
132    4700 4350 5950 4350
133Wire Wire Line
134    4700 4500 5950 4500
135Wire Wire Line
136    4700 3650 5950 3650
137Wire Wire Line
138    4700 3450 5950 3450
139Wire Wire Line
140    4700 3350 5950 3350
141Wire Bus Line
142    4700 2950 5950 2950
143Wire Wire Line
144    9300 6350 10600 6350
145Wire Wire Line
146    9300 6600 10600 6600
147Wire Wire Line
148    9300 7000 10600 7000
149Wire Wire Line
150    9300 7300 10600 7300
151Wire Wire Line
152    9300 7500 10600 7500
153Wire Wire Line
154    9300 7700 10600 7700
155Wire Wire Line
156    9300 7900 10600 7900
157Wire Wire Line
158    10650 5100 9300 5100
159Wire Wire Line
160    10650 5300 9300 5300
161Wire Bus Line
162    9300 7600 10600 7600
163Wire Bus Line
164    10600 7200 9300 7200
165Wire Wire Line
166    9300 3000 10650 3000
167Wire Wire Line
168    10600 6700 9300 6700
169Wire Bus Line
170    10650 4050 9300 4050
171Wire Wire Line
172    10650 3650 9300 3650
173Wire Wire Line
174    10650 3750 9300 3750
175Wire Wire Line
176    10650 3950 9300 3950
177$Sheet
178S 10650 2700 1150 1850
179U 4C4227FE
180F0 "Non volatile memories" 60
181F1 "NV_MEMORIES.sch" 60
182F2 "SD_CMD" I L 10650 3000 60
183F3 "SD_CLK" I L 10650 2900 60
184F4 "SD_DAT[0..3]" B L 10650 3100 60
185F5 "NF_D[0..7]" B L 10650 4050 60
186F6 "NF_ALE" B L 10650 3550 60
187F7 "NF_CLE" B L 10650 3650 60
188F8 "NF_WE_N" B L 10650 3750 60
189F9 "NF_CS1_N" B L 10650 3450 60
190F10 "NF_RE_N" B L 10650 3850 60
191F11 "NF_RNB" B L 10650 3950 60
192$EndSheet
193$Sheet
194S 10650 4800 1150 750
195U 4C5F1EDC
196F0 "USB" 60
197F1 "USB.sch" 60
198F2 "USBA_SPD" B L 10650 5000 60
199F3 "USBA_OE_N" B L 10650 5100 60
200F4 "USBA_RCV" B L 10650 5200 60
201F5 "USBA_VP" B L 10650 5300 60
202F6 "USBA_VM" B L 10650 5400 60
203$EndSheet
204Text Notes 12850 10750 0 60 ~ 0
205Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
206$Sheet
207S 5950 2700 3350 5800
208U 4C431A63
209F0 "FPGA Spartan6" 60
210F1 "FPGA.sch" 60
211F2 "M1_CLK" O L 5950 4000 60
212F3 "M1_CLK#" O L 5950 4100 60
213F4 "M0_CLK" O L 5950 6050 60
214F5 "M0_CLK#" O L 5950 6150 60
215F6 "M0_A[0..12]" O L 5950 5150 60
216F7 "M1_A[0..12]" O L 5950 3050 60
217F8 "M0_DQ[0..15]" B L 5950 5050 60
218F9 "M0_UDQS" O L 5950 5400 60
219F10 "M0_LDM" O L 5950 5800 60
220F11 "M0_LDQS" O L 5950 5500 60
221F12 "M0_UDM" O L 5950 5700 60
222F13 "M0_RAS#" O L 5950 6400 60
223F14 "M0_WE#" O L 5950 6550 60
224F15 "M0_CKE" O L 5950 5950 60
225F16 "M0_CAS#" O L 5950 6300 60
226F17 "M1_CAS#" O L 5950 4250 60
227F18 "M1_CKE" O L 5950 3900 60
228F19 "M0_CS#" O L 5950 4900 60
229F20 "M1_CS#" O L 5950 2800 60
230F21 "M1_WE#" O L 5950 4500 60
231F22 "M1_RAS#" O L 5950 4350 60
232F23 "M1_UDM" O L 5950 3650 60
233F24 "M1_LDQS" O L 5950 3450 60
234F25 "M1_LDM" O L 5950 3750 60
235F26 "M1_UDQS" O L 5950 3350 60
236F27 "M1_DQ[0..15]" B L 5950 2950 60
237F28 "M1_BA[0..1]" O L 5950 3150 60
238F29 "M0_BA[0..1]" O L 5950 5250 60
239F30 "USBA_VM" B R 9300 5400 60
240F31 "USBA_VP" B R 9300 5300 60
241F32 "USBA_RCV" B R 9300 5200 60
242F33 "USBA_OE_N" B R 9300 5100 60
243F34 "USBA_SPD" B R 9300 5000 60
244F35 "ETH_CLK" B R 9300 7900 60
245F36 "ETH_RXC" B R 9300 6500 60
246F37 "ETH_TXC" B R 9300 7500 60
247F38 "ETH_TXD[0..3]" O R 9300 7600 60
248F39 "ETH_TXEN" B R 9300 7700 60
249F40 "ETH_TXER" B R 9300 7800 60
250F41 "ETH_RXER" B R 9300 7400 60
251F42 "ETH_RXDV" B R 9300 7300 60
252F43 "ETH_RXD[0..3]" I R 9300 7200 60
253F44 "ETH_RESET_N" B R 9300 6600 60
254F45 "ETH_MDIO" B R 9300 6900 60
255F46 "ETH_MDC" B R 9300 7000 60
256F47 "ETH_INT" B R 9300 6350 60
257F48 "SD_CLK" B R 9300 2900 60
258F49 "SD_CMD" B R 9300 3000 60
259F50 "SD_DAT[0..3]" B R 9300 3100 60
260F51 "ETH_CRS" I R 9300 6700 60
261F52 "ETH_COL" I R 9300 6800 60
262F53 "NF_D[0..7]" B R 9300 4050 60
263F54 "NF_WE_N" O R 9300 3750 60
264F55 "NF_ALE" O R 9300 3550 60
265F56 "NF_CLE" O R 9300 3650 60
266F57 "NF_CS1_N" O R 9300 3450 60
267F58 "NF_RE_N" O R 9300 3850 60
268F59 "NF_RNB" B R 9300 3950 60
269$EndSheet
270$Sheet
271S 10600 6250 1300 1800
272U 4C4320F3
273F0 "Ethernet Phy" 60
274F1 "eth_phy.sch" 60
275F2 "ETH_RXC" O L 10600 6500 60
276F3 "ETH_RST_N" I L 10600 6600 60
277F4 "ETH_CRS" O L 10600 6700 60
278F5 "ETH_COL" O L 10600 6800 60
279F6 "ETH_MDIO" B L 10600 6900 60
280F7 "ETH_MDC" I L 10600 7000 60
281F8 "ETH_RXD[0..3]" O L 10600 7200 60
282F9 "ETH_RXDV" O L 10600 7300 60
283F10 "ETH_RXER" O L 10600 7400 60
284F11 "ETH_TXC" B L 10600 7500 60
285F12 "ETH_TXD[0..3]" I L 10600 7600 60
286F13 "ETH_TXEN" I L 10600 7700 60
287F14 "ETH_TXER" I L 10600 7800 60
288F15 "ETH_CLK" I L 10600 7900 60
289F16 "ETH_INT" O L 10600 6350 60
290$EndSheet
291$Sheet
292S 3600 2700 1100 4000
293U 4C421DD3
294F0 "DDR Banks" 60
295F1 "DRAM.sch" 60
296F2 "M0_BA[0..1]" I R 4700 5250 60
297F3 "M1_BA[0..1]" I R 4700 3150 60
298F4 "M0_WE#" I R 4700 6550 60
299F5 "M0_RAS#" I R 4700 6400 60
300F6 "M1_RAS#" I R 4700 4350 60
301F7 "M1_WE#" I R 4700 4500 60
302F8 "M0_CAS#" I R 4700 6300 60
303F9 "M0_CKE" I R 4700 5950 60
304F10 "M0_CLK" I R 4700 6050 60
305F11 "M0_CLK#" I R 4700 6150 60
306F12 "M0_CS#" I R 4700 4900 60
307F13 "M1_CLK#" I R 4700 4100 60
308F14 "M1_CLK" I R 4700 4000 60
309F15 "M1_CKE" I R 4700 3900 60
310F16 "M1_CAS#" I R 4700 4250 60
311F17 "M0_DQ[0..15]" B R 4700 5050 60
312F18 "M0_UDM" I R 4700 5700 60
313F19 "M0_LDQS" I R 4700 5500 60
314F20 "M0_A[0..12]" I R 4700 5150 60
315F21 "M0_LDM" I R 4700 5800 60
316F22 "M0_UDQS" I R 4700 5400 60
317F23 "M1_UDQS" I R 4700 3350 60
318F24 "M1_LDM" I R 4700 3750 60
319F25 "M1_LDQS" I R 4700 3450 60
320F26 "M1_UDM" I R 4700 3650 60
321F27 "M1_CS#" I R 4700 2800 60
322F28 "M1_A[0..12]" I R 4700 3050 60
323F29 "M1_DQ[0..15]" B R 4700 2950 60
324$EndSheet
325$EndSCHEMATC
326

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