Root/kicad/xue-rnc/xue-rnc.sch

Source at commit f1c6506 created 13 years 7 months ago.
By Andres Calderon, terminal resistors placement
1EESchema Schematic File Version 2 date Mon 16 Aug 2010 07:34:39 PM COT
2LIBS:power
3LIBS:r_pack2
4LIBS:v0402mhs03
5LIBS:usb-48204-0001
6LIBS:microsmd075f
7LIBS:mic2550ayts
8LIBS:rj45-48025
9LIBS:xue-nv
10LIBS:xc6slx75fgg484
11LIBS:xc6slx45fgg484
12LIBS:micron_mobile_ddr
13LIBS:micron_ddr_512Mb
14LIBS:k8001
15LIBS:device
16LIBS:transistors
17LIBS:conn
18LIBS:linear
19LIBS:regul
20LIBS:74xx
21LIBS:cmos4000
22LIBS:adc-dac
23LIBS:memory
24LIBS:xilinx
25LIBS:special
26LIBS:microcontrollers
27LIBS:dsp
28LIBS:microchip
29LIBS:analog_switches
30LIBS:motorola
31LIBS:texas
32LIBS:intel
33LIBS:audio
34LIBS:interface
35LIBS:digital-audio
36LIBS:philips
37LIBS:display
38LIBS:cypress
39LIBS:siliconi
40LIBS:opto
41LIBS:atmel
42LIBS:contrib
43LIBS:valves
44LIBS:pasives-connectors
45LIBS:x25x64mb
46LIBS:xue-rnc-cache
47EELAYER 24 0
48EELAYER END
49$Descr A3 16535 11700
50Sheet 1 6
51Title ""
52Date "17 aug 2010"
53Rev ""
54Comp ""
55Comment1 ""
56Comment2 ""
57Comment3 ""
58Comment4 ""
59$EndDescr
60Wire Wire Line
61    10650 4400 9300 4400
62Wire Wire Line
63    10650 4300 9300 4300
64Wire Wire Line
65    10650 3950 9300 3950
66Wire Wire Line
67    10650 3750 9300 3750
68Wire Wire Line
69    10650 3650 9300 3650
70Wire Bus Line
71    10650 4050 9300 4050
72Wire Wire Line
73    10600 6700 9300 6700
74Wire Wire Line
75    9300 3000 10650 3000
76Wire Bus Line
77    10600 7200 9300 7200
78Wire Bus Line
79    9300 7600 10600 7600
80Wire Wire Line
81    10650 5750 9300 5750
82Wire Wire Line
83    10650 5550 9300 5550
84Wire Wire Line
85    9300 7900 10600 7900
86Wire Wire Line
87    9300 7700 10600 7700
88Wire Wire Line
89    9300 7500 10600 7500
90Wire Wire Line
91    9300 7300 10600 7300
92Wire Wire Line
93    9300 7000 10600 7000
94Wire Wire Line
95    9300 6600 10600 6600
96Wire Wire Line
97    9300 6350 10600 6350
98Wire Bus Line
99    4700 2950 5950 2950
100Wire Wire Line
101    4700 3350 5950 3350
102Wire Wire Line
103    4700 3450 5950 3450
104Wire Wire Line
105    4700 3650 5950 3650
106Wire Wire Line
107    4700 4500 5950 4500
108Wire Wire Line
109    4700 4350 5950 4350
110Wire Wire Line
111    4700 4900 5950 4900
112Wire Wire Line
113    4700 6400 5950 6400
114Wire Wire Line
115    4700 5500 5950 5500
116Wire Wire Line
117    4700 5800 5950 5800
118Wire Bus Line
119    4700 5150 5950 5150
120Wire Wire Line
121    4700 4000 5950 4000
122Wire Wire Line
123    4700 6050 5950 6050
124Wire Bus Line
125    4700 5050 5950 5050
126Wire Bus Line
127    5950 5050 5950 5100
128Wire Wire Line
129    4700 6150 5950 6150
130Wire Wire Line
131    5950 4100 4700 4100
132Wire Bus Line
133    4700 3050 5950 3050
134Wire Wire Line
135    4700 5400 5950 5400
136Wire Wire Line
137    4700 5700 5950 5700
138Wire Wire Line
139    4700 6300 5950 6300
140Wire Bus Line
141    4700 5250 5950 5250
142Wire Wire Line
143    4700 6550 5950 6550
144Wire Wire Line
145    4700 5950 5950 5950
146Wire Wire Line
147    4700 4250 5950 4250
148Wire Wire Line
149    4700 3900 5950 3900
150Wire Wire Line
151    4700 3750 5950 3750
152Wire Wire Line
153    4700 2800 5950 2800
154Wire Bus Line
155    4700 3150 5950 3150
156Wire Wire Line
157    9300 6500 10600 6500
158Wire Wire Line
159    10600 6900 9300 6900
160Wire Wire Line
161    9300 7400 10600 7400
162Wire Wire Line
163    9300 7800 10600 7800
164Wire Wire Line
165    10650 5450 9300 5450
166Wire Wire Line
167    10650 5650 9300 5650
168Wire Wire Line
169    10650 5850 9300 5850
170Wire Wire Line
171    9300 2900 10650 2900
172Wire Bus Line
173    9300 3100 10650 3100
174Wire Wire Line
175    10600 6800 9300 6800
176Wire Wire Line
177    9300 3550 10650 3550
178Wire Wire Line
179    10650 3850 9300 3850
180Wire Wire Line
181    10650 3450 9300 3450
182Wire Bus Line
183    10650 4500 9300 4500
184$Sheet
185S 10650 2700 1050 1950
186U 4C4227FE
187F0 "Non volatile memories" 60
188F1 "NV_MEMORIES.sch" 60
189F2 "SD_CMD" I L 10650 3000 60
190F3 "SD_CLK" I L 10650 2900 60
191F4 "SD_DAT[0..3]" B L 10650 3100 60
192F5 "NF_D[0..7]" B L 10650 4050 60
193F6 "NF_ALE" B L 10650 3550 60
194F7 "NF_CLE" B L 10650 3650 60
195F8 "NF_WE_N" B L 10650 3750 60
196F9 "NF_CS1_N" B L 10650 3450 60
197F10 "NF_RE_N" B L 10650 3850 60
198F11 "NF_RNB" B L 10650 3950 60
199F12 "SPI_CLK" I L 10650 4400 60
200F13 "SPI_FLASH_CS#" I L 10650 4300 60
201F14 "SPI_DQ[0..3]" B L 10650 4500 60
202$EndSheet
203$Sheet
204S 10650 5250 1150 750
205U 4C5F1EDC
206F0 "USB" 60
207F1 "USB.sch" 60
208F2 "USBA_SPD" B L 10650 5450 60
209F3 "USBA_OE_N" B L 10650 5550 60
210F4 "USBA_RCV" B L 10650 5650 60
211F5 "USBA_VP" B L 10650 5750 60
212F6 "USBA_VM" B L 10650 5850 60
213$EndSheet
214Text Notes 12850 10750 0 60 ~ 0
215Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
216$Sheet
217S 5950 2700 3350 5800
218U 4C431A63
219F0 "FPGA Spartan6" 60
220F1 "FPGA.sch" 60
221F2 "M1_CLK" O L 5950 4000 60
222F3 "M1_CLK#" O L 5950 4100 60
223F4 "M0_CLK" O L 5950 6050 60
224F5 "M0_CLK#" O L 5950 6150 60
225F6 "M0_A[0..12]" O L 5950 5150 60
226F7 "M1_A[0..12]" O L 5950 3050 60
227F8 "M0_DQ[0..15]" B L 5950 5050 60
228F9 "M0_UDQS" O L 5950 5400 60
229F10 "M0_LDM" O L 5950 5800 60
230F11 "M0_LDQS" O L 5950 5500 60
231F12 "M0_UDM" O L 5950 5700 60
232F13 "M0_RAS#" O L 5950 6400 60
233F14 "M0_WE#" O L 5950 6550 60
234F15 "M0_CKE" O L 5950 5950 60
235F16 "M0_CAS#" O L 5950 6300 60
236F17 "M1_CAS#" O L 5950 4250 60
237F18 "M1_CKE" O L 5950 3900 60
238F19 "M0_CS#" O L 5950 4900 60
239F20 "M1_CS#" O L 5950 2800 60
240F21 "M1_WE#" O L 5950 4500 60
241F22 "M1_RAS#" O L 5950 4350 60
242F23 "M1_UDM" O L 5950 3650 60
243F24 "M1_LDQS" O L 5950 3450 60
244F25 "M1_LDM" O L 5950 3750 60
245F26 "M1_UDQS" O L 5950 3350 60
246F27 "M1_DQ[0..15]" B L 5950 2950 60
247F28 "M1_BA[0..1]" O L 5950 3150 60
248F29 "M0_BA[0..1]" O L 5950 5250 60
249F30 "USBA_VM" B R 9300 5850 60
250F31 "USBA_VP" B R 9300 5750 60
251F32 "USBA_RCV" B R 9300 5650 60
252F33 "USBA_OE_N" B R 9300 5550 60
253F34 "USBA_SPD" B R 9300 5450 60
254F35 "ETH_CLK" B R 9300 7900 60
255F36 "ETH_RXC" B R 9300 6500 60
256F37 "ETH_TXC" B R 9300 7500 60
257F38 "ETH_TXD[0..3]" O R 9300 7600 60
258F39 "ETH_TXEN" B R 9300 7700 60
259F40 "ETH_TXER" B R 9300 7800 60
260F41 "ETH_RXER" B R 9300 7400 60
261F42 "ETH_RXDV" B R 9300 7300 60
262F43 "ETH_RXD[0..3]" I R 9300 7200 60
263F44 "ETH_RESET_N" B R 9300 6600 60
264F45 "ETH_MDIO" B R 9300 6900 60
265F46 "ETH_MDC" B R 9300 7000 60
266F47 "ETH_INT" B R 9300 6350 60
267F48 "SD_CLK" B R 9300 2900 60
268F49 "SD_CMD" B R 9300 3000 60
269F50 "SD_DAT[0..3]" B R 9300 3100 60
270F51 "ETH_CRS" I R 9300 6700 60
271F52 "ETH_COL" I R 9300 6800 60
272F53 "NF_D[0..7]" B R 9300 4050 60
273F54 "NF_WE_N" O R 9300 3750 60
274F55 "NF_ALE" O R 9300 3550 60
275F56 "NF_CLE" O R 9300 3650 60
276F57 "NF_CS1_N" O R 9300 3450 60
277F58 "NF_RE_N" O R 9300 3850 60
278F59 "NF_RNB" B R 9300 3950 60
279F60 "PROG_CCLK" O R 9300 4400 60
280F61 "PROG_CSO" O R 9300 4300 60
281F62 "PROG_MISO[0..3]" B R 9300 4500 60
282$EndSheet
283$Sheet
284S 10600 6250 1300 1800
285U 4C4320F3
286F0 "Ethernet Phy" 60
287F1 "eth_phy.sch" 60
288F2 "ETH_RXC" O L 10600 6500 60
289F3 "ETH_RST_N" I L 10600 6600 60
290F4 "ETH_CRS" O L 10600 6700 60
291F5 "ETH_COL" O L 10600 6800 60
292F6 "ETH_MDIO" B L 10600 6900 60
293F7 "ETH_MDC" I L 10600 7000 60
294F8 "ETH_RXD[0..3]" O L 10600 7200 60
295F9 "ETH_RXDV" O L 10600 7300 60
296F10 "ETH_RXER" O L 10600 7400 60
297F11 "ETH_TXC" B L 10600 7500 60
298F12 "ETH_TXD[0..3]" I L 10600 7600 60
299F13 "ETH_TXEN" I L 10600 7700 60
300F14 "ETH_TXER" I L 10600 7800 60
301F15 "ETH_CLK" I L 10600 7900 60
302F16 "ETH_INT" O L 10600 6350 60
303$EndSheet
304$Sheet
305S 3600 2700 1100 4000
306U 4C421DD3
307F0 "DDR Banks" 60
308F1 "DRAM.sch" 60
309F2 "M0_BA[0..1]" I R 4700 5250 60
310F3 "M1_BA[0..1]" I R 4700 3150 60
311F4 "M0_WE#" I R 4700 6550 60
312F5 "M0_RAS#" I R 4700 6400 60
313F6 "M1_RAS#" I R 4700 4350 60
314F7 "M1_WE#" I R 4700 4500 60
315F8 "M0_CAS#" I R 4700 6300 60
316F9 "M0_CKE" I R 4700 5950 60
317F10 "M0_CLK" I R 4700 6050 60
318F11 "M0_CLK#" I R 4700 6150 60
319F12 "M0_CS#" I R 4700 4900 60
320F13 "M1_CLK#" I R 4700 4100 60
321F14 "M1_CLK" I R 4700 4000 60
322F15 "M1_CKE" I R 4700 3900 60
323F16 "M1_CAS#" I R 4700 4250 60
324F17 "M0_DQ[0..15]" B R 4700 5050 60
325F18 "M0_UDM" I R 4700 5700 60
326F19 "M0_LDQS" I R 4700 5500 60
327F20 "M0_A[0..12]" I R 4700 5150 60
328F21 "M0_LDM" I R 4700 5800 60
329F22 "M0_UDQS" I R 4700 5400 60
330F23 "M1_UDQS" I R 4700 3350 60
331F24 "M1_LDM" I R 4700 3750 60
332F25 "M1_LDQS" I R 4700 3450 60
333F26 "M1_UDM" I R 4700 3650 60
334F27 "M1_CS#" I R 4700 2800 60
335F28 "M1_A[0..12]" I R 4700 3050 60
336F29 "M1_DQ[0..15]" B R 4700 2950 60
337$EndSheet
338$EndSCHEMATC
339

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