Root/sim/verilog/micron_2048Mb_ddr2/ddr2.v

1/****************************************************************************************
2*
3* File Name: ddr2.v
4* Version: 5.83
5* Model: BUS Functional
6*
7* Dependencies: ddr2_parameters.vh
8*
9* Description: Micron SDRAM DDR2 (Double Data Rate 2)
10*
11* Limitation: - doesn't check for average refresh timings
12* - positive ck and ck_n edges are used to form internal clock
13* - positive dqs and dqs_n edges are used to latch data
14* - test mode is not modeled
15*
16* Note: - Set simulator resolution to "ps" accuracy
17* - Set Debug = 0 to disable $display messages
18*
19* Disclaimer This software code and all associated documentation, comments or other
20* of Warranty: information (collectively "Software") is provided "AS IS" without
21* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
22* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
23* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
24* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
25* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
26* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
27* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
28* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
29* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
30* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
31* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
32* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
33* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
34* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
35* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
36* DAMAGES. Because some jurisdictions prohibit the exclusion or
37* limitation of liability for consequential or incidental damages, the
38* above limitation may not apply to you.
39*
40* Copyright 2003 Micron Technology, Inc. All rights reserved.
41*
42* Rev Author Date Changes
43* ---------------------------------------------------------------------------------------
44* 1.00 JMK 07/29/03 Initial Release
45* 1.10 JMK 08/09/03 Timing Parameter updates to tIS, tIH, tDS, tDH
46* 2.20 JMK 08/07/03 General cleanup
47* 2.30 JMK 11/26/03 Added CL_MIN, CL_MAX, wl_min and wl_max parameters.
48* Added AL_MIN and AL_MAX parameters.
49* Removed support for OCD.
50* 2.40 JMK 01/15/04 Removed verilog 2001 constructs.
51* 2.50 JMK 01/29/04 Removed tRP checks during Precharge command.
52* 2.60 JMK 04/20/04 Fixed tWTR check.
53* 2.70 JMK 04/30/04 Added tRFC maximum check.
54* Combined Self Refresh and Power Down always blocks.
55* Added Reset Function (CKE LOW Anytime).
56* 2.80 JMK 08/19/04 Precharge is treated as NOP when bank is not active.
57* Added checks for tRAS, tWR, tRTP to any bank during Pre-All.
58* tRFC maximum violation will only display one time.
59* 2.90 JMK 11/05/04 Fixed DQS checking during write.
60* Fixed false tRFC max assertion during power up and self ref.
61* Added warning for 200us CKE low time during initialization.
62* Added -3, -3E, and -37V speed grades to ddr2_parameters.v
63* 3.00 JMK 04/22/05 Removed ODT off requirement during power down.
64* Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.
65* Added ODT status messages.
66* Updated the initialization sequence.
67* Disable ODT and CLK pins during self refresh.
68* Disable cmd and addr pins during power down and self refresh.
69* 3.10 JMK 06/07/05 Disable trpa checking if the part does not have 8 banks.
70* Changed tAXPD message from error to a warning.
71* Added tDSS checking.
72* Removed tDQSL checking during tWPRE and tWPST.
73* Fixed a burst order error during writes.
74* Renamed parameters file with .vh extension.
75* 3.20 JMK 07/18/05 Removed 14 tCK requirement from LMR to READ.
76* 3.30 JMK 08/03/05 Added check for interrupting a burst with auto precharge.
77* 4.00 JMK 11/21/05 Parameter names all UPPERCASE, signal names all lowercase.
78* Clock jitter can be tolerated within specification range.
79* Clock frequency is sampled from the CK pin.
80* Scaleable up to 64 DQ and 16 DQS bits.
81* Read data can be randomly skewed using RANDOM_OUT_DELAY.
82* Parameterized read and write DQS, and read DQ.
83* Initialization can be bypassed using initialize task.
84* 4.10 JMK 11/30/05 Fixed compile errors when `MAX_MEM was defined.
85* 4.20 JMK 12/09/05 Fixed memory addressing error when `MAX_MEM was defined.
86* 4.30 JMK 02/15/06 Added dummy write to initialization sequence.
87* Removed tWPST maximum checking.
88* Rising dqs_n edge latches data when enabled in EMR.
89* Fixed a sign error in the tJIT(cc) calculation.
90* 4.40 JMK 02/16/06 Fixed dummy write when`MAX_MEM was defined.
91* 4.50 JMK 02/27/06 Fixed extra tDQSS assertions.
92* Fixed tRCD and tWTR checking.
93* Errors entering Power Down or Self Refresh will cause reset.
94* Ignore dqs_n when disabled in EMR.
95* 5.00 JMK 04/24/06 Test stimulus now included from external file (subtest.vh)
96* Fixed tRFC max assertion during self refresh.
97* Fixed tANPD checking during Power Down.
98* Removed dummy write from initialization sequence.
99* 5.01 JMK 04/28/06 Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.
100* Removed Auto Precharge error message during Power Down Enter.
101* 5.10 JMK 07/26/06 Created internal clock using ck and ck_n.
102* RDQS can only be enabled in EMR for x8 configurations.
103* CAS latency is checked vs frequency when DLL locks.
104* tMOD changed from tCK units to ns units.
105* Added 50 Ohm setting for Rtt in EMR.
106* Improved checking of DQS during writes.
107* 5.20 JMK 10/02/06 Fixed DQS checking for interrupting write to write and x16.
108* 5.30 JMK 05/25/07 Fixed checking for 0-Z transition on write postamble.
109* 5.50 JMK 05/30/08 Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support.
110* Added a register delay to ddr2_module.v when RDIMM is defined.
111* Added multi-chip package model support in ddr2_mcp.v
112* Added High Temp Self Refresh rate setting in EMRS2[7]
113* 5.70 JMK 04/23/09 Updated tRPA definition
114* Increased internal width to 72 bit DQ bus
115* 5.80 SPH 08/12/09 Fixed tRAS maximum violation (only check if bank still open)
116* 5.81 SPH 12/08/09 Only check tIH for cmd_addr if CS# LOW
117* 5.82 SPH 04/08/10 Correct debug message for SRT in EMR2
118* 5.83 SPH 04/29/10 Correct tDQSS check on valid DQS group
119****************************************************************************************/
120
121// DO NOT CHANGE THE TIMESCALE
122// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
123`timescale 1ps / 1ps
124
125module ddr2 (
126    ck,
127    ck_n,
128    cke,
129    cs_n,
130    ras_n,
131    cas_n,
132    we_n,
133    dm_rdqs,
134    ba,
135    addr,
136    dq,
137    dqs,
138    dqs_n,
139    rdqs_n,
140    odt
141);
142
143    `include "ddr2_parameters.vh"
144
145    // text macros
146    `define DQ_PER_DQS DQ_BITS/DQS_BITS
147    `define BANKS (1<<BA_BITS)
148    `define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
149    `define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
150    `define MEM_SIZE (1<<MEM_BITS)
151    `define MAX_PIPE 2*(AL_MAX + CL_MAX)
152
153    // Declare Ports
154    input ck;
155    input ck_n;
156    input cke;
157    input cs_n;
158    input ras_n;
159    input cas_n;
160    input we_n;
161    inout [DM_BITS-1:0] dm_rdqs;
162    input [BA_BITS-1:0] ba;
163    input [ADDR_BITS-1:0] addr;
164    inout [DQ_BITS-1:0] dq;
165    inout [DQS_BITS-1:0] dqs;
166    inout [DQS_BITS-1:0] dqs_n;
167    output [DQS_BITS-1:0] rdqs_n;
168    input odt;
169                            
170    // clock jitter
171    real tck_avg;
172    time tck_sample [TDLLK-1:0];
173    time tch_sample [TDLLK-1:0];
174    time tcl_sample [TDLLK-1:0];
175    time tck_i;
176    time tch_i;
177    time tcl_i;
178    real tch_avg;
179    real tcl_avg;
180    time tm_ck_pos;
181    time tm_ck_neg;
182    real tjit_per_rtime;
183    integer tjit_cc_time;
184    real terr_nper_rtime;
185
186    // clock skew
187    real out_delay;
188    integer dqsck [DQS_BITS-1:0];
189    integer dqsck_min;
190    integer dqsck_max;
191    integer dqsq_min;
192    integer dqsq_max;
193    integer seed;
194
195    // Mode Registers
196    reg burst_order;
197    reg [BL_BITS:0] burst_length;
198    integer cas_latency;
199    integer additive_latency;
200    reg dll_reset;
201    reg dll_locked;
202    reg dll_en;
203    integer write_recovery;
204    reg low_power;
205    reg [1:0] odt_rtt;
206    reg odt_en;
207    reg [2:0] ocd;
208    reg dqs_n_en;
209    reg rdqs_en;
210    reg out_en;
211    integer read_latency;
212    integer write_latency;
213
214    // cmd encoding
215    parameter
216        LOAD_MODE = 4'b0000,
217        REFRESH = 4'b0001,
218        PRECHARGE = 4'b0010,
219        ACTIVATE = 4'b0011,
220        WRITE = 4'b0100,
221        READ = 4'b0101,
222        NOP = 4'b0111,
223        PWR_DOWN = 4'b1000,
224        SELF_REF = 4'b1001
225    ;
226
227    reg [8*9-1:0] cmd_string [9:0];
228    initial begin
229        cmd_string[LOAD_MODE] = "Load Mode";
230        cmd_string[REFRESH ] = "Refresh ";
231        cmd_string[PRECHARGE] = "Precharge";
232        cmd_string[ACTIVATE ] = "Activate ";
233        cmd_string[WRITE ] = "Write ";
234        cmd_string[READ ] = "Read ";
235        cmd_string[NOP ] = "No Op ";
236        cmd_string[PWR_DOWN ] = "Pwr Down ";
237        cmd_string[SELF_REF ] = "Self Ref ";
238    end
239
240    // command state
241    reg [`BANKS-1:0] active_bank;
242    reg [`BANKS-1:0] auto_precharge_bank;
243    reg [`BANKS-1:0] write_precharge_bank;
244    reg [`BANKS-1:0] read_precharge_bank;
245    reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
246    reg in_power_down;
247    reg in_self_refresh;
248    reg [3:0] init_mode_reg;
249    reg init_done;
250    integer init_step;
251    reg er_trfc_max;
252    reg odt_state;
253    reg prev_odt;
254
255    // cmd timers/counters
256    integer ref_cntr;
257    integer ck_cntr;
258    integer ck_load_mode;
259    integer ck_write;
260    integer ck_read;
261    integer ck_write_ap;
262    integer ck_power_down;
263    integer ck_slow_exit_pd;
264    integer ck_self_refresh;
265    integer ck_cke;
266    integer ck_odt;
267    integer ck_dll_reset;
268    integer ck_bank_write [`BANKS-1:0];
269    integer ck_bank_read [`BANKS-1:0];
270    time tm_refresh;
271    time tm_precharge;
272    time tm_precharge_all;
273    time tm_activate;
274    time tm_write_end;
275    time tm_self_refresh;
276    time tm_odt_en;
277    time tm_bank_precharge [`BANKS-1:0];
278    time tm_bank_activate [`BANKS-1:0];
279    time tm_bank_write_end [`BANKS-1:0];
280    time tm_bank_read_end [`BANKS-1:0];
281
282    // pipelines
283    reg [`MAX_PIPE:0] al_pipeline;
284    reg [`MAX_PIPE:0] wr_pipeline;
285    reg [`MAX_PIPE:0] rd_pipeline;
286    reg [`MAX_PIPE:0] odt_pipeline;
287    reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
288    reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
289    reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
290    reg prev_cke;
291    
292    // data state
293    reg [BL_MAX*DQ_BITS-1:0] memory_data;
294    reg [BL_MAX*DQ_BITS-1:0] bit_mask;
295    reg [BL_BITS-1:0] burst_position;
296    reg [BL_BITS:0] burst_cntr;
297    reg [DQ_BITS-1:0] dq_temp;
298    reg [35:0] check_write_postamble;
299    reg [35:0] check_write_preamble;
300    reg [35:0] check_write_dqs_high;
301    reg [35:0] check_write_dqs_low;
302    reg [17:0] check_dm_tdipw;
303    reg [71:0] check_dq_tdipw;
304
305    // data timers/counters
306    time tm_cke;
307    time tm_odt;
308    time tm_tdqss;
309    time tm_dm [17:0];
310    time tm_dqs [17:0];
311    time tm_dqs_pos [35:0];
312    time tm_dqss_pos [35:0];
313    time tm_dqs_neg [35:0];
314    time tm_dq [71:0];
315    time tm_cmd_addr [22:0];
316    reg [8*7-1:0] cmd_addr_string [22:0];
317    initial begin
318        cmd_addr_string[ 0] = "CS_N ";
319        cmd_addr_string[ 1] = "RAS_N ";
320        cmd_addr_string[ 2] = "CAS_N ";
321        cmd_addr_string[ 3] = "WE_N ";
322        cmd_addr_string[ 4] = "BA 0 ";
323        cmd_addr_string[ 5] = "BA 1 ";
324        cmd_addr_string[ 6] = "BA 2 ";
325        cmd_addr_string[ 7] = "ADDR 0";
326        cmd_addr_string[ 8] = "ADDR 1";
327        cmd_addr_string[ 9] = "ADDR 2";
328        cmd_addr_string[10] = "ADDR 3";
329        cmd_addr_string[11] = "ADDR 4";
330        cmd_addr_string[12] = "ADDR 5";
331        cmd_addr_string[13] = "ADDR 6";
332        cmd_addr_string[14] = "ADDR 7";
333        cmd_addr_string[15] = "ADDR 8";
334        cmd_addr_string[16] = "ADDR 9";
335        cmd_addr_string[17] = "ADDR 10";
336        cmd_addr_string[18] = "ADDR 11";
337        cmd_addr_string[19] = "ADDR 12";
338        cmd_addr_string[20] = "ADDR 13";
339        cmd_addr_string[21] = "ADDR 14";
340        cmd_addr_string[22] = "ADDR 15";
341    end
342
343    reg [8*5-1:0] dqs_string [1:0];
344    initial begin
345        dqs_string[0] = "DQS ";
346        dqs_string[1] = "DQS_N";
347    end
348
349    // Memory Storage
350`ifdef MAX_MEM
351    reg [BL_MAX*DQ_BITS-1:0] memory [0:`MAX_SIZE-1];
352`else
353    reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
354    reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
355    reg [MEM_BITS:0] memory_index;
356    reg [MEM_BITS:0] memory_used;
357`endif
358
359    // receive
360    reg ck_in;
361    reg ck_n_in;
362    reg cke_in;
363    reg cs_n_in;
364    reg ras_n_in;
365    reg cas_n_in;
366    reg we_n_in;
367    reg [17:0] dm_in;
368    reg [2:0] ba_in;
369    reg [15:0] addr_in;
370    reg [71:0] dq_in;
371    reg [35:0] dqs_in;
372    reg odt_in;
373
374    reg [17:0] dm_in_pos;
375    reg [17:0] dm_in_neg;
376    reg [71:0] dq_in_pos;
377    reg [71:0] dq_in_neg;
378    reg dq_in_valid;
379    reg dqs_in_valid;
380    integer wdqs_cntr;
381    integer wdq_cntr;
382    integer wdqs_pos_cntr [35:0];
383    reg b2b_write;
384    reg [35:0] prev_dqs_in;
385    reg diff_ck;
386
387    always @(ck ) ck_in <= #BUS_DELAY ck;
388    always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
389    always @(cke ) cke_in <= #BUS_DELAY cke;
390    always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
391    always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
392    always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
393    always @(we_n ) we_n_in <= #BUS_DELAY we_n;
394    always @(dm_rdqs) dm_in <= #BUS_DELAY dm_rdqs;
395    always @(ba ) ba_in <= #BUS_DELAY ba;
396    always @(addr ) addr_in <= #BUS_DELAY addr;
397    always @(dq ) dq_in <= #BUS_DELAY dq;
398    always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<18) | dqs;
399    always @(odt ) odt_in <= #BUS_DELAY odt;
400    // create internal clock
401    always @(posedge ck_in) diff_ck <= ck_in;
402    always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
403
404    wire [17:0] dqs_even = dqs_in[17:0];
405    wire [17:0] dqs_odd = dqs_n_en ? dqs_in[35:18] : ~dqs_in[17:0];
406    wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
407
408    // transmit
409    reg dqs_out_en;
410    reg [DQS_BITS-1:0] dqs_out_en_dly;
411    reg dqs_out;
412    reg [DQS_BITS-1:0] dqs_out_dly;
413    reg dq_out_en;
414    reg [DQ_BITS-1:0] dq_out_en_dly;
415    reg [DQ_BITS-1:0] dq_out;
416    reg [DQ_BITS-1:0] dq_out_dly;
417    integer rdqsen_cntr;
418    integer rdqs_cntr;
419    integer rdqen_cntr;
420    integer rdq_cntr;
421
422    bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
423    bufif1 buf_dm [DM_BITS-1:0] (dm_rdqs, dqs_out_dly, dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});
424    bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});
425    bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});
426    bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
427
428    initial begin
429        if (BL_MAX < 2)
430            $display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
431        if ((1<<BO_BITS) > BL_MAX)
432            $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
433        $timeformat (-12, 1, " ps", 1);
434        reset_task;
435        seed = RANDOM_SEED;
436        ck_cntr = 0;
437    end
438
439    // calculate the absolute value of a real number
440    function real abs_value;
441    input arg;
442    real arg;
443    begin
444        if (arg < 0.0)
445            abs_value = -1.0 * arg;
446        else
447            abs_value = arg;
448    end
449    endfunction
450
451`ifdef MAX_MEM
452`else
453    function get_index;
454        input [`MAX_BITS-1:0] addr;
455        begin : index
456            get_index = 0;
457            for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
458                if (address[memory_index] == addr) begin
459                    get_index = 1;
460                    disable index;
461                end
462            end
463        end
464    endfunction
465`endif
466
467    task memory_write;
468        input [BA_BITS-1:0] bank;
469        input [ROW_BITS-1:0] row;
470        input [COL_BITS-1:0] col;
471        input [BL_MAX*DQ_BITS-1:0] data;
472        reg [`MAX_BITS-1:0] addr;
473        begin
474            // chop off the lowest address bits
475            addr = {bank, row, col}/BL_MAX;
476`ifdef MAX_MEM
477            memory[addr] = data;
478`else
479            if (get_index(addr)) begin
480                address[memory_index] = addr;
481                memory[memory_index] = data;
482            end else if (memory_used == `MEM_SIZE) begin
483                $display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
484                if (STOP_ON_ERROR) $stop(0);
485            end else begin
486                address[memory_used] = addr;
487                memory[memory_used] = data;
488                memory_used = memory_used + 1;
489            end
490`endif
491        end
492    endtask
493
494    task memory_read;
495        input [BA_BITS-1:0] bank;
496        input [ROW_BITS-1:0] row;
497        input [COL_BITS-1:0] col;
498        output [BL_MAX*DQ_BITS-1:0] data;
499        reg [`MAX_BITS-1:0] addr;
500        begin
501            // chop off the lowest address bits
502            addr = {bank, row, col}/BL_MAX;
503`ifdef MAX_MEM
504            data = memory[addr];
505`else
506            if (get_index(addr)) begin
507                data = memory[memory_index];
508            end else begin
509                data = {BL_MAX*DQ_BITS{1'bx}};
510            end
511`endif
512        end
513    endtask
514
515    // Before this task runs, the model must be in a valid state for precharge power down.
516    // After this task runs, NOP commands must be issued until tRFC has been met
517    task initialize;
518        input [ADDR_BITS-1:0] mode_reg0;
519        input [ADDR_BITS-1:0] mode_reg1;
520        input [ADDR_BITS-1:0] mode_reg2;
521        input [ADDR_BITS-1:0] mode_reg3;
522        begin
523            if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
524            cmd_task(1, NOP, 'bx, 'bx);
525            cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
526            cmd_task(1, LOAD_MODE, 3, mode_reg3);
527            cmd_task(1, LOAD_MODE, 2, mode_reg2);
528            cmd_task(1, LOAD_MODE, 1, mode_reg1);
529            cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
530            cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
531            cmd_task(1, REFRESH, 'bx, 'bx);
532            cmd_task(1, REFRESH, 'bx, 'bx);
533            cmd_task(1, LOAD_MODE, 0, mode_reg0);
534            cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default
535            cmd_task(1, LOAD_MODE, 1, mode_reg1);
536            cmd_task(0, NOP, 'bx, 'bx);
537        end
538    endtask
539    
540    task reset_task;
541        integer i;
542        begin
543            // disable inputs
544            dq_in_valid = 0;
545            dqs_in_valid <= 0;
546            wdqs_cntr = 0;
547            wdq_cntr = 0;
548            for (i=0; i<36; i=i+1) begin
549                wdqs_pos_cntr[i] <= 0;
550            end
551            b2b_write <= 0;
552            // disable outputs
553            out_en = 0;
554            dqs_n_en = 0;
555            rdqs_en = 0;
556            dq_out_en = 0;
557            rdq_cntr = 0;
558            dqs_out_en = 0;
559            rdqs_cntr = 0;
560            // disable ODT
561            odt_en = 0;
562            odt_state = 0;
563            // reset bank state
564            active_bank = {`BANKS{1'b1}};
565            auto_precharge_bank = 0;
566            read_precharge_bank = 0;
567            write_precharge_bank = 0;
568            // require initialization sequence
569            init_done = 0;
570            init_step = 0;
571            init_mode_reg = 0;
572            // reset DLL
573            dll_en = 0;
574            dll_reset = 0;
575            dll_locked = 0;
576            ocd = 0;
577            // exit power down and self refresh
578            in_power_down = 0;
579            in_self_refresh = 0;
580            // clear pipelines
581            al_pipeline = 0;
582            wr_pipeline = 0;
583            rd_pipeline = 0;
584            odt_pipeline = 0;
585            // clear memory
586`ifdef MAX_MEM
587            for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time
588                memory[i] <= 'bx;
589            end
590`else
591            memory_used <= 0; //erase memory
592`endif
593            // clear maximum timing checks
594            tm_refresh <= 'bx;
595            for (i=0; i<`BANKS; i=i+1) begin
596                tm_bank_activate[i] <= 'bx;
597            end
598        end
599    endtask
600
601    task chk_err;
602        input samebank;
603        input [BA_BITS-1:0] bank;
604        input [3:0] fromcmd;
605        input [3:0] cmd;
606        reg err;
607    begin
608        // all matching case expressions will be evaluated
609        casex ({samebank, fromcmd, cmd})
610            {1'b0, LOAD_MODE, 4'b0xxx } : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
611            {1'b0, LOAD_MODE, 4'b100x } : begin if (ck_cntr - ck_load_mode < TMRD) begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time); init_done = 0; end end
612            {1'b0, REFRESH , 4'b0xxx } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
613            {1'b0, REFRESH , PWR_DOWN } : ; // 1 tCK
614            {1'b0, REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time); init_done = 0; end end
615            {1'b0, PRECHARGE, 4'b000x } : begin if ($time - tm_precharge_all < TRPA) $display ("%m: at time %t ERROR: tRPA violation during %s", $time, cmd_string[cmd]);
616                                                 if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
617            {1'b1, PRECHARGE, PRECHARGE} : begin if (DEBUG && ($time - tm_precharge_all < TRPA)) $display ("%m: at time %t INFO: Precharge All interruption during %s", $time, cmd_string[cmd]);
618                                                 if (DEBUG && ($time - tm_bank_precharge[bank] < TRP)) $display ("%m: at time %t INFO: Precharge bank %d interruption during %s", $time, cmd_string[cmd], bank); end
619            {1'b1, PRECHARGE, ACTIVATE } : begin if ($time - tm_precharge_all < TRPA) $display ("%m: at time %t ERROR: tRPA violation during %s", $time, cmd_string[cmd]);
620                                                 if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
621            {1'b0, PRECHARGE, PWR_DOWN } : ; //1 tCK, can be concurrent with auto precharge
622            {1'b0, PRECHARGE, SELF_REF } : begin if (($time - tm_precharge_all < TRPA) || ($time - tm_precharge < TRP)) begin $display ("%m: at time %t INFO: Precharge to Reset condition", $time); init_done = 0; end end
623            {1'b0, ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
624            {1'b1, ACTIVATE , PRECHARGE} : begin if (($time - tm_bank_activate[bank] > TRAS_MAX) && (active_bank[bank] === 1'b1)) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
625                                                 if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
626            {1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
627            {1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
628            {1'b1, ACTIVATE , 4'b010x } : ; // tRCD is checked outside this task
629            {1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK
630            {1'b1, WRITE , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
631            {1'b0, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
632            {1'b0, WRITE , READ } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency)) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
633            {1'b0, WRITE , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && (
634                                                    |write_precharge_bank
635                                                 || (ck_cntr - ck_write_ap < 1)
636                                                 || (ck_cntr - ck_write < write_latency + burst_length/2 + 2)
637                                                 || ($time - tm_write_end < TWTR))) begin $display ("%m: at time %t INFO: Write to Reset condition", $time); init_done = 0; end end
638            {1'b1, READ , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
639            {1'b0, READ , WRITE } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency)) $display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank); end
640            {1'b0, READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
641            {1'b0, READ , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1)) begin $display ("%m: at time %t INFO: Read to Reset condition", $time); init_done = 0; end end
642            {1'b0, PWR_DOWN , 4'b00xx } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
643            {1'b0, PWR_DOWN , WRITE } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
644            {1'b0, PWR_DOWN , READ } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency) $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]);
645                                            else if (ck_cntr - ck_power_down < TXARD) $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]); end
646            {1'b0, SELF_REF , 4'b00xx } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
647            {1'b0, SELF_REF , WRITE } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
648            {1'b0, SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSRD) $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]); end
649            {1'b0, 4'b100x , 4'b100x } : begin if (ck_cntr - ck_cke < TCKE) begin $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); init_done = 0; end end
650        endcase
651    end
652    endtask
653
654    task cmd_task;
655        input cke;
656        input [2:0] cmd;
657        input [BA_BITS-1:0] bank;
658        input [ADDR_BITS-1:0] addr;
659        reg [`BANKS:0] i;
660        integer j;
661        reg [`BANKS:0] tfaw_cntr;
662        reg [COL_BITS-1:0] col;
663        begin
664
665            // tRFC max check
666            if (!er_trfc_max && !in_self_refresh) begin
667                if ($time - tm_refresh > TRFC_MAX) begin
668                    $display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
669                    er_trfc_max = 1;
670                end
671            end
672            if (cke) begin
673                if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin
674                    for (j=0; j<NOP; j=j+1) begin
675                        chk_err(1'b0, bank, j, cmd);
676                        chk_err(1'b1, bank, j, cmd);
677                    end
678                    chk_err(1'b0, bank, PWR_DOWN, cmd);
679                    chk_err(1'b0, bank, SELF_REF, cmd);
680                end
681
682                case (cmd)
683                    LOAD_MODE : begin
684                        if (|active_bank) begin
685                            $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
686                            if (STOP_ON_ERROR) $stop(0);
687                        end else begin
688                            if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
689                            case (bank)
690                                0 : begin
691                                    // Burst Length
692                                    burst_length = 1<<addr[2:0];
693                                    if ((burst_length >= BL_MIN) && (burst_length <= BL_MAX)) begin
694                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
695                                    end else begin
696                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
697                                    end
698                                    // Burst Order
699                                    burst_order = addr[3];
700                                    if (!burst_order) begin
701                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
702                                    end else if (burst_order) begin
703                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
704                                    end else begin
705                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
706                                    end
707                                    // CAS Latency
708                                    cas_latency = addr[6:4];
709                                    read_latency = cas_latency + additive_latency;
710                                    write_latency = read_latency - 1;
711                                    if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
712                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
713                                    end else begin
714                                        $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
715                                    end
716                                    // Test Mode
717                                    if (!addr[7]) begin
718                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank);
719                                    end else begin
720                                        $display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]);
721                                    end
722                                    // DLL Reset
723                                    dll_reset = addr[8];
724                                    if (!dll_reset) begin
725                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
726                                    end else if (dll_reset) begin
727                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
728                                        dll_locked = 0;
729                                        ck_dll_reset <= ck_cntr;
730                                    end else begin
731                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
732                                    end
733                                    // Write Recovery
734                                    write_recovery = addr[11:9] + 1;
735                                    if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
736                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
737                                    end else begin
738                                        $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
739                                    end
740                                    // Power Down Mode
741                                    low_power = addr[12];
742                                    if (!low_power) begin
743                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank);
744                                    end else if (low_power) begin
745                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank);
746                                    end else begin
747                                        $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
748                                    end
749                                end
750                                1 : begin
751                                    // DLL Enable
752                                    dll_en = !addr[0];
753                                    if (!dll_en) begin
754                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
755                                    end else if (dll_en) begin
756                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
757                                    end else begin
758                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
759                                    end
760                                    // Output Drive Strength
761                                    if (!addr[1]) begin
762                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank);
763                                    end else if (addr[1]) begin
764                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank);
765                                    end else begin
766                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]);
767                                    end
768                                    // ODT Rtt
769                                    odt_rtt = {addr[6], addr[2]};
770                                    if (odt_rtt == 2'b00) begin
771                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
772                                        odt_en = 0;
773                                    end else if (odt_rtt == 2'b01) begin
774                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank);
775                                        odt_en = 1;
776                                        tm_odt_en <= $time;
777                                    end else if (odt_rtt == 2'b10) begin
778                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank);
779                                        odt_en = 1;
780                                        tm_odt_en <= $time;
781                                    end else if (odt_rtt == 2'b11) begin
782                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank);
783                                        odt_en = 1;
784                                        tm_odt_en <= $time;
785                                    end else begin
786                                        $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt);
787                                        odt_en = 0;
788                                    end
789                                    // Additive Latency
790                                    additive_latency = addr[5:3];
791                                    read_latency = cas_latency + additive_latency;
792                                    write_latency = read_latency - 1;
793                                    if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin
794                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
795                                    end else begin
796                                        $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
797                                    end
798                                    // OCD Program
799                                    ocd = addr[9:7];
800                                    if (ocd == 3'b000) begin
801                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank);
802                                    end else if (ocd == 3'b111) begin
803                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank);
804                                    end else begin
805                                        $display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd);
806                                    end
807
808                                    // DQS_N Enable
809                                    dqs_n_en = !addr[10];
810                                    if (!dqs_n_en) begin
811                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank);
812                                    end else if (dqs_n_en) begin
813                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank);
814                                    end else begin
815                                        $display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en);
816                                    end
817                                    // RDQS Enable
818                                    rdqs_en = addr[11];
819                                    if (!rdqs_en) begin
820                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank);
821                                    end else if (rdqs_en) begin
822`ifdef x8
823                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank);
824`else
825                                        $display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable. RDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
826                                        rdqs_en = 0;
827`endif
828                                    end else begin
829                                        $display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en);
830                                    end
831                                    // Output Enable
832                                    out_en = !addr[12];
833                                    if (!out_en) begin
834                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank);
835                                    end else if (out_en) begin
836                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank);
837                                    end else begin
838                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en);
839                                    end
840                                end
841                                2 : begin
842                                    // High Temperature Self Refresh rate
843                                    if (!addr[7]) begin
844                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 1X (0C-85C)", $time, cmd_string[cmd], bank);
845                                    end else if (addr[7]) begin
846                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 2X (>85C)", $time, cmd_string[cmd], bank);
847                                    end else begin
848                                        $display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]);
849                                    end
850                                    if ((addr & ~(1<<7)) !== 0) begin
851                                        $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
852                                    end
853                                end
854                                3 : begin
855                                    if (addr !== 0) begin
856                                        $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
857                                    end
858                                end
859                            endcase
860                            init_mode_reg[bank] = 1;
861                            ck_load_mode <= ck_cntr;
862                        end
863                    end
864                    REFRESH : begin
865                        if (|active_bank) begin
866                            $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
867                            if (STOP_ON_ERROR) $stop(0);
868                        end else begin
869                            if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
870                            er_trfc_max = 0;
871                            ref_cntr = ref_cntr + 1;
872                            tm_refresh <= $time;
873                        end
874                    end
875                    PRECHARGE : begin
876                        if (addr[AP]) begin
877                            // tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
878                            // the number of banks already open or closed.
879                            for (i=0; i<`BANKS; i=i+1) begin
880                                for (j=0; j<NOP; j=j+1) begin
881                                    chk_err(1'b0, i, j, cmd);
882                                    chk_err(1'b1, i, j, cmd);
883                                end
884                                chk_err(1'b0, i, PWR_DOWN, cmd);
885                                chk_err(1'b0, i, SELF_REF, cmd);
886                            end
887                            if (|auto_precharge_bank) begin
888                                $display ("%m: at time %t ERROR: %s All Failure. Auto Precharge is scheduled.", $time, cmd_string[cmd]);
889                                if (STOP_ON_ERROR) $stop(0);
890                            end else begin
891                                if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
892                                active_bank = 0;
893                                tm_precharge_all <= $time;
894                            end
895                        end else begin
896                            // A PRECHARGE command is allowed if there is no open row in that bank (idle state)
897                            // or if the previously open row is already in the process of precharging.
898                            // However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
899                            if (auto_precharge_bank[bank]) begin
900                                $display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
901                                if (STOP_ON_ERROR) $stop(0);
902                            end else begin
903                                if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], bank);
904                                active_bank[bank] = 1'b0;
905                                tm_bank_precharge[bank] <= $time;
906                                tm_precharge <= $time;
907                            end
908                        end
909                    end
910                    ACTIVATE : begin
911                        if (`BANKS == 8) begin
912                            tfaw_cntr = 0;
913                            for (i=0; i<`BANKS; i=i+1) begin
914                                if ($time - tm_bank_activate[i] < TFAW) begin
915                                    tfaw_cntr = tfaw_cntr + 1;
916                                end
917                            end
918                            if (tfaw_cntr > 3) begin
919                                $display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
920                            end
921                        end
922
923                        if (!init_done) begin
924                            $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
925                            if (STOP_ON_ERROR) $stop(0);
926                        end else if (active_bank[bank]) begin
927                            $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
928                            if (STOP_ON_ERROR) $stop(0);
929                        end else begin
930                            if (addr >= 1<<ROW_BITS) begin
931                                $display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
932                            end
933                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
934                            active_bank[bank] = 1'b1;
935                            active_row[bank] = addr;
936                            tm_bank_activate[bank] <= $time;
937                            tm_activate <= $time;
938                        end
939                        
940                    end
941                    WRITE : begin
942                        if (!init_done) begin
943                            $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
944                            if (STOP_ON_ERROR) $stop(0);
945                        end else if (!active_bank[bank]) begin
946                            $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
947                            if (STOP_ON_ERROR) $stop(0);
948                        end else if (auto_precharge_bank[bank]) begin
949                            $display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
950                            if (STOP_ON_ERROR) $stop(0);
951                        end else if ((ck_cntr - ck_write < burst_length/2) && (ck_cntr - ck_write)%2) begin
952                            $display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
953                            if (STOP_ON_ERROR) $stop(0);
954                        end else begin
955                            if (addr[AP]) begin
956                                auto_precharge_bank[bank] = 1'b1;
957                                write_precharge_bank[bank] = 1'b1;
958                            end
959                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
960                            if (col >= 1<<COL_BITS) begin
961                                $display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
962                            end
963                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
964                            wr_pipeline[2*write_latency + 1] = 1;
965                            ba_pipeline[2*write_latency + 1] = bank;
966                            row_pipeline[2*write_latency + 1] = active_row[bank];
967                            col_pipeline[2*write_latency + 1] = col;
968                            ck_bank_write[bank] <= ck_cntr;
969                            ck_write <= ck_cntr;
970                        end
971                    end
972                    READ : begin
973                        if (!dll_locked)
974                            $display ("%m: at time %t WARNING: %s prior to DLL locked. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.", $time, cmd_string[cmd]);
975                        if (!init_done) begin
976                            $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
977                            if (STOP_ON_ERROR) $stop(0);
978                        end else if (!active_bank[bank]) begin
979                            $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
980                            if (STOP_ON_ERROR) $stop(0);
981                        end else if (auto_precharge_bank[bank]) begin
982                            $display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
983                            if (STOP_ON_ERROR) $stop(0);
984                        end else if ((ck_cntr - ck_read < burst_length/2) && (ck_cntr - ck_read)%2) begin
985                            $display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
986                            if (STOP_ON_ERROR) $stop(0);
987                        end else begin
988                            if (addr[AP]) begin
989                                auto_precharge_bank[bank] = 1'b1;
990                                read_precharge_bank[bank] = 1'b1;
991                            end
992                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
993                            if (col >= 1<<COL_BITS) begin
994                                $display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
995                            end
996                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
997                            rd_pipeline[2*read_latency - 1] = 1;
998                            ba_pipeline[2*read_latency - 1] = bank;
999                            row_pipeline[2*read_latency - 1] = active_row[bank];
1000                            col_pipeline[2*read_latency - 1] = col;
1001                            ck_bank_read[bank] <= ck_cntr;
1002                            ck_read <= ck_cntr;
1003                        end
1004                    end
1005                    NOP: begin
1006                        if (in_power_down) begin
1007                            if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
1008                            in_power_down = 0;
1009                            if (|active_bank & low_power) begin // slow exit active power down
1010                                ck_slow_exit_pd <= ck_cntr;
1011                            end
1012                            ck_power_down <= ck_cntr;
1013                        end
1014                        if (in_self_refresh) begin
1015                            if ($time - tm_cke < TISXR)
1016                                $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
1017                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
1018                            in_self_refresh = 0;
1019                            ck_dll_reset <= ck_cntr;
1020                            ck_self_refresh <= ck_cntr;
1021                            tm_self_refresh <= $time;
1022                            tm_refresh <= $time;
1023                        end
1024                    end
1025                endcase
1026                if ((prev_cke !== 1) && (cmd !== NOP)) begin
1027                    $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
1028                end
1029                if (!init_done) begin
1030                    case (init_step)
1031                        0 : begin
1032                            if ($time < 200000000)
1033                                $display ("%m: at time %t WARNING: 200 us is required before CKE goes active.", $time);
1034// if (cmd_chk + 200000000 > $time)
1035// $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time);
1036                            init_step = init_step + 1;
1037                        end
1038                        1 : if (dll_en) init_step = init_step + 1;
1039                        2 : begin
1040                            if (&init_mode_reg && dll_reset) begin
1041                                active_bank = {`BANKS{1'b1}}; // require Precharge All or bank Precharges
1042                                ref_cntr = 0; // require refresh
1043                                init_step = init_step + 1;
1044                            end
1045                        end
1046                        3 : if (ref_cntr == 2) begin
1047                            init_step = init_step + 1;
1048                        end
1049                        4 : if (!dll_reset) init_step = init_step + 1;
1050                        5 : if (ocd == 3'b111) init_step = init_step + 1;
1051                        6 : begin
1052                            if (ocd == 3'b000) begin
1053                                if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
1054                                init_done = 1;
1055                            end
1056                        end
1057                    endcase
1058                end
1059            end else if (prev_cke) begin
1060                if ((!init_done) && (init_step > 1)) begin
1061                    $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
1062                    if (STOP_ON_ERROR) $stop(0);
1063                end
1064                case (cmd)
1065                    REFRESH : begin
1066                        for (j=0; j<NOP; j=j+1) begin
1067                            chk_err(1'b0, bank, j, SELF_REF);
1068                        end
1069                        chk_err(1'b0, bank, PWR_DOWN, SELF_REF);
1070                        chk_err(1'b0, bank, SELF_REF, SELF_REF);
1071                        if (|active_bank) begin
1072                            $display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
1073                            if (STOP_ON_ERROR) $stop(0);
1074                            init_done = 0;
1075                        end else if (odt_en && odt_state) begin
1076                            $display ("%m: at time %t ERROR: ODT must be off prior to entering Self Refresh", $time);
1077                            if (STOP_ON_ERROR) $stop(0);
1078                            init_done = 0;
1079                        end else if (!init_done) begin
1080                            $display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
1081                            if (STOP_ON_ERROR) $stop(0);
1082                        end else begin
1083                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
1084                            in_self_refresh = 1;
1085                            dll_locked = 0;
1086                        end
1087                    end
1088                    NOP : begin
1089                        // entering slow_exit or precharge power down and tANPD has not been satisfied
1090                        if ((low_power || (active_bank == 0)) && (ck_cntr - ck_odt < TANPD))
1091                            $display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
1092                        for (j=0; j<NOP; j=j+1) begin
1093                            chk_err(1'b0, bank, j, PWR_DOWN);
1094                        end
1095                        chk_err(1'b0, bank, PWR_DOWN, PWR_DOWN);
1096                        chk_err(1'b0, bank, SELF_REF, PWR_DOWN);
1097
1098                        if (!init_done) begin
1099                            $display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
1100                            if (STOP_ON_ERROR) $stop(0);
1101                        end else begin
1102                            if (DEBUG) begin
1103                                if (|active_bank) begin
1104                                    $display ("%m: at time %t INFO: Active Power Down Enter", $time);
1105                                end else begin
1106                                    $display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
1107                                end
1108                            end
1109                            in_power_down = 1;
1110                        end
1111                    end
1112                    default : begin
1113                        $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
1114                        init_done = 0;
1115                    end
1116                endcase
1117                if (!init_done) begin
1118                    if (DEBUG) $display ("%m: at time %t WARNING: Reset has occurred. Device must be re-initialized.", $time);
1119                    reset_task;
1120                end
1121            end
1122            prev_cke = cke;
1123        end
1124    endtask
1125
1126    task data_task;
1127        reg [BA_BITS-1:0] bank;
1128        reg [ROW_BITS-1:0] row;
1129        reg [COL_BITS-1:0] col;
1130        integer i;
1131        integer j;
1132        begin
1133
1134            if (diff_ck) begin
1135                for (i=0; i<36; i=i+1) begin
1136                    if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
1137                        $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
1138                    if (check_write_dqs_high[i])
1139                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/18], i%18);
1140                end
1141                check_write_dqs_high <= 0;
1142            end else begin
1143                for (i=0; i<36; i=i+1) begin
1144                    if (dll_locked && dq_in_valid && (i % 18 < DQS_BITS)) begin // Only check valid DQS group
1145                        tm_tdqss = abs_value($itor(tm_ck_pos) - tm_dqss_pos[i]);
1146                        //$display ("at time %t, tm_tdqss = %0d, tm_ck_pos = %0d, tm_dqss_pos [%0d] = %0d", $time, tm_tdqss, tm_ck_pos, i, tm_dqss_pos[i]);
1147                        if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
1148                            $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
1149                    end
1150                    if (check_write_dqs_low[i])
1151                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18);
1152                end
1153                check_write_preamble <= 0;
1154                check_write_postamble <= 0;
1155                check_write_dqs_low <= 0;
1156            end
1157
1158            if (wr_pipeline[0] || rd_pipeline[0]) begin
1159                bank = ba_pipeline[0];
1160                row = row_pipeline[0];
1161                col = col_pipeline[0];
1162                burst_cntr = 0;
1163                memory_read(bank, row, col, memory_data);
1164            end
1165
1166            // burst counter
1167            if (burst_cntr < burst_length) begin
1168                burst_position = col ^ burst_cntr;
1169                if (!burst_order) begin
1170                    burst_position[BO_BITS-1:0] = col + burst_cntr;
1171                end
1172                burst_cntr = burst_cntr + 1;
1173            end
1174
1175            // write dqs counter
1176            if (wr_pipeline[WDQS_PRE + 1]) begin
1177                wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1;
1178            end
1179            // write dqs
1180            if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble
1181                check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
1182            end
1183            if (wdqs_cntr > 1) begin // write data
1184                if ((wdqs_cntr - WDQS_PST)%2) begin
1185                    check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
1186                end else begin
1187                    check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
1188                end
1189            end
1190            if (wdqs_cntr == WDQS_PST) begin // write postamble
1191                check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
1192            end
1193            if (wdqs_cntr > 0) begin
1194                wdqs_cntr = wdqs_cntr - 1;
1195            end
1196
1197            // write dq
1198            if (dq_in_valid) begin // write data
1199                bit_mask = 0;
1200                if (diff_ck) begin
1201                    for (i=0; i<DM_BITS; i=i+1) begin
1202                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
1203                    end
1204                    memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
1205                end else begin
1206                    for (i=0; i<DM_BITS; i=i+1) begin
1207                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
1208                    end
1209                    memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
1210                end
1211                dq_temp = memory_data>>(burst_position*DQ_BITS);
1212                if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
1213                if (burst_cntr%BL_MIN == 0) begin
1214                    memory_write(bank, row, col, memory_data);
1215                end
1216            end
1217            if (wr_pipeline[1]) begin
1218                wdq_cntr = burst_length;
1219            end
1220            if (wdq_cntr > 0) begin
1221                wdq_cntr = wdq_cntr - 1;
1222                dq_in_valid = 1'b1;
1223            end else begin
1224                dq_in_valid = 1'b0;
1225                dqs_in_valid <= 1'b0;
1226                for (i=0; i<36; i=i+1) begin
1227                    wdqs_pos_cntr[i] <= 0;
1228                end
1229            end
1230            if (wr_pipeline[0]) begin
1231                b2b_write <= 1'b0;
1232            end
1233            if (wr_pipeline[2]) begin
1234                if (dqs_in_valid) begin
1235                    b2b_write <= 1'b1;
1236                end
1237                dqs_in_valid <= 1'b1;
1238            end
1239            // read dqs enable counter
1240            if (rd_pipeline[RDQSEN_PRE]) begin
1241                rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1;
1242            end
1243            if (rdqsen_cntr > 0) begin
1244                rdqsen_cntr = rdqsen_cntr - 1;
1245                dqs_out_en = 1'b1;
1246            end else begin
1247                dqs_out_en = 1'b0;
1248            end
1249            
1250            // read dqs counter
1251            if (rd_pipeline[RDQS_PRE]) begin
1252                rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1;
1253            end
1254            // read dqs
1255            if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble
1256                dqs_out = 1'b0;
1257            end else if (rdqs_cntr > RDQS_PST) begin // read data
1258                dqs_out = rdqs_cntr - RDQS_PST;
1259            end else if (rdqs_cntr > 0) begin // read postamble
1260                dqs_out = 1'b0;
1261            end else begin
1262                dqs_out = 1'b1;
1263            end
1264            if (rdqs_cntr > 0) begin
1265                rdqs_cntr = rdqs_cntr - 1;
1266            end
1267
1268            // read dq enable counter
1269            if (rd_pipeline[RDQEN_PRE]) begin
1270                rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST;
1271            end
1272            if (rdqen_cntr > 0) begin
1273                rdqen_cntr = rdqen_cntr - 1;
1274                dq_out_en = 1'b1;
1275            end else begin
1276                dq_out_en = 1'b0;
1277            end
1278            // read dq
1279            if (rd_pipeline[0]) begin
1280                rdq_cntr = burst_length;
1281            end
1282            if (rdq_cntr > 0) begin // read data
1283                dq_temp = memory_data>>(burst_position*DQ_BITS);
1284                dq_out = dq_temp;
1285                if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
1286                rdq_cntr = rdq_cntr - 1;
1287            end else begin
1288                dq_out = {DQ_BITS{1'b1}};
1289            end
1290
1291            // delay signals prior to output
1292            if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin
1293                for (i=0; i<DQS_BITS; i=i+1) begin
1294                    // DQSCK requirements
1295                    // 1.) less than tDQSCK
1296                    // 2.) greater than -tDQSCK
1297                    // 3.) cannot change more than tQHS + tDQSQ from previous DQS edge
1298                    dqsck_max = TDQSCK;
1299                    if (dqsck_max > dqsck[i] + TQHS + TDQSQ) begin
1300                        dqsck_max = dqsck[i] + TQHS + TDQSQ;
1301                    end
1302                    dqsck_min = -1*TDQSCK;
1303                    if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin
1304                        dqsck_min = dqsck[i] - TQHS - TDQSQ;
1305                    end
1306
1307                    // DQSQ requirements
1308                    // 1.) less than tAC - DQSCK
1309                    // 2.) less than tDQSQ
1310                    // 3.) greater than -tAC
1311                    // 4.) greater than tQH from previous DQS edge
1312                    dqsq_min = -1*TAC;
1313                    if (dqsq_min < dqsck[i] - TQHS) begin
1314                        dqsq_min = dqsck[i] - TQHS;
1315                    end
1316                    if (dqsck_min == dqsck_max) begin
1317                        dqsck[i] = dqsck_min;
1318                    end else begin
1319                        dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
1320                    end
1321                    dqsq_max = TAC;
1322                    if (dqsq_max > TDQSQ + dqsck[i]) begin
1323                        dqsq_max = TDQSQ + dqsck[i];
1324                    end
1325
1326                    dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en;
1327                    dqs_out_dly[i] <= #(tck_avg/2.0 + dqsck[i]) dqs_out;
1328                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
1329                        if (dq_out_en) begin // tLZ2
1330                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en;
1331                        end else begin // tHZ
1332                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en;
1333                        end
1334                        if (dqsq_min == dqsq_max) begin
1335                            dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
1336                        end else begin
1337                            dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
1338                        end
1339                    end
1340                end
1341            end else begin
1342                out_delay = tck_avg/2.0;
1343                dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
1344                dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
1345                dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
1346                dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
1347            end
1348        end
1349    endtask
1350
1351    always @(diff_ck) begin : main
1352        integer i;
1353
1354        if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
1355            $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
1356        data_task;
1357        if (diff_ck) begin
1358            // check setup of command signals
1359            if ($time > TIS) begin
1360                if ($time - tm_cke < TIS)
1361                    $display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
1362                if (cke_in) begin
1363                    for (i=0; i<22; i=i+1) begin
1364                        if ($time - tm_cmd_addr[i] < TIS)
1365                            $display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
1366                    end
1367                end
1368            end
1369
1370            // update current state
1371            if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin
1372                // check CL value against the clock frequency
1373                if (cas_latency*tck_avg < CL_TIME)
1374                    $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
1375                // check WR value against the clock frequency
1376                if (write_recovery*tck_avg < TWR)
1377                    $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
1378                dll_locked = 1;
1379            end
1380            if (|auto_precharge_bank) begin
1381                for (i=0; i<`BANKS; i=i+1) begin
1382                    // Write with Auto Precharge Calculation
1383                    // 1. Meet minimum tRAS requirement
1384                    // 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
1385                    if (write_precharge_bank[i]
1386                        && ($time - tm_bank_activate[i] >= TRAS_MIN)
1387                        && (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin
1388
1389                        if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
1390                        write_precharge_bank[i] = 0;
1391                        active_bank[i] = 0;
1392                        auto_precharge_bank[i] = 0;
1393                        ck_write_ap = ck_cntr;
1394                        tm_bank_precharge[i] = $time;
1395                        tm_precharge = $time;
1396                    end
1397                    // Read with Auto Precharge Calculation
1398                    // 1. Meet minimum tRAS requirement
1399                    // 2. Additive Latency plus BL/2 cycles after Read command
1400                    // 3. tRTP after the last 4-bit prefetch
1401                    if (read_precharge_bank[i]
1402                        && ($time - tm_bank_activate[i] >= TRAS_MIN)
1403                        && (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin
1404
1405                        read_precharge_bank[i] = 0;
1406                        // In case the internal precharge is pushed out by tRTP, tRP starts at the point where
1407                        // the internal precharge happens (not at the next rising clock edge after this event).
1408                        if ($time - tm_bank_read_end[i] < TRTP) begin
1409                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
1410                            active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
1411                            auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
1412                            tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
1413                            tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
1414                        end else begin
1415                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
1416                            active_bank[i] = 0;
1417                            auto_precharge_bank[i] = 0;
1418                            tm_bank_precharge[i] = $time;
1419                            tm_precharge = $time;
1420                        end
1421                    end
1422                end
1423            end
1424
1425            // respond to incoming command
1426            if (cke_in ^ prev_cke) begin
1427                ck_cke <= ck_cntr;
1428            end
1429
1430            cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
1431            if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
1432                al_pipeline[2*additive_latency] = 1'b1;
1433            end
1434            if (al_pipeline[0]) begin
1435                // check tRCD after additive latency
1436                if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin
1437                    if (rd_pipeline[2*cas_latency - 1]) begin
1438                        $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
1439                    end else begin
1440                        $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
1441                    end
1442                end
1443                // check tWTR after additive latency
1444                if (rd_pipeline[2*cas_latency - 1]) begin
1445                    if ($time - tm_write_end < TWTR)
1446                        $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
1447                end
1448            end
1449            if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin
1450                tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time;
1451            end
1452            for (i=0; i<`BANKS; i=i+1) begin
1453                if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
1454                    tm_bank_write_end[i] <= $time;
1455                    tm_write_end <= $time;
1456                end
1457            end
1458
1459            // clk pin is disabled during self refresh
1460            if (!in_self_refresh) begin
1461                tjit_cc_time = $time - tm_ck_pos - tck_i;
1462                tck_i = $time - tm_ck_pos;
1463                tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
1464                tck_avg = tck_avg + tck_i/$itor(TDLLK);
1465                tck_sample[ck_cntr%TDLLK] = tck_i;
1466                tjit_per_rtime = tck_i - tck_avg;
1467
1468                if (dll_locked) begin
1469                    // check accumulated error
1470                    terr_nper_rtime = 0;
1471                    for (i=0; i<50; i=i+1) begin
1472                        terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
1473                        terr_nper_rtime = abs_value(terr_nper_rtime);
1474                        case (i)
1475                                  0 :;
1476                                  1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
1477                                  2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
1478                                  3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
1479                                  4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
1480                          5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER);
1481                            default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER);
1482                        endcase
1483                    end
1484
1485                    // check tCK min/max/jitter
1486                    if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
1487                        $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
1488                    if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
1489                        $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
1490                    if (TCK_MIN - tck_avg >= 1.0)
1491                        $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
1492                    if (tck_avg - TCK_MAX >= 1.0)
1493                        $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
1494                    if (tm_ck_pos + TCK_MIN - TJIT_PER > $time)
1495                        $display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time);
1496                    if (tm_ck_pos + TCK_MAX + TJIT_PER < $time)
1497                        $display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER);
1498
1499                    // check tCL
1500                    if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time)
1501                        $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time);
1502                    if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time)
1503                        $display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY);
1504                    if (tcl_avg < TCL_MIN*tck_avg)
1505                        $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg);
1506                    if (tcl_avg > TCL_MAX*tck_avg)
1507                        $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg);
1508                end
1509
1510                // calculate the tch avg jitter
1511                tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
1512                tch_avg = tch_avg + tch_i/$itor(TDLLK);
1513                tch_sample[ck_cntr%TDLLK] = tch_i;
1514
1515                // update timers/counters
1516                tcl_i <= $time - tm_ck_neg;
1517            end
1518
1519            prev_odt <= odt_in;
1520            // update timers/counters
1521            ck_cntr <= ck_cntr + 1;
1522            tm_ck_pos <= $time;
1523        end else begin
1524            // clk pin is disabled during self refresh
1525            if (!in_self_refresh) begin
1526                if (dll_locked) begin
1527                    if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time)
1528                        $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time);
1529                    if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time)
1530                        $display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY);
1531                    if (tch_avg < TCH_MIN*tck_avg)
1532                        $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg);
1533                    if (tch_avg > TCH_MAX*tck_avg)
1534                        $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg);
1535                end
1536
1537                // calculate the tcl avg jitter
1538                tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
1539                tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
1540                tcl_sample[ck_cntr%TDLLK] = tcl_i;
1541
1542                // update timers/counters
1543                tch_i <= $time - tm_ck_pos;
1544            end
1545            tm_ck_neg <= $time;
1546        end
1547
1548        // on die termination
1549        if (odt_en) begin
1550            // clk pin is disabled during self refresh
1551            if (!in_self_refresh && diff_ck) begin
1552                if ($time - tm_odt < TIS) begin
1553                    $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
1554                end
1555                if (prev_odt ^ odt_in) begin
1556                    if (!dll_locked)
1557                        $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
1558                    if (odt_in && ($time - tm_odt_en < TMOD))
1559                        $display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
1560                    if ($time - tm_self_refresh < TXSNR)
1561                        $display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time);
1562                    if (in_self_refresh)
1563                        $display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
1564
1565                    // async ODT mode applies:
1566                    // 1.) during active power down with slow exit
1567                    // 2.) during precharge power down
1568                    // 3.) if tANPD has not been satisfied
1569                    // 4.) until tAXPD has been satisfied
1570                    if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin
1571                        if (ck_cntr - ck_slow_exit_pd < TAXPD)
1572                            $display ("%m: at time %t WARNING: tAXPD violation during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
1573                        if (odt_in) begin
1574                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1);
1575                            odt_state <= #(TAONPD) 1'b1;
1576                        end else begin
1577                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0);
1578                            odt_state <= #(TAOFPD) 1'b0;
1579                        end
1580                    // sync ODT mode applies:
1581                    // 1.) during normal operation
1582                    // 2.) during active power down with fast exit
1583                    end else begin
1584                        if (odt_in) begin
1585                            i = TAOND*2;
1586                            odt_pipeline[i] = 1'b1;
1587                        end else begin
1588                            i = TAOFD*2;
1589                            odt_pipeline[i] = 1'b1;
1590                        end
1591                    end
1592                    ck_odt <= ck_cntr;
1593                end
1594            end
1595            if (odt_pipeline[0]) begin
1596                odt_state = ~odt_state;
1597                if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state);
1598            end
1599        end
1600
1601        // shift pipelines
1602        if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
1603            al_pipeline = al_pipeline>>1;
1604            wr_pipeline = wr_pipeline>>1;
1605            rd_pipeline = rd_pipeline>>1;
1606            for (i=0; i<`MAX_PIPE; i=i+1) begin
1607                ba_pipeline[i] = ba_pipeline[i+1];
1608                row_pipeline[i] = row_pipeline[i+1];
1609                col_pipeline[i] = col_pipeline[i+1];
1610            end
1611        end
1612        if (|odt_pipeline) begin
1613            odt_pipeline = odt_pipeline>>1;
1614        end
1615    end
1616
1617    // receiver(s)
1618    task dqs_even_receiver;
1619        input [4:0] i;
1620        reg [71:0] bit_mask;
1621        begin
1622            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
1623            if (dqs_even[i]) begin
1624                if (rdqs_en) begin // rdqs disables dm
1625                    dm_in_pos[i] = 1'b0;
1626                end else begin
1627                    dm_in_pos[i] = dm_in[i];
1628                end
1629                dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
1630            end
1631        end
1632    endtask
1633
1634    always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
1635    always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
1636    always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
1637    always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
1638    always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
1639    always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
1640    always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
1641    always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
1642    always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
1643    always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
1644    always @(posedge dqs_even[10]) dqs_even_receiver(10);
1645    always @(posedge dqs_even[11]) dqs_even_receiver(11);
1646    always @(posedge dqs_even[12]) dqs_even_receiver(12);
1647    always @(posedge dqs_even[13]) dqs_even_receiver(13);
1648    always @(posedge dqs_even[14]) dqs_even_receiver(14);
1649    always @(posedge dqs_even[15]) dqs_even_receiver(15);
1650    always @(posedge dqs_even[16]) dqs_even_receiver(16);
1651    always @(posedge dqs_even[17]) dqs_even_receiver(17);
1652
1653    task dqs_odd_receiver;
1654        input [4:0] i;
1655        reg [71:0] bit_mask;
1656        begin
1657            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
1658            if (dqs_odd[i]) begin
1659                if (rdqs_en) begin // rdqs disables dm
1660                    dm_in_neg[i] = 1'b0;
1661                end else begin
1662                    dm_in_neg[i] = dm_in[i];
1663                end
1664                dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
1665            end
1666        end
1667    endtask
1668
1669    always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
1670    always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
1671    always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
1672    always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
1673    always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
1674    always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
1675    always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
1676    always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
1677    always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
1678    always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
1679    always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
1680    always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
1681    always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
1682    always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
1683    always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
1684    always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
1685    always @(posedge dqs_odd[16]) dqs_odd_receiver(16);
1686    always @(posedge dqs_odd[17]) dqs_odd_receiver(17);
1687 
1688    // Processes to check hold and pulse width of control signals
1689    always @(cke_in) begin
1690        if ($time > TIH) begin
1691            if ($time - tm_ck_pos < TIH)
1692                $display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
1693        end
1694        if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg)))
1695            $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time);
1696        tm_cke = $time;
1697    end
1698    always @(odt_in) begin
1699        if (odt_en && !in_self_refresh) begin
1700            if ($time - tm_ck_pos < TIH)
1701                $display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
1702            if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg)))
1703                $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time);
1704        end
1705        tm_odt = $time;
1706    end
1707
1708    task cmd_addr_timing_check;
1709    input i;
1710    reg [4:0] i;
1711    begin
1712        if (prev_cke) begin
1713            if ((i == 0) && ($time - tm_ck_pos < TIH)) // Always check tIH for CS#
1714                $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
1715            if ((i > 0) && (cs_n_in == 1'b0) && ($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# low
1716                $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
1717            if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg)))
1718                $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time);
1719        end
1720        tm_cmd_addr[i] = $time;
1721    end
1722    endtask
1723
1724    always @(cs_n_in ) cmd_addr_timing_check( 0);
1725    always @(ras_n_in ) cmd_addr_timing_check( 1);
1726    always @(cas_n_in ) cmd_addr_timing_check( 2);
1727    always @(we_n_in ) cmd_addr_timing_check( 3);
1728    always @(ba_in [ 0]) cmd_addr_timing_check( 4);
1729    always @(ba_in [ 1]) cmd_addr_timing_check( 5);
1730    always @(ba_in [ 2]) cmd_addr_timing_check( 6);
1731    always @(addr_in[ 0]) cmd_addr_timing_check( 7);
1732    always @(addr_in[ 1]) cmd_addr_timing_check( 8);
1733    always @(addr_in[ 2]) cmd_addr_timing_check( 9);
1734    always @(addr_in[ 3]) cmd_addr_timing_check(10);
1735    always @(addr_in[ 4]) cmd_addr_timing_check(11);
1736    always @(addr_in[ 5]) cmd_addr_timing_check(12);
1737    always @(addr_in[ 6]) cmd_addr_timing_check(13);
1738    always @(addr_in[ 7]) cmd_addr_timing_check(14);
1739    always @(addr_in[ 8]) cmd_addr_timing_check(15);
1740    always @(addr_in[ 9]) cmd_addr_timing_check(16);
1741    always @(addr_in[10]) cmd_addr_timing_check(17);
1742    always @(addr_in[11]) cmd_addr_timing_check(18);
1743    always @(addr_in[12]) cmd_addr_timing_check(19);
1744    always @(addr_in[13]) cmd_addr_timing_check(20);
1745    always @(addr_in[14]) cmd_addr_timing_check(21);
1746    always @(addr_in[15]) cmd_addr_timing_check(22);
1747
1748    // Processes to check setup and hold of data signals
1749    task dm_timing_check;
1750    input i;
1751    reg [4:0] i;
1752    begin
1753        if (dqs_in_valid) begin
1754            if ($time - tm_dqs[i] < TDH)
1755                $display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
1756            if (check_dm_tdipw[i]) begin
1757                if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg)))
1758                    $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time);
1759            end
1760        end
1761        check_dm_tdipw[i] <= 1'b0;
1762        tm_dm[i] = $time;
1763    end
1764    endtask
1765
1766    always @(dm_in[ 0]) dm_timing_check( 0);
1767    always @(dm_in[ 1]) dm_timing_check( 1);
1768    always @(dm_in[ 2]) dm_timing_check( 2);
1769    always @(dm_in[ 3]) dm_timing_check( 3);
1770    always @(dm_in[ 4]) dm_timing_check( 4);
1771    always @(dm_in[ 5]) dm_timing_check( 5);
1772    always @(dm_in[ 6]) dm_timing_check( 6);
1773    always @(dm_in[ 7]) dm_timing_check( 7);
1774    always @(dm_in[ 8]) dm_timing_check( 8);
1775    always @(dm_in[ 9]) dm_timing_check( 9);
1776    always @(dm_in[10]) dm_timing_check(10);
1777    always @(dm_in[11]) dm_timing_check(11);
1778    always @(dm_in[12]) dm_timing_check(12);
1779    always @(dm_in[13]) dm_timing_check(13);
1780    always @(dm_in[14]) dm_timing_check(14);
1781    always @(dm_in[15]) dm_timing_check(15);
1782    always @(dm_in[16]) dm_timing_check(16);
1783    always @(dm_in[17]) dm_timing_check(17);
1784
1785    task dq_timing_check;
1786    input i;
1787    reg [6:0] i;
1788    begin
1789        if (dqs_in_valid) begin
1790            if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
1791                $display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
1792            if (check_dq_tdipw[i]) begin
1793                if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg)))
1794                    $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time);
1795            end
1796        end
1797        check_dq_tdipw[i] <= 1'b0;
1798        tm_dq[i] = $time;
1799    end
1800    endtask
1801
1802    always @(dq_in[ 0]) dq_timing_check( 0);
1803    always @(dq_in[ 1]) dq_timing_check( 1);
1804    always @(dq_in[ 2]) dq_timing_check( 2);
1805    always @(dq_in[ 3]) dq_timing_check( 3);
1806    always @(dq_in[ 4]) dq_timing_check( 4);
1807    always @(dq_in[ 5]) dq_timing_check( 5);
1808    always @(dq_in[ 6]) dq_timing_check( 6);
1809    always @(dq_in[ 7]) dq_timing_check( 7);
1810    always @(dq_in[ 8]) dq_timing_check( 8);
1811    always @(dq_in[ 9]) dq_timing_check( 9);
1812    always @(dq_in[10]) dq_timing_check(10);
1813    always @(dq_in[11]) dq_timing_check(11);
1814    always @(dq_in[12]) dq_timing_check(12);
1815    always @(dq_in[13]) dq_timing_check(13);
1816    always @(dq_in[14]) dq_timing_check(14);
1817    always @(dq_in[15]) dq_timing_check(15);
1818    always @(dq_in[16]) dq_timing_check(16);
1819    always @(dq_in[17]) dq_timing_check(17);
1820    always @(dq_in[18]) dq_timing_check(18);
1821    always @(dq_in[19]) dq_timing_check(19);
1822    always @(dq_in[20]) dq_timing_check(20);
1823    always @(dq_in[21]) dq_timing_check(21);
1824    always @(dq_in[22]) dq_timing_check(22);
1825    always @(dq_in[23]) dq_timing_check(23);
1826    always @(dq_in[24]) dq_timing_check(24);
1827    always @(dq_in[25]) dq_timing_check(25);
1828    always @(dq_in[26]) dq_timing_check(26);
1829    always @(dq_in[27]) dq_timing_check(27);
1830    always @(dq_in[28]) dq_timing_check(28);
1831    always @(dq_in[29]) dq_timing_check(29);
1832    always @(dq_in[30]) dq_timing_check(30);
1833    always @(dq_in[31]) dq_timing_check(31);
1834    always @(dq_in[32]) dq_timing_check(32);
1835    always @(dq_in[33]) dq_timing_check(33);
1836    always @(dq_in[34]) dq_timing_check(34);
1837    always @(dq_in[35]) dq_timing_check(35);
1838    always @(dq_in[36]) dq_timing_check(36);
1839    always @(dq_in[37]) dq_timing_check(37);
1840    always @(dq_in[38]) dq_timing_check(38);
1841    always @(dq_in[39]) dq_timing_check(39);
1842    always @(dq_in[40]) dq_timing_check(40);
1843    always @(dq_in[41]) dq_timing_check(41);
1844    always @(dq_in[42]) dq_timing_check(42);
1845    always @(dq_in[43]) dq_timing_check(43);
1846    always @(dq_in[44]) dq_timing_check(44);
1847    always @(dq_in[45]) dq_timing_check(45);
1848    always @(dq_in[46]) dq_timing_check(46);
1849    always @(dq_in[47]) dq_timing_check(47);
1850    always @(dq_in[48]) dq_timing_check(48);
1851    always @(dq_in[49]) dq_timing_check(49);
1852    always @(dq_in[50]) dq_timing_check(50);
1853    always @(dq_in[51]) dq_timing_check(51);
1854    always @(dq_in[52]) dq_timing_check(52);
1855    always @(dq_in[53]) dq_timing_check(53);
1856    always @(dq_in[54]) dq_timing_check(54);
1857    always @(dq_in[55]) dq_timing_check(55);
1858    always @(dq_in[56]) dq_timing_check(56);
1859    always @(dq_in[57]) dq_timing_check(57);
1860    always @(dq_in[58]) dq_timing_check(58);
1861    always @(dq_in[59]) dq_timing_check(59);
1862    always @(dq_in[60]) dq_timing_check(60);
1863    always @(dq_in[61]) dq_timing_check(61);
1864    always @(dq_in[62]) dq_timing_check(62);
1865    always @(dq_in[63]) dq_timing_check(63);
1866    always @(dq_in[64]) dq_timing_check(64);
1867    always @(dq_in[65]) dq_timing_check(65);
1868    always @(dq_in[66]) dq_timing_check(66);
1869    always @(dq_in[67]) dq_timing_check(67);
1870    always @(dq_in[68]) dq_timing_check(68);
1871    always @(dq_in[69]) dq_timing_check(69);
1872    always @(dq_in[70]) dq_timing_check(70);
1873    always @(dq_in[71]) dq_timing_check(71);
1874
1875    task dqs_pos_timing_check;
1876    input i;
1877    reg [5:0] i;
1878    reg [3:0] j;
1879    begin
1880        if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin
1881            if (dqs_in[i] ^ prev_dqs_in[i]) begin
1882                if (dll_locked) begin
1883                    if (check_write_preamble[i]) begin
1884                        if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg))
1885                            $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18);
1886                    end else if (check_write_postamble[i]) begin
1887                        if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
1888                            $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18);
1889                    end else begin
1890                        if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
1891                            $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18);
1892                    end
1893                end
1894                if ($time - tm_dm[i%18] < TDS)
1895                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time);
1896                if (!dq_out_en) begin
1897                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
1898                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
1899                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
1900                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
1901                    end
1902                end
1903                if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin
1904                    wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
1905                end else begin
1906                    wdqs_pos_cntr[i] <= 1;
1907                end
1908                check_dm_tdipw[i%18] <= 1'b1;
1909                check_write_preamble[i] <= 1'b0;
1910                check_write_postamble[i] <= 1'b0;
1911                check_write_dqs_low[i] <= 1'b0;
1912                tm_dqs[i%18] <= $time;
1913            end else begin
1914                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
1915            end
1916        end
1917        tm_dqss_pos[i] <= $time;
1918        tm_dqs_pos[i] = $time;
1919        prev_dqs_in[i] <= dqs_in[i];
1920    end
1921    endtask
1922
1923    always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
1924    always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
1925    always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
1926    always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
1927    always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
1928    always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
1929    always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
1930    always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
1931    always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
1932    always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
1933    always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
1934    always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
1935    always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
1936    always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
1937    always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
1938    always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
1939    always @(posedge dqs_in[16]) dqs_pos_timing_check(16);
1940    always @(posedge dqs_in[17]) dqs_pos_timing_check(17);
1941    always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
1942    always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
1943    always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
1944    always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
1945    always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
1946    always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
1947    always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
1948    always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
1949    always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
1950    always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
1951    always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
1952    always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
1953    always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
1954    always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
1955    always @(negedge dqs_in[32]) dqs_neg_timing_check(32);
1956    always @(negedge dqs_in[33]) dqs_neg_timing_check(33);
1957    always @(negedge dqs_in[34]) dqs_neg_timing_check(34);
1958    always @(negedge dqs_in[35]) dqs_neg_timing_check(35);
1959
1960    task dqs_neg_timing_check;
1961    input i;
1962    reg [5:0] i;
1963    reg [3:0] j;
1964    begin
1965        if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin
1966            if (dqs_in[i] ^ prev_dqs_in[i]) begin
1967                if (dll_locked) begin
1968                    if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
1969                        $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
1970                    if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
1971                        $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
1972                end
1973                if ($time - tm_dm[i%18] < TDS)
1974                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time);
1975                if (!dq_out_en) begin
1976                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
1977                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
1978                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
1979                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
1980                    end
1981                end
1982                check_dm_tdipw[i%18] <= 1'b1;
1983                check_write_dqs_high[i] <= 1'b0;
1984                tm_dqs[i%18] <= $time;
1985            end else begin
1986                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
1987            end
1988        end
1989        tm_dqs_neg[i] = $time;
1990        prev_dqs_in[i] <= dqs_in[i];
1991    end
1992    endtask
1993
1994    always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
1995    always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
1996    always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
1997    always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
1998    always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
1999    always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
2000    always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
2001    always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
2002    always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
2003    always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
2004    always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
2005    always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
2006    always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
2007    always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
2008    always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
2009    always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
2010    always @(negedge dqs_in[16]) dqs_neg_timing_check(16);
2011    always @(negedge dqs_in[17]) dqs_neg_timing_check(17);
2012    always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
2013    always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
2014    always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
2015    always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
2016    always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
2017    always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
2018    always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
2019    always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
2020    always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
2021    always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
2022    always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
2023    always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
2024    always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
2025    always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
2026    always @(posedge dqs_in[32]) dqs_neg_timing_check(32);
2027    always @(posedge dqs_in[33]) dqs_neg_timing_check(33);
2028    always @(posedge dqs_in[34]) dqs_neg_timing_check(34);
2029    always @(posedge dqs_in[35]) dqs_neg_timing_check(35);
2030
2031endmodule
2032

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