Root/sim/verilog/micron_2048Mb_ddr2/ddr2_mcp.v

1/****************************************************************************************
2*
3* File Name: ddr2_mcp.v
4*
5* Dependencies: ddr2.v, ddr2_parameters.vh
6*
7* Description: Micron SDRAM DDR2 (Double Data Rate 2) multi-chip package model
8*
9* Disclaimer This software code and all associated documentation, comments or other
10* of Warranty: information (collectively "Software") is provided "AS IS" without
11* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
12* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
13* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
14* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
15* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
16* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
17* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
18* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
19* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
20* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
21* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
22* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
23* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
24* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
25* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
26* DAMAGES. Because some jurisdictions prohibit the exclusion or
27* limitation of liability for consequential or incidental damages, the
28* above limitation may not apply to you.
29*
30* Copyright 2003 Micron Technology, Inc. All rights reserved.
31*
32****************************************************************************************/
33 `timescale 1ps / 1ps
34
35module ddr2_mcp (
36    ck,
37    ck_n,
38    cke,
39    cs_n,
40    ras_n,
41    cas_n,
42    we_n,
43    dm_rdqs,
44    ba,
45    addr,
46    dq,
47    dqs,
48    dqs_n,
49    rdqs_n,
50    odt
51);
52
53    `include "ddr2_parameters.vh"
54
55    // Declare Ports
56    input ck;
57    input ck_n;
58    input [CS_BITS-1:0] cke;
59    input [CS_BITS-1:0] cs_n;
60    input ras_n;
61    input cas_n;
62    input we_n;
63    inout [DM_BITS-1:0] dm_rdqs;
64    input [BA_BITS-1:0] ba;
65    input [ADDR_BITS-1:0] addr;
66    inout [DQ_BITS-1:0] dq;
67    inout [DQS_BITS-1:0] dqs;
68    inout [DQS_BITS-1:0] dqs_n;
69    output [DQS_BITS-1:0] rdqs_n;
70    input [CS_BITS-1:0] odt;
71
72    wire [RANKS-1:0] cke_mcp = cke;
73    wire [RANKS-1:0] cs_n_mcp = cs_n;
74    wire [RANKS-1:0] odt_mcp = odt;
75
76    ddr2 rank [RANKS-1:0] (
77        ck,
78        ck_n,
79        cke_mcp,
80        cs_n_mcp,
81        ras_n,
82        cas_n,
83        we_n,
84        dm_rdqs,
85        ba,
86        addr,
87        dq,
88        dqs,
89        dqs_n,
90        rdqs_n,
91        odt_mcp
92    );
93
94endmodule
95

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