Root/sim/verilog/micron_2048Mb_ddr2/readme.txt

1Disclaimer of Warranty:
2-----------------------
3This software code and all associated documentation, comments or other
4information (collectively "Software") is provided "AS IS" without
5warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
6DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
7TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
8OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
9WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
10OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
11FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
12THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
13ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
14OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
15ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
16INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
17WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
18OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
19THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
20DAMAGES. Because some jurisdictions prohibit the exclusion or
21limitation of liability for consequential or incidental damages, the
22above limitation may not apply to you.
23
24Copyright 2003 Micron Technology, Inc. All rights reserved.
25
26Getting Started:
27----------------
28Unzip the included files to a folder.
29Compile ddr2.v, ddr2_mcp.v, and tb.v using a verilog simulator.
30Simulate the top level test bench tb.
31Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
32
33File Descriptions:
34------------------
35ddr2.v -ddr2 model
36ddr2_mcp.v -structural wrapper for ddr2 - multi-chip package model
37ddr2_module.v -structural wrapper for ddr2 - module model
38ddr2_parameters.vh -file that contains all parameters used by the model
39readme.txt -this file
40tb.v -ddr2 model test bench
41subtest.vh -example test included by the test bench.
42tb.do -compiles and runs the ddr2 model and test bench
43
44Defining the Speed Grade:
45-------------------------
46The verilog compiler directive "`define" may be used to choose between
47multiple speed grades supported by the ddr2 model. Allowable speed
48grades are listed in the ddr2_parameters.vh file and begin with the
49letters "sg". The speed grade is used to select a set of timing
50parameters for the ddr2 model. The following are examples of defining
51the speed grade.
52
53    simulator command line
54    --------- ------------
55    ModelSim vlog +define+sg5 ddr2.v
56    NC-Verilog ncverilog +define+sg5 ddr2.v
57    VCS vcs +define+sg5 ddr2.v
58
59Defining the Organization:
60--------------------------
61The verilog compiler directive "`define" may be used to choose between
62multiple organizations supported by the ddr2 model. Valid
63organizations include "x4", "x8", and x16, and are listed in the
64ddr2_parameters.vh file. The organization is used to select the amount
65of memory and the port sizes of the ddr2 model. The following are
66examples of defining the organization.
67
68    simulator command line
69    --------- ------------
70    ModelSim vlog +define+x8 ddr2.v
71    NC-Verilog ncverilog +define+x8 ddr2.v
72    VCS vcs +define+x8 ddr2.v
73
74All combinations of speed grade and organization are considered valid
75by the ddr2 model even though a Micron part may not exist for every
76combination.
77
78Allocating Memory:
79------------------
80An associative array has been implemented to reduce the amount of
81static memory allocated by the ddr2 model. Each entry in the
82associative array is a burst length of eight in size. The number of
83entries in the associative array is controlled by the MEM_BITS
84parameter, and is equal to 2^MEM_BITS. For example, if the MEM_BITS
85parameter is equal to 10, the associative array will be large enough
86to store 1024 writes of burst length 8 to unique addresses. The
87following are examples of setting the MEM_BITS parameter to 8.
88
89    simulator command line
90    --------- ------------
91    ModelSim vsim -GMEM_BITS=8 ddr2
92    NC-Verilog ncverilog +defparam+ddr2.MEM_BITS=8 ddr2.v
93    VCS vcs -pvalue+MEM_BITS=8 ddr2.v
94
95It is possible to allocate memory for every address supported by the
96ddr2 model by using the verilog compiler directive "`define MAX_MEM".
97This procedure will improve simulation performance at the expense of
98system memory. The following are examples of allocating memory for
99every address.
100
101    Simulator command line
102    --------- ------------
103    ModelSim vlog +define+MAX_MEM ddr2.v
104    NC-Verilog ncverilog +define+MAX_MEM ddr2.v
105    VCS vcs +define+MAX_MEM ddr2.v
106
107
108**********************************************************************
109The following information is provided to assist the modeling engineer
110in creating multi-chip package (mcp) models. ddr2_mcp.v is a
111structural wrapper that instantiates ddr2 models. This wrapper can be
112used to create single, dual, or quad rank mcp models. From the
113perspective of the model, the only item that needs to be defined is the
114number of ranks.
115**********************************************************************
116
117Defining the Number of Ranks in a multi-chip package:
118----------------------------------------------------
119The verilog compiler directive "`define" may be used to choose between
120single, dual, and quad rank mcp configurations. The default is single
121rank if nothing is defined. Dual rank configuration can be selected by
122defining "DUAL_RANK" when the ddr2_mcp is compiled. Quad rank
123configuration can be selected by defining "QUAD_RANK" when the ddr2_mcp
124is compiled. The following are examples of defining a dual rank mcp
125configuration.
126
127    simulator command line
128    --------- ------------
129    ModelSim vlog +define+DUAL_RANK ddr2.v ddr2_mcp.v
130    NC-Verilog ncverilog +define+DUAL_RANK ddr2.v ddr2_mcp.v
131    VCS vcs +define+DUAL_RANK ddr2.v ddr2_mcp.v
132
133
134**********************************************************************
135The following information is provided to assist the modeling engineer
136in creating DIMM models. ddr2_module.v is a structural wrapper that
137instantiates ddr2 models. This wrapper can be used to create UDIMM,
138RDIMM or SODIMM models. Other form factors are not supported
139(MiniDIMM, VLP DIMM, etc.). From the perspective of the model, the
140items that need to be defined are the number of ranks, the module
141type, and the presence of ECC. All combinations of ranks, module
142type, and ECC are considered valid by the ddr2_module model even
143though a Micron part may not exist for every combination.
144**********************************************************************
145
146Defining the Number of Ranks on a module:
147----------------------------------------
148The verilog compiler directive "`define" may be used to choose between
149single, dual, and quad rank module configurations. The default is single
150rank if nothing is defined. Dual rank configuration can be selected by
151defining "DUAL_RANK" when the ddr2_module is compiled. Quad rank
152configuration can be selected by defining "QUAD_RANK" when the ddr2_module
153is compiled. The following are examples of defining a dual rank module
154configuration.
155
156    simulator command line
157    --------- ------------
158    ModelSim vlog +define+DUAL_RANK ddr2.v ddr2_module.v
159    NC-Verilog ncverilog +define+DUAL_RANK ddr2.v ddr2_module.v
160    VCS vcs +define+DUAL_RANK ddr2.v ddr2_module.v
161
162Defining the Module Type:
163-----------------------------------
164The verilog compiler directive "`define" may be used to choose between
165UDIMM, RDIMM, and SODIMM module configurations. The default is
166unregistered (UDIMM) if nothing is defined. SODIMM configuration can be
167selected by defining "SODIMM" when the ddr2_module is compiled. Registered
168configuration can be selected by defining "RDIMM" when the ddr2_module is
169compiled. The following are examples of defining a registered module
170configuration.
171
172    simulator command line
173    --------- ------------
174    ModelSim vlog +define+RDIMM ddr2.v ddr2_module.v
175    NC-Verilog ncverilog +define+RDIMM ddr2.v ddr2_module.v
176    VCS vcs +define+RDIMM ddr2.v ddr2_module.v
177
178Defining the ECC for a module:
179-----------------------------
180The verilog compiler directive "`define" may be used to choose between
181ECC and nonECC module configurations. The default is nonECC if nothing
182is defined. ECC configuration can be selected by defining "ECC" when
183the ddr2_module is compiled. The following are examples of defining an
184ECC module configuration.
185
186    simulator command line
187    --------- ------------
188    ModelSim vlog +define+ECC ddr2.v ddr2_module.v
189    NC-Verilog ncverilog +define+ECC ddr2.v ddr2_module.v
190    VCS vcs +define+ECC ddr2.v ddr2_module.v
191

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