Root/sim/verilog/micron_mobile_ddr/1024Mb_mobile_ddr_parameters.vh

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24* Copyright 2005 Micron Technology, Inc. All rights reserved.
25*
26*
27* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
28* Added ROW_BITS & BA_BITS for compatibility w/our system.
29* Removed part size parameter.
30*
31****************************************************************************************/
32
33    // Parameters current with 1024Mb datasheet rev C (10/02/07)
34    // 04.17.08 - Consolidated 1024Mb and T48M designs; Updated to rev E (03/08)
35    // 12.10.08 - Updated to datasheet rev G (07/08)
36
37
38                                          // SYMBOL UNITS DESCRIPTION
39                                          // ------ ----- -----------
40`ifdef sg5 // Timing Parameters for -5 (CL = 3)
41    parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
42    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
43    parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
44    parameter tCK3_min = 5.0; // tCK ns Nominal Clock Cycle Time
45    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
46    parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
47    parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
48    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
49    parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
50    parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
51    parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
52    parameter tRP = 15.0; // tRP ns Precharge command period
53    parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
54    parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
55    parameter tXP = 10.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
56`else `ifdef sg54 // Timing Parameters for -6 (CL = 3)
57    parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
58    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
59    parameter tCK = 5.4; // tCK ns Nominal Clock Cycle Time
60    parameter tCK3_min = 5.4; // tCK ns Nominal Clock Cycle Time
61    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
62    parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
63    parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
64    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
65    parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
66    parameter tRC = 58.2; // tRC ns Active to Active/Auto Refresh command time
67    parameter tRCD = 16.2; // tRCD ns Active to Read/Write command time
68    parameter tRP = 16.2; // tRP ns Precharge command period
69    parameter tRRD = 10.8; // tRRD ns Active bank a to Active bank b command time
70    parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
71    parameter tXP = 10.8; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
72`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
73    parameter tAC3_max = 5.5; // tAC ns Access window of DQ from CK/CK#
74    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
75    parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
76    parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
77    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
78    parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
79    parameter tHZ3_max = 5.5; // tHZ ns Data-out high Z window from CK/CK#
80    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
81    parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
82    parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
83    parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
84    parameter tRP = 18.0; // tRP ns Precharge command period
85    parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
86    parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
87    parameter tXP = 12.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
88`else `define sg75 // Timing Parameters for -75 (CL = 3)
89    parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
90    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
91    parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
92    parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
93    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
94    parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
95    parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
96    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
97    parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
98    parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time
99    parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
100    parameter tRP = 22.5; // tRP ns Precharge command period
101    parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
102    parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
103    parameter tXP = 15.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
104`endif `endif `endif
105
106    parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
107    parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
108    parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
109    parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
110    parameter tRFC = 110.0; // tRFC ns Refresh to Refresh Command interval time
111    parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command Note: model adds CL to this value
112    parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command
113    parameter tWR = 15.0; // tWR ns Write recovery time
114    parameter tCH_MAX = 0.55; // Clk high level width
115    parameter tCH_MIN = 0.45; // Clk high level width
116    parameter tCL_MAX = 0.55; // Clk low level width
117    parameter tCL_MIN = 0.45; // Clk low level width
118    parameter tCKE = 1.0 ; // Minimum tCKE High/Low time (in tCK's)
119    parameter CL_MAX = 3 ; // Maximum CAS Latency
120    parameter BL_MAX = 16 ;
121
122
123
124
125     // Size Parameters based on Part Width
126`ifdef x16
127    parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
128    parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
129    parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
130    parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
131    parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
132    parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
133    parameter BA_BITS = 2; // Set this parameter to control how many Bank bits are used
134`else `define x32
135  `ifdef RP // reduced page mode
136    parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
137    parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
138    parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
139    parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
140    parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
141    parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
142    parameter BA_BITS = 2; // Bank bits
143  `else
144    parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
145    parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
146    parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
147    parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
148    parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
149    parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
150    parameter BA_BITS = 2; // Bank bits
151  `endif
152`endif
153
154    // For use with the Multi Chip Package
155`ifdef DUAL_RANK
156    parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
157    parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
158`else
159    parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
160    parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
161`endif
162
163    parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
164    parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
165    parameter part_size = 1024; // Set this parameter to indicate part size(1024Mb, 512Mb, 256Mb, 128Mb)
166    
167
168

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