Root/sim/verilog/micron_mobile_ddr/128Mb_mobile_ddr_parameters.vh

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24* Copyright 2005 - 2006 Micron Technology, Inc. All rights reserved.
25*
26*
27* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK - fixed.
28* Added ROW_BITS & BA_BITS for compatibility w/our system.
29* Also changed Col bits from 10 to 9 per spec.
30* Removed x32 option and part size parameter.
31*
32****************************************************************************************/
33
34    // Parameters current with 128Mb datasheet rev J (11/05)
35    // 04.17.08 - Parameters current with 128Mb Data sheet rev A (04/08)
36
37    // Timing parameters based on Speed Grade
38
39                                          // SYMBOL UNITS DESCRIPTION
40                                          // ------ ----- -----------
41`ifdef sg5 // Timing Parameters for -5 (CL = 3)
42    parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
43    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
44    parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
45    parameter tCK3_min = 5.0; // tCK ns Nominal Clock Cycle Time
46    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
47    parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
48    parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
49    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
50    parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
51    parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
52    parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
53    parameter tRP = 15.0; // tRP ns Precharge command period
54    parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
55    parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
56    parameter tXP = 5.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
57`else `ifdef sg54 // Timing Parameters for -6 (CL = 3)
58    parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
59    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
60    parameter tCK = 5.4; // tCK ns Nominal Clock Cycle Time
61    parameter tCK3_min = 5.4; // tCK ns Nominal Clock Cycle Time
62    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
63    parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
64    parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
65    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
66    parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
67    parameter tRC = 58.2; // tRC ns Active to Active/Auto Refresh command time
68    parameter tRCD = 16.2; // tRCD ns Active to Read/Write command time
69    parameter tRP = 16.2; // tRP ns Precharge command period
70    parameter tRRD = 10.8; // tRRD ns Active bank a to Active bank b command time
71    parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
72    parameter tXP = 5.4; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
73`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
74    parameter tAC3_max = 5.5; // tAC ns Access window of DQ from CK/CK#
75    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
76    parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
77    parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
78    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
79    parameter tDQSQ = 0.50; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
80    parameter tHZ3_max = 5.5; // tHZ ns Data-out high Z window from CK/CK#
81    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
82    parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
83    parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
84    parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
85    parameter tRP = 18.0; // tRP ns Precharge command period
86    parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
87    parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
88    parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
89`else `define sg75 // Timing Parameters for -75 (CL = 3)
90    parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
91    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
92    parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
93    parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
94    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
95    parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
96    parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
97    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
98    parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
99    parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time
100    parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
101    parameter tRP = 22.5; // tRP ns Precharge command period
102    parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
103    parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
104    parameter tXP = 7.5; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
105`endif `endif `endif
106
107    parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
108    parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
109    parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
110    parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
111    parameter tRFC = 80.0; // tRFC ns Refresh to Refresh Command interval time
112    parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb Parts)
113    parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command (Not Applicable for 128Mb, 256Mb Parts)
114    parameter tWR = 15.0; // tWR ns Write recovery time
115
116    // Size Parameters based on Part Width
117`ifdef x16
118    parameter ADDR_BITS = 12; // Set this parameter to control how many Address bits are used
119    parameter ROW_BITS = 12; // Set this parameter to control how many Row bits are used
120    parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
121    parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
122    parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
123    parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
124    parameter BA_BITS = 2; // Bank bits
125`else `define x32
126    parameter ADDR_BITS = 12; // Set this parameter to control how many Address bits are used
127    parameter ROW_BITS = 12; // Set this parameter to control how many Row bits are used
128    parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
129    parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
130    parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
131    parameter COL_BITS = 8; // Set this parameter to control how many Column bits are used
132    parameter BA_BITS = 2; // Bank bits
133`endif
134
135    // For use with the Multi Chip Package
136`ifdef DUAL_RANK
137    parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
138    parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
139`else
140    parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
141    parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
142`endif
143
144    parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
145    parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
146    parameter part_size = 128; // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
147    parameter tCH_MAX = 0.55; // Clk high level width
148    parameter tCH_MIN = 0.45; // Clk high level width
149    parameter tCL_MAX = 0.55; // Clk low level width
150    parameter tCL_MIN = 0.45; // Clk low level width
151    parameter tCKE = 2.0; // Minimum tCKE High/Low time (in tCK's)
152    parameter CL_MAX = 3; // Maximum CAS Latency
153    parameter BL_MAX = 16 ;
154

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