Root/sim/verilog/micron_mobile_ddr/2048Mb_mobile_ddr_parameters.vh

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24* Copyright 2005 Micron Technology, Inc. All rights reserved.
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26*
27* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
28* Added ROW_BITS & BA_BITS for compatibility w/our system.
29* Removed part size parameter.
30*
31****************************************************************************************/
32
33    // Parameters current with 2048Mb LPDDR SDRAM
34    // 04.26.10 - Based on Rev 0.7 04/09EN (DDS)
35
36
37                                          // SYMBOL UNITS DESCRIPTION
38                                          // ------ ----- -----------
39`ifdef sg5 // Timing Parameters for -5 (CL = 3)
40    parameter tAC3_max = 4.8; // tAC ns Access window of DQ from CK/CK#
41    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
42    parameter tCK = 4.8; // tCK ns Nominal Clock Cycle Time
43    parameter tCK3_min = 4.8; // tCK ns Nominal Clock Cycle Time
44    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
45    parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
46    parameter tHZ3_max = 4.8; // tHZ ns Data-out high Z window from CK/CK#
47    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
48    parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
49    parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
50    parameter tRCD = 14.4; // tRCD ns Active to Read/Write command time
51    parameter tRP = 14.4; // tRP ns Precharge command period
52    parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
53    parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
54    parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
55    parameter tWR = 14.4; // tWR ns Write recovery time
56`else `ifdef sg54 // Timing Parameters for -6 (CL = 3)
57    parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
58    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
59    parameter tCK = 5.4; // tCK ns Nominal Clock Cycle Time
60    parameter tCK3_min = 5.4; // tCK ns Nominal Clock Cycle Time
61    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
62    parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
63    parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
64    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
65    parameter tRAS = 41.8; // tRAS ns Active to Precharge command time
66    parameter tRC = 58.2; // tRC ns Active to Active/Auto Refresh command time
67    parameter tRCD = 16.2; // tRCD ns Active to Read/Write command time
68    parameter tRP = 16.2; // tRP ns Precharge command period
69    parameter tRRD = 10.8; // tRRD ns Active bank a to Active bank b command time
70    parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
71    parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
72    parameter tWR = 15.0; // tWR ns Write recovery time
73`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
74    parameter tAC3_max = 5.5; // tAC ns Access window of DQ from CK/CK#
75    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
76    parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
77    parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
78    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
79    parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
80    parameter tHZ3_max = 5.5; // tHZ ns Data-out high Z window from CK/CK#
81    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
82    parameter tRAS = 41.8; // tRAS ns Active to Precharge command time
83    parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
84    parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
85    parameter tRP = 18.0; // tRP ns Precharge command period
86    parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
87    parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
88    parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
89    parameter tWR = 15.0; // tWR ns Write recovery time
90`else `define sg75 // Timing Parameters for -75 (CL = 3)
91    parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
92    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
93    parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
94    parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
95    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
96    parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
97    parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
98    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
99    parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
100    parameter tRC = 67.5; // tRC ns Active to Active/Auto Refresh command time
101    parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
102    parameter tRP = 22.5; // tRP ns Precharge command period
103    parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
104    parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
105    parameter tXP = 7.50; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
106    parameter tWR = 15.0; // tWR ns Write recovery time
107`endif `endif `endif
108
109    parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
110    parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
111    parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
112    parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
113    parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
114    parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command Note: model adds CL to this value
115    parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command
116    parameter tCH_MAX = 0.55; // Clk high level width
117    parameter tCH_MIN = 0.45; // Clk high level width
118    parameter tCL_MAX = 0.55; // Clk low level width
119    parameter tCL_MIN = 0.45; // Clk low level width
120    parameter tCKE = 1.0 ; // Minimum tCKE High/Low time (in tCK's)
121    parameter CL_MAX = 3 ; // Maximum CAS Latency
122    parameter BL_MAX = 16 ;
123
124
125
126
127     // Size Parameters based on Part Width
128`ifdef x16
129    `ifdef RP
130        parameter ADDR_BITS = 15; // Set this parameter to control how many Address bits are used
131        parameter ROW_BITS = 15; // Set this parameter to control how many Row bits are used
132        parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
133        parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
134        parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
135        parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
136        parameter BA_BITS = 2; // Set this parameter to control how many Bank bits are used
137    `else
138        parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
139        parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
140        parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
141        parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
142        parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
143        parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
144        parameter BA_BITS = 2; // Set this parameter to control how many Bank bits are used
145    `endif
146`else `define x32
147    `ifdef RP // reduced page mode
148        parameter ADDR_BITS = 15; // Set this parameter to control how many Address bits are used
149        parameter ROW_BITS = 15; // Set this parameter to control how many Row bits are used
150        parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
151        parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
152        parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
153        parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
154        parameter BA_BITS = 2; // Bank bits
155    `else
156        parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
157        parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
158        parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
159        parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
160        parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
161        parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
162        parameter BA_BITS = 2; // Bank bits
163    `endif
164`endif
165
166    // For use with the Multi Chip Package
167`ifdef DUAL_RANK
168    parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
169    parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
170`else
171    parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
172    parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
173`endif
174
175    parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
176    parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
177    parameter part_size = 2048; // Set this parameter to indicate part size(1024Mb, 512Mb, 256Mb, 128Mb)
178    
179
180

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