Root/sim/verilog/micron_mobile_ddr/256Mb_mobile_ddr_parameters.vh

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24* Copyright 2005 Micron Technology, Inc. All rights reserved.
25*
26*
27* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
28* Added ROW_BITS & BA_BITS for compatibility w/our system.
29* Also changed x16 Col bits from 8 to 9 per spec.
30* Removed part size parameter.
31*
32****************************************************************************************/
33
34    // Parameters current with 256Mb datasheet rev E (05/07)
35    // 04.17.08 - Parameters current with 256Mb Data sheet rev H (03/08)
36
37    // Timing parameters based on Speed Grade
38
39                                          // SYMBOL UNITS DESCRIPTION
40                                          // ------ ----- -----------
41`ifdef sg6 // Timing Parameters for -6 (CL = 3)
42    parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
43    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
44    parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
45    parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
46    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
47    parameter tDQSQ = 0.50; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
48    parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
49    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
50    parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
51    parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
52    parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
53    parameter tRP = 18.0; // tRP ns Precharge command period
54    parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
55    parameter tWR = 12.0; // tWR ns Write recovery time
56    parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
57    parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd
58`else `define sg75 // Timing Parameters for -75 (CL = 3)
59    parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
60    parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
61    parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
62    parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
63    parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
64    parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
65    parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
66    parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
67    parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
68    parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time
69    parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
70    parameter tRP = 22.5; // tRP ns Precharge command period
71    parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
72    parameter tWR = 15.0; // tWR ns Write recovery time
73    parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
74    parameter tXP = 7.5; // tXP ns Exit power-down to first valid cmd
75`endif
76
77    parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
78    parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
79    parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
80    parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
81    parameter tRFC = 70.0; // tRFC ns Refresh to Refresh Command interval time
82    parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
83    parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
84
85    // Size Parameters based on Part Width
86`ifdef x16
87    parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
88    parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
89    parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
90    parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
91    parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
92    parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
93    parameter BA_BITS = 2; // Bank bits
94`else `define x32
95    `ifdef RP
96    parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
97    parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
98    parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
99    parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
100    parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
101    parameter COL_BITS = 8; // Set this parameter to control how many Column bits are used
102    parameter BA_BITS = 2; // Bank bits
103    `else
104    parameter ADDR_BITS = 12; // Set this parameter to control how many Address bits are used
105    parameter ROW_BITS = 12; // Set this parameter to control how many Row bits are used
106    parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
107    parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
108    parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
109    parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
110    parameter BA_BITS = 2; // Bank bits
111    `endif
112`endif
113
114    // For use with the Multi Chip Package
115`ifdef DUAL_RANK
116    parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
117    parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
118`else
119    parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
120    parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
121`endif
122
123    parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
124    parameter part_mem_bits = 10; // For fast sim load
125    parameter part_size = 256; // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
126    parameter tCH_MAX = 0.55; // Clk high level width
127    parameter tCH_MIN = 0.45; // Clk high level width
128    parameter tCL_MAX = 0.55; // Clk low level width
129    parameter tCL_MIN = 0.45; // Clk low level width
130    parameter tCKE = 2.0; // Minimum tCKE High/Low time (in tCK's)
131    parameter CL_MAX = 3; // Maximum CAS Latency
132    parameter BL_MAX = 16;
133
134
135

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