Root/sim/verilog/micron_mobile_ddr/readme.txt

1Disclaimer of Warranty:
2-----------------------
3This software code and all associated documentation, comments or other
4information (collectively "Software") is provided "AS IS" without
5warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
6DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
7TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
8OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
9WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
10OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
11FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
12THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
13ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
14OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
15ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
16INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
17WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
18OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
19THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
20DAMAGES. Because some jurisdictions prohibit the exclusion or
21limitation of liability for consequential or incidental damages, the
22above limitation may not apply to you.
23
24Copyright 2008 Micron Technology, Inc. All rights reserved.
25
26Getting Started:
27----------------
28Unzip the included files to a folder.
29Compile mobile_ddr.v and tb.v using a verilog simulator.
30Simulate the top level test bench tb.
31Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
32
33File Descriptions:
34------------------
35mobile_ddr.v --mobile ddr model
36mobile_ddr_mcp.v --structural wrapper for mobile_ddr multi-chip package model
37128Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
38256Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
39512Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
401024Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
412048Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
42readme.txt --This file
43tb.v --Test bench
44tb.do --File that compiles and runs the above files
45
46Defining the Density (part size):
47-------------------------
48The verilog compiler directive "`define" may be used to choose between on of the
49densities supported by the mobile ddr model. Allowable densities are listed in
50the *.vh file. The density is used to select a set of bank, row, column, and timing
51parameters for the mobile ddr model. The following are examples of defining
52the density.
53
54    simulator command line
55    --------- ------------
56    ModelSim vlog +define+den512Mb mobile_ddr.v
57    VCS vcs +define+den512Mb mobile_ddr.v
58    NC-Verilog ncverilog +define+den512Mb mobile_ddr.v
59
60
61Defining the Speed Grade:
62-------------------------
63The verilog compiler directive "`define" may be used to choose between
64multiple speed grades supported by the mobile ddr model. Allowable speed
65grades are listed in the mobile_ddr_parameters.vh file and begin with the
66letters "sg". The speed grade is used to select a set of timing
67parameters for the mobile ddr model. The following are examples of defining
68the speed grade.
69
70    simulator command line
71    --------- ------------
72    ModelSim vlog +define+sg75 mobile_ddr.v
73    VCS vcs +define+sg75 mobile_ddr.v
74    NC-Verilog ncverilog +define+sg75 mobile_ddr.v
75
76
77Defining the Organization:
78--------------------------
79The verilog compiler directive "`define" may be used to choose between
80multiple organizations supported by the mobile ddr model. Valid
81organizations include "x16" and "x32", and are listed in the
82mobile_ddr_parameters.vh file. The organization is used to select the amount
83of memory and the port sizes of the mobile ddr model. The following are
84examples of defining the organization.
85
86    vlog +define+x16 mobile_ddr.v
87    simulator command line
88    --------- ------------
89    ModelSim vlog +define+x16 mobile_ddr.v
90    VCS vcs +define+x16 mobile_ddr.v
91    NC-Verilog ncverilog +define+x16 mobile_ddr.v
92
93All combinations of speed grade and organization are considered valid
94by the mobile ddr model even though a Micron part may not exist for every
95combination.
96
97Allocating Memory:
98------------------
99An associative array has been implemented to reduce the amount of
100static memory allocated by the mobile ddr model. The number of
101entries in the associative array is controlled by the part_mem_bits
102parameter, and is equal to 2^part_mem_bits. For example, if the
103part_mem_bits parameter is equal to 10, the associative array will be
104large enough to store 1024 write data transfers to unique addresses.
105The following are examples of setting the MEM_BITS parameter to 8.
106
107    simulator command line
108    --------- ------------
109    ModelSim vsim -Gpart_mem_bits=8 mobile_ddr
110    VCS vcs -pvalue+part_mem_bits=8 mobile_ddr.v
111    NC-Verilog ncverilog +defparam+mobile_ddr.part_mem_bits=8 mobile_ddr.v
112
113It is possible to allocate memory for every address supported by the
114mobile ddr model by using the verilog compiler directive "`define FULL_MEM".
115This procedure will improve simulation performance at the expense of
116system memory. The following are examples of allocating memory for
117every address.
118
119    Simulator command line
120    --------- ------------
121    ModelSim vlog +define+FULL_MEM mobile_ddr.v
122    VCS vcs +define+FULL_MEM mobile_ddr.v
123    NC-Verilog ncverilog +define+FULL_MEM mobile_ddr.v
124
125
126Reduced Page Mode:
127------------------
128Mobile DDR 256Mb, 512Mb, and 1024Mb part may be built with the reduced page size
129architecture. This part is accessed with the +define+RP designator. RP
130parts have one extra row bit and one less column bit effectively cutting
131the page size in half but doubling the number of rows keeping total part
132size the same.
133
134    Part Size Valid RP Designators
135    --------- --------------------
136    256Mb +define+RP
137    512Mb +define+RP
138    1024Mb +define+RP
139
140    Simulator command line
141    --------- ------------
142    ModelSim vlog +define+RP mobile_ddr.v
143    VCS vcs +define+RP mobile_ddr.v
144    NC-Verilog ncverilog +define+RP mobile_ddr.v
145
146Multi-Chip Package Model:
147-------------------------
148The 1024Mb model can be supported in a Multi Chip Package, that allows
149multiple die models in one structural package. The number of ranks and
150chip selects of the mcp can be configured by using the `DUAL_RANK define
151on the simulator call line. The currently supported configurations are
152listed below:
153
154    Package Configuration Valid MCP Designator
155    --------------------- --------------------
156    2 Chip Selects, 2 Die +define+DUAL_RANK
157    2 Chip Selects, 1 Die (default)
158
159The single rank mcp is the default. In order to simulate the DUAL_RANK
160model, the define needs to be added:
161
162    Simulator command line
163    --------- ------------
164    ModelSim vlog +define+DUAL_RANK mobile_ddr.v mobile_ddr_mcp.v
165    VCS vcs +define+DUAL_RANK mobile_ddr.v mobile_ddr_mcp.v
166    NC-Verilog ncverilog +define+DUAL_RANK mobile_ddr.v mobile_ddr_mcp.v
167
168

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