Root/sim/verilog/micron_mobile_ddr/subtest.vh

1initial begin:test
2    //ck <= 1'b0;
3    cke <= 1'b0;
4    cs_n <= 1'bz;
5    ras_n <= 1'bz;
6    cas_n <= 1'bz;
7    we_n <= 1'bz;
8    a <= {ADDR_BITS{1'bz}};
9    ba <= {BA_BITS{1'bz}};
10    dq_en <= 1'b0;
11    dqs_en <= 1'b0;
12    power_up;
13    nop (10); // wait 10 clocks intead of 200 us for simulation purposes
14    precharge('h00000000, 1);
15    nop(trp);
16    refresh;
17    nop(trfc);
18    refresh;
19    nop(trfc);
20    load_mode('h0, 'h00000032);
21    nop(tmrd);
22    load_mode('h2, 'h00004000);
23    nop(tmrd);
24    activate('h00000000, 'h00000000);
25    nop(trcd-1);
26    write('h00000000, 'h00000000, 0, { {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}}, { 16'h3000, 16'h2000, 16'h1000, 16'h0});
27    nop(bl/2+twr);
28    read('h00000000, 'h00000000, 1);
29    nop(bl/2-1);
30    nop('h00000014);
31    test_done;
32end
33

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