Xué video camera

Xué video camera Git Source Tree

Root/xue-rnc/expansion.sch

1	EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT
2	LIBS:power
3	LIBS:r_pack2
4	LIBS:v0402mhs03
5	LIBS:usb-48204-0001
6	LIBS:microsmd075f
7	LIBS:mic2550
8	LIBS:rj45-48025
9	LIBS:xue-nv
10	LIBS:xc6slx75fgg484
11	LIBS:xc6slx45fgg484
12	LIBS:micron_mobile_ddr
13	LIBS:micron_ddr_512Mb
14	LIBS:k8001
15	LIBS:device
16	LIBS:transistors
17	LIBS:conn
18	LIBS:linear
19	LIBS:regul
20	LIBS:74xx
21	LIBS:cmos4000
22	LIBS:adc-dac
23	LIBS:memory
24	LIBS:xilinx
25	LIBS:special
26	LIBS:microcontrollers
27	LIBS:dsp
28	LIBS:microchip
29	LIBS:analog_switches
30	LIBS:motorola
31	LIBS:texas
32	LIBS:intel
33	LIBS:audio
34	LIBS:interface
35	LIBS:digital-audio
36	LIBS:philips
37	LIBS:display
38	LIBS:cypress
39	LIBS:siliconi
40	LIBS:opto
41	LIBS:atmel
42	LIBS:contrib
43	LIBS:valves
44	LIBS:pasives-connectors
45	LIBS:x25x64mb
46	LIBS:attiny
47	LIBS:PSU
48	LIBS:tps793xx
49	LIBS:reg102
50	LIBS:mt9m033
51	LIBS:m12-tu400a
52	LIBS:ft2232c
53	LIBS:fxo-hc536r
54	LIBS:zx62d-b-5p8
55	LIBS:a7130
56	EELAYER 24 0
57	EELAYER END
58	$Descr A4 11700 8267
59	Sheet 9 9
60	Title ""
61	Date "31 dec 2010"
62	Rev ""
63	Comp ""
64	Comment1 ""
65	Comment2 ""
66	Comment3 ""
67	Comment4 ""
68	$EndDescr
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315	Wire Wire Line
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317	Wire Wire Line
318	9850 3300 10700 3300
319	Wire Wire Line
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323	Wire Wire Line
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325	Wire Wire Line
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327	Wire Wire Line
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329	Wire Wire Line
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331	Wire Wire Line
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333	Wire Wire Line
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335	Wire Wire Line
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337	Wire Wire Line
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339	Wire Wire Line
340	6400 4550 5500 4550
341	Wire Wire Line
342	7200 4450 8100 4450
343	$Comp
344	L CONN_25X2 P1
345	U 1 1 4CBAFE50
346	P 6800 3550
347	F 0 "P1" H 6800 4850 60 0000 C CNN
348	F 1 "CONN_25X2" V 6800 3550 50 0000 C CNN
349	F 2 "header25x2_smd_2mm" H 6740 4910 60 0001 C CNN
350	1 6800 3550
351	1 0 0 -1
352	$EndComp
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405	Text Label 5500 3450 0 60 ~ 0
406	FPGA_BANK0_IO_39
407	Text Label 9844 3400 0 60 ~ 0
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409	Text Label 9844 6800 0 60 ~ 0
410	FPGA_BANK0_IO_35
411	Text Label 7244 4350 0 60 ~ 0
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724	2550 4750 2650 4850
725	Entry Wire Line
726	2550 4650 2650 4750
727	Text Label 1650 5050 0 60 ~ 0
728	FPGA_BANK0_IO_36
729	Text Label 1650 4850 0 60 ~ 0
730	FPGA_BANK0_IO_34
731	Text Label 1650 4950 0 60 ~ 0
732	FPGA_BANK0_IO_35
733	Entry Wire Line
734	2550 4950 2650 5050
735	Entry Wire Line
736	2550 5050 2650 5150
737	Entry Wire Line
738	2550 4850 2650 4950
739	Entry Wire Line
740	2850 2950 2950 2850
741	Entry Wire Line
742	2850 2850 2950 2750
743	Entry Wire Line
744	2850 2750 2950 2650
745	Entry Wire Line
746	2850 2650 2950 2550
747	Entry Wire Line
748	2850 2550 2950 2450
749	Entry Wire Line
750	2850 2450 2950 2350
751	Entry Wire Line
752	2850 2350 2950 2250
753	Entry Wire Line
754	2850 2250 2950 2150
755	Entry Wire Line
756	2850 2150 2950 2050
757	$EndSCHEMATC
758

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