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Jul 24, 2010
13 years 5 months initial import
Commit d6f7c20935a5b135f60f19004dd31bf3b288272f, by Andrés Calderón
13 years 5 months xue logo added
Commit 450366b113d73a949d80e313ce45b372e435d362, by Andrés Calderón
13 years 5 months xue logo added
Commit 5761bbd5591d34ffcaf5ac44c4b59b978a0e59d2, by Andrés Calderón
13 years 5 months chie renamed to xue
Commit a8cbac05c9901b52e5ff0e412dbfef2ed1f5eb25, by Andrés Calderón
Jul 28, 2010
13 years 4 months some ethernet phy conections
Commit d79faef060649603eff2d3bc0fb4a03a7b90fcc2, by Andrés Calderón
13 years 4 months some ethernet phy conections
Commit 939c04d645b734c8a030217adfcf0649fbf2e116, by Andrés Calderón
13 years 4 months only one wire connected
Commit 1580e66a1e7062cd57e2e43fe1df26fa8e081de1, by Andrés Calderón
Aug 4, 2010
13 years 4 months micron ddr ibis model added
Commit f386b0178db5a0cd485cbc40248f22830e757281, by Andrés Calderón
13 years 4 months micron_ddr_512Mb models added
Commit 55284358c3b370b94d53efcd57d55aa65894a499, by Andrés Calderón
13 years 4 months micron_ddr_512Mb.lib fixed
Commit a29352d9974d75a44b819d01c9695eda97e066fd, by Andrés Calderón
13 years 4 months 60fbga_ddr.fpd added
Commit d6bbd2dcbaa48bee5e38ee322a747e5754b2ff13, by Andrés Calderón
13 years 4 months 60fbga_ddr.mod added
Commit 1e0102079efd6254eef7efb4bae847d40291c11a, by Andrés Calderón
13 years 4 months ddr mobile replaced by ddr
Commit 3e25e8dec9a1d2c721cbf0bf1d7a6833e314684c, by Andrés Calderón
Aug 5, 2010
13 years 4 months ddr address and data has been conected to the FPGA
Commit 5197a479534892ae7ac2d9ab28183404c12f1742, by Andrés Calderón
Aug 8, 2010
13 years 4 months Phy
Commit 5ce4404765346bc894315eccbe3f6d35ab936c3f, by Juan64Bits
Aug 9, 2010
13 years 4 months USB and MICROSD footprints added
Commit 0d12fb26f4bcb7bf330022fcd76943a0ea40b75c, by Juan64Bits
13 years 4 months borrando basura
Commit 9fa83a71a679ebbd00ea6aa15aed56c22250aa38, by Andrés Calderón
13 years 4 months cleanup
Commit bd2d314d9cb223cb5bc56549ea19ed890c6cdfa1, by Andrés Calderón
13 years 4 months more fpga ddr lines has been connected
Commit 3678b1cf050f1411444cfc117ea271de174d8639, by Andrés Calderón
13 years 4 months pasive footprint added
Commit 675d06abe3b247cff7b80c23811ea4a068dce82c, by Andrés Calderón

Development Team
Admins
Carlos Camargo
Juan Florez
Andrés Calderón
Happy Crew
Wolfgang Spraul
Adam Wang
Werner Almesberger



interactive